From: Mao Han <han_mao@c-sky.com>
To: Palmer Dabbelt <palmer@sifive.com>
Cc: linux-riscv@lists.infradead.org, guoren@kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/3] riscv: Add support for perf registers sampling
Date: Mon, 29 Apr 2019 16:42:05 +0800 [thread overview]
Message-ID: <20190429084204.GB22718@vmh-VirtualBox> (raw)
In-Reply-To: <mhng-0787435f-0b2c-4ab4-ad73-0b68a815e613@palmer-si-x1e>
On Thu, Apr 25, 2019 at 02:11:02PM -0700, Palmer Dabbelt wrote:
> On Thu, 11 Apr 2019 00:53:49 PDT (-0700), han_mao@c-sky.com wrote:
> >+ PERF_REG_RISCV_S10,
> >+ PERF_REG_RISCV_S11,
> >+ PERF_REG_RISCV_T3,
> >+ PERF_REG_RISCV_T4,
> >+ PERF_REG_RISCV_T5,
> >+ PERF_REG_RISCV_T6,
> >+ PERF_REG_RISCV_MAX,
> >+};
>
> Is it expected this eventually supports floating-point and vector registers?
> If so, how do we make this extensible?
>
It seems none of current architecture put their fp/vfp registers into this
file, gpr is normally enough for backtrace and context restoration. I'm not
quite understand the problem of extensible. All modification to this file
should be synchronzied as the perf tool is released with the kernel.
Thanks,
Mao Han
next prev parent reply other threads:[~2019-04-29 8:42 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-11 7:53 [PATCH 0/3] riscv: Add perf callchain support Mao Han
2019-04-11 7:53 ` [PATCH 1/3] " Mao Han
2019-04-11 14:24 ` Christoph Hellwig
2019-04-25 21:11 ` Palmer Dabbelt
2019-04-29 8:39 ` Mao Han
2019-04-11 7:53 ` [PATCH 2/3] riscv: Add support for perf registers sampling Mao Han
2019-04-25 21:11 ` Palmer Dabbelt
2019-04-29 8:42 ` Mao Han [this message]
2019-04-11 7:53 ` [PATCH 3/3] riscv: Add support for libdw Mao Han
2019-04-25 21:11 ` Palmer Dabbelt
2019-04-29 8:45 ` Mao Han
2019-04-11 14:14 ` [PATCH 0/3] riscv: Add perf callchain support Christoph Hellwig
2019-04-12 9:38 ` [PATCH 2/3] riscv: Add support for perf registers sampling Mao Han
2019-04-13 8:01 ` Christoph Hellwig
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