From: Geert Uytterhoeven <geert+renesas@glider.be>
To: Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <marc.zyngier@arm.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Simon Horman <horms@verge.net.au>,
Magnus Damm <magnus.damm@gmail.com>,
Chris Brandt <chris.brandt@renesas.com>
Cc: devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
linux-kernel@vger.kernel.org,
Geert Uytterhoeven <geert+renesas@glider.be>
Subject: [PATCH 1/5] dt-bindings: interrupt-controller: Add Renesas RZ/A1 Interrupt Controller
Date: Mon, 29 Apr 2019 11:36:27 +0200 [thread overview]
Message-ID: <20190429093631.10799-2-geert+renesas@glider.be> (raw)
In-Reply-To: <20190429093631.10799-1-geert+renesas@glider.be>
Add DT bindings for the Renesas RZ/A1 Interrupt Controller.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
.../renesas,rza1-irqc.txt | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt
new file mode 100644
index 0000000000000000..0914d3d216c3bdac
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt
@@ -0,0 +1,27 @@
+DT bindings for the Renesas RZ/A1 Interrupt Controller
+
+The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas
+RZ/A1 SoCs:
+ - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI
+ interrupts,
+ - NMI edge select.
+
+Required properties:
+ - compatible: Must be "renesas,<soctype>-irqc", and "renesas,rza1-irqc" as
+ fallback.
+ Examples with soctypes are:
+ - "renesas,r7s72100-irqc" (RZ/A1H)
+ - #interrupt-cells: Must be 2 (an interrupt index and flags, as defined
+ in interrupts.txt in this directory)
+ - interrupt-controller: Marks the device as an interrupt controller
+ - reg: Base address and length of the memory resource used by the interrupt
+ controller
+
+Example:
+
+ irqc: interrupt-controller@fcfef800 {
+ compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0xfcfef800 0x6>;
+ };
--
2.17.1
next prev parent reply other threads:[~2019-04-29 9:36 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-29 9:36 [PATCH 0/5] ARM: rskrza1: Add RZ/A1 IRQC and input switches Geert Uytterhoeven
2019-04-29 9:36 ` Geert Uytterhoeven [this message]
2019-04-29 9:36 ` [PATCH 2/5] irqchip: Add Renesas RZ/A1 Interrupt Controller driver Geert Uytterhoeven
2019-04-29 10:06 ` Marc Zyngier
2019-04-29 11:21 ` Geert Uytterhoeven
2019-04-29 11:36 ` Marc Zyngier
2019-04-29 17:31 ` Chris Brandt
2019-04-29 12:25 ` Chris Brandt
2019-04-29 9:36 ` [PATCH 3/5] soc: renesas: Enable RZ/A1 IRQC on RZ/A1H Geert Uytterhoeven
2019-04-29 12:58 ` Simon Horman
2019-04-29 9:36 ` [PATCH 4/5] ARM: dts: r7s72100: Add IRQC device node Geert Uytterhoeven
2019-04-29 13:11 ` Simon Horman
2019-04-29 9:36 ` [PATCH 5/5] ARM: dts: rskrza1: Add input switches Geert Uytterhoeven
2019-04-29 12:21 ` [PATCH 0/5] ARM: rskrza1: Add RZ/A1 IRQC and " Chris Brandt
2019-04-29 12:49 ` Geert Uytterhoeven
2019-04-29 13:14 ` Chris Brandt
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