[PATCH v2] MIPS: Fix Ingenic SoCs sometimes reporting wrong ISA

From: Paul Cercueil <paul@crapouillou.net>
To: Ralf Baechle <ralf@linux-mips.org>,
	Paul Burton <paul.burton@mips.com>,
	James Hogan <jhogan@kernel.org>
Cc: od@zcrc.me, linux-mips@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Paul Cercueil <paul@crapouillou.net>
Subject: [PATCH v2] MIPS: Fix Ingenic SoCs sometimes reporting wrong ISA
Date: Wed,  8 May 2019 00:17:55 +0200	[thread overview]
Message-ID: <20190507221755.3396-1-paul@crapouillou.net> (raw)

The config0 register in the Xburst CPUs with a processor ID of
PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
but they don't actually support this ISA.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---

Notes:
    v2: Apply fix according to the PRID

 arch/mips/kernel/cpu-probe.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index d5e335e6846a..6126b77d5a62 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1973,6 +1973,14 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 		panic("Unknown Ingenic Processor ID!");
 		break;
 	}
+
+	/*
+	 * The config0 register in the Xburst CPUs with a processor ID of
+	 * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
+	 * but they don't actually support this ISA.
+	 */
+	if ((c->processor_id & PRID_COMP_MASK) == PRID_COMP_INGENIC_D0)
+		c->isa_level &= ~MIPS_CPU_ISA_M32R2;
 }
 
 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
-- 
2.21.0.593.g511ec345e18

