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From: Paul Cercueil <paul@crapouillou.net>
To: Ralf Baechle <ralf@linux-mips.org>,
	Paul Burton <paul.burton@mips.com>,
	James Hogan <jhogan@kernel.org>
Cc: od@zcrc.me, linux-mips@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Paul Cercueil <paul@crapouillou.net>
Subject: [PATCH 2/2] MIPS: Decode config3 register on Ingenic SoCs
Date: Wed,  8 May 2019 00:43:57 +0200	[thread overview]
Message-ID: <20190507224357.23778-2-paul@crapouillou.net> (raw)
In-Reply-To: <20190507224357.23778-1-paul@crapouillou.net>

XBurst misses a config2 register, so config3 decode was skipped in
decode_configs().

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
 arch/mips/kernel/cpu-probe.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index fdb73c1b0cd7..ed240cdfef46 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1960,9 +1960,17 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 {
 	decode_configs(c);
+
+	/*
+	 * XBurst misses a config2 register, so config3 decode was skipped in
+	 * decode_configs().
+	 */
+	decode_config3(c);
+
 	/* XBurst does not implement the CP0 counter. */
 	c->options &= ~MIPS_CPU_COUNTER;
 	BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
+
 	switch (c->processor_id & PRID_IMP_MASK) {
 	case PRID_IMP_XBURST:
 		c->cputype = CPU_XBURST;
-- 
2.21.0.593.g511ec345e18


  reply	other threads:[~2019-05-07 22:44 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-07 22:43 [PATCH 1/2] MIPS: Rename JZRISC to XBURST Paul Cercueil
2019-05-07 22:43 ` Paul Cercueil [this message]
2019-07-22 21:21   ` [PATCH 2/2] MIPS: Decode config3 register on Ingenic SoCs Paul Burton
2019-07-22 21:13 ` [PATCH 1/2] MIPS: Rename JZRISC to XBURST Paul Burton

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