From: Jerome Brunet <jbrunet@baylibre.com>
To: Neil Armstrong <narmstrong@baylibre.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: Jerome Brunet <jbrunet@baylibre.com>,
Kevin Hilman <khilman@baylibre.com>,
linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v2 3/7] clk: meson: axg: spread spectrum is on mpll2
Date: Mon, 13 May 2019 14:31:11 +0200 [thread overview]
Message-ID: <20190513123115.18145-4-jbrunet@baylibre.com> (raw)
In-Reply-To: <20190513123115.18145-1-jbrunet@baylibre.com>
After testing, it appears that the SSEN bit controls the spread
spectrum function on MPLL2, not MPLL0.
Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/clk/meson/axg.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 7a8ef80e5f2c..3ddd0efc9ee0 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -469,11 +469,6 @@ static struct clk_regmap axg_mpll0_div = {
.shift = 16,
.width = 9,
},
- .ssen = {
- .reg_off = HHI_MPLL_CNTL,
- .shift = 25,
- .width = 1,
- },
.misc = {
.reg_off = HHI_PLL_TOP_MISC,
.shift = 0,
@@ -568,6 +563,11 @@ static struct clk_regmap axg_mpll2_div = {
.shift = 16,
.width = 9,
},
+ .ssen = {
+ .reg_off = HHI_MPLL_CNTL,
+ .shift = 25,
+ .width = 1,
+ },
.misc = {
.reg_off = HHI_PLL_TOP_MISC,
.shift = 2,
--
2.20.1
next prev parent reply other threads:[~2019-05-13 12:31 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-13 12:31 [PATCH v2 0/7] clk: meson: fix mpll jitter Jerome Brunet
2019-05-13 12:31 ` [PATCH v2 1/7] clk: meson: mpll: properly handle spread spectrum Jerome Brunet
2019-05-14 18:16 ` Martin Blumenstingl
2019-05-13 12:31 ` [PATCH v2 2/7] clk: meson: gxbb: no spread spectrum on mpll0 Jerome Brunet
2019-05-13 12:31 ` Jerome Brunet [this message]
2019-05-13 12:31 ` [PATCH v2 4/7] clk: meson: mpll: add init callback and regs Jerome Brunet
2019-05-13 12:31 ` [PATCH v2 5/7] clk: meson: g12a: add mpll register init sequences Jerome Brunet
2019-05-13 12:31 ` [PATCH v2 6/7] clk: meson: eeclk: add init regs Jerome Brunet
2019-05-13 12:31 ` [PATCH v2 7/7] clk: meson: g12a: add controller register init Jerome Brunet
2019-05-20 11:26 ` [PATCH v2 0/7] clk: meson: fix mpll jitter Jerome Brunet
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