From: Peter Zijlstra <peterz@infradead.org>
To: Raphael Gault <raphael.gault@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, mingo@redhat.com,
catalin.marinas@arm.com, will.deacon@arm.com, acme@kernel.org,
mark.rutland@arm.com
Subject: Re: [PATCH 4/6] arm64: pmu: Add hook to handle pmu-related undefined instructions
Date: Fri, 17 May 2019 09:10:18 +0200 [thread overview]
Message-ID: <20190517071018.GH2623@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20190516132148.10085-5-raphael.gault@arm.com>
On Thu, May 16, 2019 at 02:21:46PM +0100, Raphael Gault wrote:
> In order to prevent the userspace processes which are trying to access
> the registers from the pmu registers on a big.LITTLE environment we
> introduce a hook to handle undefined instructions.
>
> The goal here is to prevent the process to be interrupted by a signal
> when the error is caused by the task being scheduled while accessing
> a counter, causing the counter access to be invalid. As we are not able
> to know efficiently the number of counters available physically on both
> pmu in that context we consider that any faulting access to a counter
> which is architecturally correct should not cause a SIGILL signal if
> the permissions are set accordingly.
The other approach is using rseq for this; with that you can guarantee
it will never issue the instruction on a wrong CPU.
That said; emulating the thing isn't horrible either.
> + /*
> + * We put 0 in the target register if we
> + * are reading from pmu register. If we are
> + * writing, we do nothing.
> + */
Wait _what_ ?!? userspace can _WRITE_ to these registers?
next prev parent reply other threads:[~2019-05-17 7:10 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-16 13:21 [RFC 0/6] arm64: Enable access to pmu registers by user-space Raphael Gault
2019-05-16 13:21 ` [PATCH 1/6] perf: arm64: Compile tests unconditionally Raphael Gault
2019-05-16 13:21 ` [PATCH 2/6] perf: arm64: Add test to check userspace access to hardware counters Raphael Gault
2019-05-16 13:21 ` [PATCH 3/6] arm64: pmu: Add function implementation to update event index in userpage Raphael Gault
2019-05-17 13:21 ` Mark Rutland
2019-05-16 13:21 ` [PATCH 4/6] arm64: pmu: Add hook to handle pmu-related undefined instructions Raphael Gault
2019-05-17 7:10 ` Peter Zijlstra [this message]
2019-05-17 7:35 ` Raphael Gault
2019-05-17 8:04 ` Mark Rutland
2019-05-17 8:26 ` Peter Zijlstra
2019-05-17 9:07 ` Peter Zijlstra
2019-05-16 13:21 ` [PATCH 5/6] arm64: perf: Enable pmu counter direct access for perf event on armv8 Raphael Gault
2019-05-16 13:21 ` [PATCH 6/6] Documentation: arm64: Document PMU counters access from userspace Raphael Gault
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190517071018.GH2623@hirez.programming.kicks-ass.net \
--to=peterz@infradead.org \
--cc=acme@kernel.org \
--cc=catalin.marinas@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=mingo@redhat.com \
--cc=raphael.gault@arm.com \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).