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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id a21sm9754032pjh.10.2019.06.04.15.59.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Jun 2019 15:59:33 -0700 (PDT) Date: Tue, 4 Jun 2019 15:59:31 -0700 From: Bjorn Andersson To: Stephen Boyd , vivek.gautam@codeaurora.org Cc: Andy Gross , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Sibi Sankar Subject: Re: [PATCH] arm64: dts: sdm845: Add iommus property to qup1 Message-ID: <20190604225931.GG4814@minitux> References: <20190604222939.195471-1-swboyd@chromium.org> <20190604223700.GE4814@minitux> <5cf6f4bb.1c69fb81.c39da.5496@mx.google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5cf6f4bb.1c69fb81.c39da.5496@mx.google.com> User-Agent: Mutt/1.12.0 (2019-05-25) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue 04 Jun 15:46 PDT 2019, Stephen Boyd wrote: > Quoting Bjorn Andersson (2019-06-04 15:37:00) > > On Tue 04 Jun 15:29 PDT 2019, Stephen Boyd wrote: > > > > > The SMMU that sits in front of the QUP needs to be programmed properly > > > so that the i2c geni driver can allocate DMA descriptors. Failure to do > > > this leads to faults when using devices such as an i2c touchscreen where > > > the transaction is larger than 32 bytes and we use a DMA buffer. > > > > > > > I'm pretty sure I've run into this problem, but before we marked the > > smmu bypass_disable and as such didn't get the fault, thanks. > > > > > arm-smmu 15000000.iommu: Unexpected global fault, this could be serious > > > arm-smmu 15000000.iommu: GFSR 0x00000002, GFSYNR0 0x00000002, GFSYNR1 0x000006c0, GFSYNR2 0x00000000 > > > > > > Add the right SID and mask so this works. > > > > > > Cc: Sibi Sankar > > > Signed-off-by: Stephen Boyd > > > --- > > > arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + > > > 1 file changed, 1 insertion(+) > > > > > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > > index fcb93300ca62..2e57e861e17c 100644 > > > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > > > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > > @@ -900,6 +900,7 @@ > > > #address-cells = <2>; > > > #size-cells = <2>; > > > ranges; > > > + iommus = <&apps_smmu 0x6c0 0x3>; > > > > According to the docs this stream belongs to TZ, the HLOS stream should > > be 0x6c3. > > Aye, I saw this line in the downstream kernel but it doesn't work for > me. If I specify <&apps_smmu 0x6c3 0x0> it still blows up. I wonder if > my firmware perhaps is missing some initialization here to make the QUP > operate in HLOS mode? Otherwise, I thought that the 0x3 at the end was > the mask and so it should be split off to the second cell in the DT > specifier but that seemed a little weird. > Both 0x3 and 0x6c3 are documented as the actual HLOS stream id, with mask of 0x0. Looping in Vivek as well. Regards, Bjorn