From: Stephen Boyd <sboyd@kernel.org>
To: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>, mturquette@baylibre.com
Cc: agross@kernel.org, david.brown@linaro.org,
bjorn.andersson@linaro.org, robh+dt@kernel.org,
mark.rutland@arm.com, marc.w.gonzalez@free.fr,
jcrouse@codeaurora.org, linux-arm-msm@vger.kernel.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Subject: Re: [PATCH 2/3] clk: qcom: Add MSM8998 GPU Clock Controller (GPUCC) driver
Date: Thu, 06 Jun 2019 16:00:49 -0700 [thread overview]
Message-ID: <20190606230050.2F33720645@mail.kernel.org> (raw)
In-Reply-To: <20190528164803.38642-1-jeffrey.l.hugo@gmail.com>
Quoting Jeffrey Hugo (2019-05-28 09:48:03)
> diff --git a/drivers/clk/qcom/gpucc-msm8998.c b/drivers/clk/qcom/gpucc-msm8998.c
> new file mode 100644
> index 000000000000..e45062e40718
> --- /dev/null
> +++ b/drivers/clk/qcom/gpucc-msm8998.c
> +
> +static int gpucc_msm8998_probe(struct platform_device *pdev)
> +{
> + struct regmap *regmap;
> + struct clk *xo;
> +
> + /*
> + * We must have a valid XO to continue until orphan probe defer is
> + * implemented.
> + */
> + xo = clk_get(&pdev->dev, "xo");
Why is this necessary?
> + if (IS_ERR(xo))
> + return PTR_ERR(xo);
> + clk_put(xo);
> +
> + regmap = qcom_cc_map(pdev, &gpucc_msm8998_desc);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + /* force periph logic on to acoid perf counter corruption */
avoid?
> + regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(13), BIT(13));
> + /* tweak droop detector (GPUCC_GPU_DD_WRAP_CTRL) to reduce leakage */
> + regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(0), BIT(0));
> +
> + return qcom_cc_really_probe(pdev, &gpucc_msm8998_desc, regmap);
> +}
> +
next prev parent reply other threads:[~2019-06-06 23:00 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-28 16:46 [PATCH 0/3] MSM8998 GPUCC Support Jeffrey Hugo
2019-05-28 16:47 ` [PATCH 1/3] dt-bindings: clock: Document gpucc for msm8998 Jeffrey Hugo
2019-06-06 23:27 ` Stephen Boyd
2019-05-28 16:48 ` [PATCH 2/3] clk: qcom: Add MSM8998 GPU Clock Controller (GPUCC) driver Jeffrey Hugo
2019-06-06 23:00 ` Stephen Boyd [this message]
2019-06-07 14:08 ` Jeffrey Hugo
2019-06-07 20:32 ` Stephen Boyd
2019-06-07 21:34 ` Jeffrey Hugo
2019-05-28 16:48 ` [PATCH 3/3] arm64: dts: qcom: msm8998: Add gpucc node Jeffrey Hugo
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190606230050.2F33720645@mail.kernel.org \
--to=sboyd@kernel.org \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=david.brown@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=jcrouse@codeaurora.org \
--cc=jeffrey.l.hugo@gmail.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=marc.w.gonzalez@free.fr \
--cc=mark.rutland@arm.com \
--cc=mturquette@baylibre.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).