From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,T_DKIMWL_WL_HIGH,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAC01C2BCA1 for ; Fri, 7 Jun 2019 15:49:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C089420840 for ; Fri, 7 Jun 2019 15:49:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1559922584; bh=sOpS9BJPc9CQMEbKe7GUO1LW2UZbZVTSju2eUBZ0mPc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=Nyddnjx2gyCyUbQzKiML/F+P/BbjC/5e4OLkx9uHmSMR5Pnm5Jh6iYKhBpmuL6Ue2 RFrb8biTIPvo3P97cDig2Fw6Lx2xcn+K+8lZEX7EZE0K5IfjioFDS8v8VnezXc03kr yxG2Oy8piO1VCseFcoiFXcyQ7+uhqHiQ7GY11ynA= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732017AbfFGPto (ORCPT ); Fri, 7 Jun 2019 11:49:44 -0400 Received: from mail.kernel.org ([198.145.29.99]:35770 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732000AbfFGPtk (ORCPT ); Fri, 7 Jun 2019 11:49:40 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 48B6520657; Fri, 7 Jun 2019 15:49:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1559922579; bh=sOpS9BJPc9CQMEbKe7GUO1LW2UZbZVTSju2eUBZ0mPc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OLn0rbvitHP6B/h0z7n5owYFREkcSeATGJFEwiWzDAE5IF9+tLuvZ6OzYWeb/P52Z D4ANUDjO3MUSXcsbmB4qHbhAnHOrWb2HUjkJyt+R8W4PLV7jbhwwOEpolPnRR/QfG8 FIGB0eoALwLsZMh7ZT4ZPEX+fRkJ4OlIayz3HzJM= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Peng Fan , Fabio Estevam , Jacky Bai , Stephen Boyd Subject: [PATCH 5.1 62/85] clk: imx: imx8mm: fix int pll clk gate Date: Fri, 7 Jun 2019 17:39:47 +0200 Message-Id: <20190607153856.271374220@linuxfoundation.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190607153849.101321647@linuxfoundation.org> References: <20190607153849.101321647@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Peng Fan commit b3fddd5b100e4aee4f7ec58360435024971dea47 upstream. To Frac pll, the gate shift is 13, however to Int PLL the gate shift is 11. Cc: Fixes: ba5625c3e27 ("clk: imx: Add clock driver support for imx8mm") Signed-off-by: Peng Fan Reviewed-by: Fabio Estevam Reviewed-by: Jacky Bai Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman --- drivers/clk/imx/clk-imx8mm.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -449,12 +449,12 @@ static int __init imx8mm_clocks_init(str clks[IMX8MM_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13); clks[IMX8MM_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13); clks[IMX8MM_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13); - clks[IMX8MM_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 13); - clks[IMX8MM_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 13); - clks[IMX8MM_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 13); - clks[IMX8MM_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 13); - clks[IMX8MM_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 13); - clks[IMX8MM_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 13); + clks[IMX8MM_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11); + clks[IMX8MM_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11); + clks[IMX8MM_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11); + clks[IMX8MM_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11); + clks[IMX8MM_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11); + clks[IMX8MM_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11); /* SYS PLL fixed output */ clks[IMX8MM_SYS_PLL1_40M] = imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);