From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23D00C06510 for ; Tue, 2 Jul 2019 15:29:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0098C21721 for ; Tue, 2 Jul 2019 15:29:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726767AbfGBP3O (ORCPT ); Tue, 2 Jul 2019 11:29:14 -0400 Received: from relay5-d.mail.gandi.net ([217.70.183.197]:34061 "EHLO relay5-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726457AbfGBP3O (ORCPT ); Tue, 2 Jul 2019 11:29:14 -0400 X-Originating-IP: 90.89.68.76 Received: from localhost (lfbn-1-10718-76.w90-89.abo.wanadoo.fr [90.89.68.76]) (Authenticated sender: maxime.ripard@bootlin.com) by relay5-d.mail.gandi.net (Postfix) with ESMTPSA id 548C91C0012; Tue, 2 Jul 2019 15:29:09 +0000 (UTC) Date: Tue, 2 Jul 2019 17:29:08 +0200 From: Maxime Ripard To: Jagan Teki Cc: David Airlie , Daniel Vetter , Chen-Yu Tsai , dri-devel , linux-arm-kernel , linux-kernel , Bhushan Shah , Vasily Khoruzhick , =?utf-8?B?5Z2a5a6a5YmN6KGM?= , Michael Trimarchi , linux-amarula , linux-sunxi Subject: Re: [linux-sunxi] Re: [PATCH v10 04/11] drm/sun4i: tcon: Compute DCLK dividers based on format, lanes Message-ID: <20190702152908.fwwf7smt7nh2lxo2@flea> References: <20190523204823.mx7l4ozklzdh7npn@flea> <20190604143016.fcx3ezmga244xakp@flea> <20190613131626.7zbwvrvd4e7eafrc@flea> <20190624130442.ww4l3zctykr4i2e2@flea> <20190625143747.3czd7sit4waz75b6@flea> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20180716 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jul 02, 2019 at 12:30:14AM +0530, Jagan Teki wrote: > On Tue, Jun 25, 2019 at 8:07 PM Maxime Ripard wrote: > > > > > > > > > BSP has tcon_div and dsi_div. dsi_div is dynamic which depends on > > > > > > > > > bpp/lanes and it indeed depends on PLL computation (not tcon_div), > > > > > > > > > anyway I have explained again on this initial link you mentioned. > > > > > > > > > Please have a look and get back. > > > > > > > > > > > > > > > > I'll have a look, thanks. > > > > > > > > > > > > > > > > I've given your patches a try on my setup though, and this patch > > > > > > > > breaks it with vblank timeouts and some horizontal lines that looks > > > > > > > > like what should be displayed, but blinking and on the right of the > > > > > > > > display. The previous ones are fine though. > > > > > > > > > > > > > > Would you please send me the link of panel driver. > > > > > > > > > > > > It's drivers/gpu/drm/panel/panel-ronbo-rb070d30.c > > > > > > > > > > Look like this panel work even w/o any vendor sequence. it's similar > > > > > to the 4-lane panel I have with RGB888, so the dclk div is 6, is it > > > > > working with this divider? > > > > > > > > It works with 4, it doesn't work with 6. > > > > > > Can be the pixel clock with associated timings can make this diff. > > > Would you send me the pixel clock, pll_rate and timings this panel > > > used it from BSP? > > > > This board never had an Allwinner BSP > > Running on BSP would help to understand some clue, anyway would you > send me the the value PLL_MIPI register (devme 0x1c20040) on this > board. I'm trying to understand how it value in your case. I'm sorry, but I'm not going to port a whole BSP on that board, especially for something I haven't been convinced it's the right fix. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com