From: Greg KH <gregkh@linuxfoundation.org>
To: Moritz Fischer <mdf@kernel.org>
Cc: linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, Wu Hao <hao.wu@intel.com>,
Ananda Ravuri <ananda.ravuri@intel.com>,
Xu Yilun <yilun.xu@intel.com>, Alan Tull <atull@kernel.org>
Subject: Re: [PATCH 04/15] fpga: dfl: fme: support 512bit data width PR
Date: Wed, 3 Jul 2019 19:56:01 +0200 [thread overview]
Message-ID: <20190703175601.GA14034@kroah.com> (raw)
In-Reply-To: <20190628004951.6202-5-mdf@kernel.org>
On Thu, Jun 27, 2019 at 05:49:40PM -0700, Moritz Fischer wrote:
> From: Wu Hao <hao.wu@intel.com>
>
> In early partial reconfiguration private feature, it only
> supports 32bit data width when writing data to hardware for
> PR. 512bit data width PR support is an important optimization
> for some specific solutions (e.g. XEON with FPGA integrated),
> it allows driver to use AVX512 instruction to improve the
> performance of partial reconfiguration. e.g. programming one
> 100MB bitstream image via this 512bit data width PR hardware
> only takes ~300ms, but 32bit revision requires ~3s per test
> result.
>
> Please note now this optimization is only done on revision 2
> of this PR private feature which is only used in integrated
> solution that AVX512 is always supported. This revision 2
> hardware doesn't support 32bit PR.
>
> Signed-off-by: Ananda Ravuri <ananda.ravuri@intel.com>
> Signed-off-by: Xu Yilun <yilun.xu@intel.com>
> Signed-off-by: Wu Hao <hao.wu@intel.com>
> Acked-by: Alan Tull <atull@kernel.org>
> Signed-off-by: Moritz Fischer <mdf@kernel.org>
> ---
> drivers/fpga/dfl-fme-main.c | 3 +
> drivers/fpga/dfl-fme-mgr.c | 113 +++++++++++++++++++++++++++++++-----
> drivers/fpga/dfl-fme-pr.c | 43 +++++++++-----
> drivers/fpga/dfl-fme.h | 2 +
> drivers/fpga/dfl.h | 5 ++
> 5 files changed, 135 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c
> index 086ad2420ade..076d74f6416d 100644
> --- a/drivers/fpga/dfl-fme-main.c
> +++ b/drivers/fpga/dfl-fme-main.c
> @@ -21,6 +21,8 @@
> #include "dfl.h"
> #include "dfl-fme.h"
>
> +#define DRV_VERSION "0.8"
> +
> static ssize_t ports_num_show(struct device *dev,
> struct device_attribute *attr, char *buf)
> {
> @@ -277,3 +279,4 @@ MODULE_DESCRIPTION("FPGA Management Engine driver");
> MODULE_AUTHOR("Intel Corporation");
> MODULE_LICENSE("GPL v2");
> MODULE_ALIAS("platform:dfl-fme");
> +MODULE_VERSION(DRV_VERSION);
No, we ripped out these useless "driver version" things all over the
place, please do not add them back in again. They mean nothing and
confuse people to no end.
I'll not take this patch, sorry.
greg k-h
next prev parent reply other threads:[~2019-07-03 17:56 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-28 0:49 [PATCH 00/15] FPGA DFL updates Moritz Fischer
2019-06-28 0:49 ` [PATCH 01/15] fpga: dfl-fme-mgr: fix FME_PR_INTFC_ID register address Moritz Fischer
2019-06-28 0:49 ` [PATCH 02/15] fpga: dfl: fme: remove copy_to_user() in ioctl for PR Moritz Fischer
2019-06-28 0:49 ` [PATCH 03/15] fpga: dfl: fme: align PR buffer size per PR datawidth Moritz Fischer
2019-06-28 0:49 ` [PATCH 04/15] fpga: dfl: fme: support 512bit data width PR Moritz Fischer
2019-07-03 17:56 ` Greg KH [this message]
2019-07-03 23:44 ` Wu Hao
2019-06-28 0:49 ` [PATCH 05/15] Documentation: fpga: dfl: add descriptions for virtualization and new interfaces Moritz Fischer
2019-07-03 17:59 ` Greg KH
2019-07-03 23:38 ` Wu Hao
2019-07-04 5:37 ` Greg KH
2019-07-04 6:42 ` Wu Hao
2019-07-04 8:17 ` Greg KH
2019-07-04 8:19 ` Wu Hao
2019-06-28 0:49 ` [PATCH 06/15] fpga: dfl: fme: add DFL_FPGA_FME_PORT_RELEASE/ASSIGN ioctl support Moritz Fischer
2019-07-03 18:07 ` Greg KH
2019-07-03 23:30 ` Wu Hao
2019-07-04 5:39 ` Greg KH
2019-07-04 6:31 ` Wu Hao
2019-07-04 8:20 ` Greg KH
2019-07-04 8:58 ` Wu Hao
2019-07-04 11:04 ` Greg KH
2019-07-04 11:29 ` Wu Hao
2019-06-28 0:49 ` [PATCH 07/15] fpga: dfl: pci: enable SRIOV support Moritz Fischer
2019-06-28 0:49 ` [PATCH 08/15] fpga: dfl: afu: add AFU state related sysfs interfaces Moritz Fischer
2019-06-28 0:49 ` [PATCH 09/15] fpga: dfl: afu: add userclock " Moritz Fischer
2019-06-28 0:49 ` [PATCH 10/15] fpga: dfl: add id_table for dfl private feature driver Moritz Fischer
2019-06-28 0:49 ` [PATCH 11/15] fpga: dfl: afu: export __port_enable/disable function Moritz Fischer
2019-06-28 0:49 ` [PATCH 12/15] fpga: dfl: afu: add error reporting support Moritz Fischer
2019-06-28 0:49 ` [PATCH 13/15] fpga: dfl: afu: add STP (SignalTap) support Moritz Fischer
2019-06-28 0:49 ` [PATCH 14/15] fpga: dfl: fme: add capability sysfs interfaces Moritz Fischer
2019-06-28 0:49 ` [PATCH 15/15] fpga: dfl: fme: add global error reporting support Moritz Fischer
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