From: Niklas Cassel <niklas.cassel@linaro.org>
To: Ilia Lin <ilia.lin@kernel.org>, Andy Gross <agross@kernel.org>,
Viresh Kumar <vireshk@kernel.org>, Nishanth Menon <nm@ti.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, jorge.ramirez-ortiz@linaro.org,
bjorn.andersson@linaro.org, ulf.hansson@linaro.org,
Niklas Cassel <niklas.cassel@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 05/13] dt-bindings: cpufreq: qcom-nvmem: Support pstates provided by a power domain
Date: Fri, 5 Jul 2019 11:57:16 +0200 [thread overview]
Message-ID: <20190705095726.21433-6-niklas.cassel@linaro.org> (raw)
In-Reply-To: <20190705095726.21433-1-niklas.cassel@linaro.org>
Some Qualcomm SoCs have support for Core Power Reduction (CPR).
On these platforms, we need to attach to the power domain provider
providing the performance states, so that the leaky device (the CPU)
can configure the performance states (which represent different
CPU clock frequencies).
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
---
.../bindings/opp/qcom-nvmem-cpufreq.txt | 111 ++++++++++++++++++
1 file changed, 111 insertions(+)
diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
index c5ea8b90e35d..e19a95318e98 100644
--- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
@@ -23,6 +23,15 @@ In 'operating-points-v2' table:
Optional properties:
--------------------
+In 'cpus' nodes:
+- power-domains: A phandle pointing to the PM domain specifier which provides
+ the performance states available for active state management.
+ Please refer to the power-domains bindings
+ Documentation/devicetree/bindings/power/power_domain.txt
+ and also examples below.
+- power-domain-names: Should be
+ - 'cpr' for qcs404.
+
In 'operating-points-v2' table:
- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
efuse registers that has information about the
@@ -682,3 +691,105 @@ soc {
};
};
};
+
+Example 2:
+---------
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x100>;
+ ....
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ power-domains = <&cprpd>;
+ power-domain-names = "cpr";
+ };
+
+ CPU1: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x101>;
+ ....
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ power-domains = <&cprpd>;
+ power-domain-names = "cpr";
+ };
+
+ CPU2: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x102>;
+ ....
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ power-domains = <&cprpd>;
+ power-domain-names = "cpr";
+ };
+
+ CPU3: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x103>;
+ ....
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ power-domains = <&cprpd>;
+ power-domain-names = "cpr";
+ };
+ };
+
+ cpu_opp_table: cpu-opp-table {
+ compatible = "operating-points-v2-kryo-cpu";
+ opp-shared;
+
+ opp-1094400000 {
+ opp-hz = /bits/ 64 <1094400000>;
+ required-opps = <&cpr_opp1>;
+ };
+ opp-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ required-opps = <&cpr_opp2>;
+ };
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ required-opps = <&cpr_opp3>;
+ };
+ };
+
+ cpr_opp_table: cpr-opp-table {
+ compatible = "operating-points-v2-qcom-level";
+
+ cpr_opp1: opp1 {
+ opp-level = <1>;
+ ....
+ };
+ cpr_opp2: opp2 {
+ opp-level = <2>;
+ ....
+ };
+ cpr_opp3: opp3 {
+ opp-level = <3>;
+ ....
+ };
+ };
+
+....
+
+soc {
+....
+ cprpd: cpr@b018000 {
+ compatible = "qcom,qcs404-cpr", "qcom,cpr";
+ reg = <0x0b018000 0x1000>;
+ ....
+ vdd-apc-supply = <&pms405_s3>;
+ #power-domain-cells = <0>;
+ operating-points-v2 = <&cpr_opp_table>;
+ ....
+ };
+};
--
2.21.0
next prev parent reply other threads:[~2019-07-05 9:58 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-05 9:57 [PATCH 00/13] Add support for QCOM Core Power Reduction Niklas Cassel
2019-07-05 9:57 ` [PATCH 01/13] dt-bindings: cpufreq: Re-organise kryo cpufreq to use it for other nvmem based qcom socs Niklas Cassel
2019-07-08 6:28 ` Ilia Lin
2019-07-24 14:53 ` Rob Herring
2019-07-05 9:57 ` [PATCH 02/13] cpufreq: qcom: " Niklas Cassel
2019-07-08 6:27 ` Ilia Lin
2019-07-10 6:18 ` Viresh Kumar
2019-07-16 11:11 ` Niklas Cassel
2019-07-05 9:57 ` [PATCH 03/13] dt-bindings: cpufreq: qcom-nvmem: Make speedbin related properties optional Niklas Cassel
2019-07-08 6:28 ` Ilia Lin
2019-07-24 14:56 ` Rob Herring
2019-07-05 9:57 ` [PATCH 04/13] cpufreq: qcom: Refactor the driver to make it easier to extend Niklas Cassel
2019-07-08 6:30 ` Ilia Lin
2019-07-10 6:30 ` Viresh Kumar
2019-07-16 11:11 ` Niklas Cassel
2019-07-05 9:57 ` Niklas Cassel [this message]
2019-07-24 15:26 ` [PATCH 05/13] dt-bindings: cpufreq: qcom-nvmem: Support pstates provided by a power domain Rob Herring
2019-07-05 9:57 ` [PATCH 06/13] cpufreq: qcom: Add support for qcs404 on nvmem driver Niklas Cassel
2019-07-05 9:57 ` [PATCH 07/13] cpufreq: Add qcs404 to cpufreq-dt-platdev blacklist Niklas Cassel
2019-07-05 9:57 ` [PATCH 08/13] dt-bindings: opp: Add qcom-opp bindings with properties needed for CPR Niklas Cassel
2019-07-24 16:03 ` Rob Herring
2019-07-05 9:57 ` [PATCH 09/13] dt-bindings: power: avs: Add support for CPR (Core Power Reduction) Niklas Cassel
2019-07-24 16:06 ` Rob Herring
2019-07-05 9:57 ` [PATCH 10/13] " Niklas Cassel
2019-07-05 9:57 ` [PATCH 11/13] arm64: dts: qcom: qcs404: Add CPR and populate OPP table Niklas Cassel
2019-07-10 9:03 ` Viresh Kumar
2019-07-15 13:24 ` Niklas Cassel
2019-07-16 10:34 ` Viresh Kumar
2019-07-16 10:53 ` Niklas Cassel
2019-07-17 4:49 ` Viresh Kumar
2019-07-19 15:45 ` Niklas Cassel
2019-07-23 1:56 ` Viresh Kumar
2019-07-25 10:40 ` Niklas Cassel
2019-07-05 9:57 ` [PATCH 12/13] arm64: defconfig: enable CONFIG_QCOM_CPR Niklas Cassel
2019-07-05 9:57 ` [PATCH 13/13] arm64: defconfig: enable CONFIG_ARM_QCOM_CPUFREQ_NVMEM Niklas Cassel
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