From: Kees Cook <keescook@chromium.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>,
Ingo Molnar <mingo@kernel.org>,
Linux List Kernel Mailing <linux-kernel@vger.kernel.org>,
Borislav Petkov <bp@alien8.de>, Len Brown <lenb@kernel.org>,
Peter Zijlstra <a.p.zijlstra@chello.nl>,
Andrew Morton <akpm@linux-foundation.org>,
"Rafael J. Wysocki" <rafael.j.wysocki@intel.com>,
Tony Luck <tony.luck@intel.com>, Jiri Kosina <jkosina@suse.cz>,
Bob Moore <robert.moore@intel.com>,
Erik Schmauss <erik.schmauss@intel.com>
Subject: Re: [GIT PULL] x86/topology changes for v5.3
Date: Tue, 9 Jul 2019 17:31:07 -0700 [thread overview]
Message-ID: <201907091727.91CC6C72D8@keescook> (raw)
In-Reply-To: <alpine.DEB.2.21.1907100115220.1758@nanos.tec.linutronix.de>
On Wed, Jul 10, 2019 at 01:17:11AM +0200, Thomas Gleixner wrote:
> On Wed, 10 Jul 2019, Thomas Gleixner wrote:
> >
> > That still does not explain the cr4/0 issue you have. Can you send me your
> > .config please?
>
> Does your machine have UMIP support? None of my test boxes has. So that'd
> be the difference of bits enforced in CR4. Should not matter because it's
> User mode instruction prevention, but who knows.
Ew. Yeah, I don't have i9 nor i7 for testing this. I did try everything
else I had (and hibernation). Is only Linus able to reproduce this so far?
To rule out (in?) UMIP, this would remove UMIP from the pinning:
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 309b6b9b49d4..f3beedb6da8a 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -380,7 +380,7 @@ static void __init setup_cr_pinning(void)
{
unsigned long mask;
- mask = (X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP);
+ mask = (X86_CR4_SMEP | X86_CR4_SMAP);
cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & mask;
static_key_enable(&cr_pinning.key);
}
--
Kees Cook
next prev parent reply other threads:[~2019-07-10 0:31 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-08 16:27 [GIT PULL] x86/topology changes for v5.3 Ingo Molnar
2019-07-09 1:45 ` pr-tracker-bot
2019-07-09 21:20 ` Linus Torvalds
2019-07-09 21:26 ` Linus Torvalds
2019-07-09 21:45 ` Linus Torvalds
2019-07-09 22:00 ` Linus Torvalds
2019-07-09 22:07 ` Linus Torvalds
2019-07-09 22:27 ` Thomas Gleixner
2019-07-09 23:00 ` Thomas Gleixner
2019-07-09 23:17 ` Thomas Gleixner
2019-07-10 0:31 ` Kees Cook [this message]
2019-07-10 11:27 ` Xi Ruoyao
2019-07-10 12:01 ` Xi Ruoyao
2019-07-10 12:19 ` Thomas Gleixner
2019-07-10 12:31 ` Jiri Kosina
2019-07-10 13:21 ` Peter Zijlstra
2019-07-10 13:27 ` Jiri Kosina
2019-07-10 13:28 ` Jiri Kosina
2019-07-10 13:31 ` Xi Ruoyao
2019-07-10 13:25 ` Xi Ruoyao
2019-07-10 13:44 ` Peter Zijlstra
2019-07-10 14:03 ` Thomas Gleixner
2019-07-10 14:26 ` Thomas Gleixner
2019-07-10 14:22 ` Jiri Kosina
2019-07-10 14:26 ` Peter Zijlstra
2019-07-10 15:13 ` Thomas Gleixner
2019-07-10 15:58 ` Xi Ruoyao
2019-07-10 19:42 ` [PATCH] x86/asm: Move native_write_cr0/3() out of line Thomas Gleixner
2019-07-10 19:59 ` Kees Cook
2019-07-10 20:00 ` Thomas Gleixner
2019-07-10 20:02 ` Peter Zijlstra
2019-07-10 20:19 ` [tip:x86/urgent] x86/asm: Move native_write_cr0/4() " tip-bot for Thomas Gleixner
2019-07-10 14:44 ` [GIT PULL] x86/topology changes for v5.3 Xi Ruoyao
2019-07-11 7:11 ` Nadav Amit
2019-07-11 7:16 ` Thomas Gleixner
2019-07-11 8:01 ` Peter Zijlstra
2019-07-11 15:08 ` Kees Cook
2019-07-11 17:09 ` Nadav Amit
2019-07-10 0:59 ` Linus Torvalds
2019-07-10 1:08 ` Linus Torvalds
2019-07-10 3:21 ` Linus Torvalds
2019-07-10 5:15 ` Linus Torvalds
2019-07-10 5:33 ` Kees Cook
2019-07-10 18:40 ` Linus Torvalds
2019-07-10 10:03 ` Rafael J. Wysocki
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