* [PATCH 0/5] MIPS: ralink: add CPU clock detection for MT7621
@ 2019-07-09 18:20 Chuanhong Guo
2019-07-09 18:20 ` [PATCH 1/5] MIPS: ralink: add dt binding header for mt7621-pll Chuanhong Guo
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: Chuanhong Guo @ 2019-07-09 18:20 UTC (permalink / raw)
To: open list:COMMON CLK FRAMEWORK,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, open list:MIPS, open list:STAGING SUBSYSTEM
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Ralf Baechle, Paul Burton, James Hogan, John Crispin,
Greg Kroah-Hartman, Weijie Gao, NeilBrown, Chuanhong Guo
This patchset ports CPU clock detection for MT7621 from OpenWrt.
Last time I sent this, I forgot to add an binding include which
caused a compile error and the patch doesn't stay in linux-next.
This patchset resent the first two commits and also added binding
documentation for mt7621-pll and used it in mt7621-dts at
drivers/staging.
BTW: What should I do with such a patchset that touches multiple
parts in kernel?
Is it correct to send the entire patchset to lists of all involved
subsystems?
Chuanhong Guo (5):
MIPS: ralink: add dt binding header for mt7621-pll
MIPS: ralink: fix cpu clock of mt7621 and add dt clk devices
dt: bindings: add mt7621-pll dt binding documentation
staging: mt7621-dts: add dt nodes for mt7621-pll
staging: mt7621-dts: fix register range of memc node in mt7621.dtsi
.../bindings/clock/mediatek,mt7621-pll.txt | 19 ++++
arch/mips/include/asm/mach-ralink/mt7621.h | 20 ++++
arch/mips/ralink/mt7621.c | 102 ++++++++++++------
arch/mips/ralink/timer-gic.c | 4 +-
drivers/staging/mt7621-dts/mt7621.dtsi | 17 ++-
include/dt-bindings/clock/mt7621-clk.h | 14 +++
6 files changed, 134 insertions(+), 42 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
create mode 100644 include/dt-bindings/clock/mt7621-clk.h
--
2.21.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/5] MIPS: ralink: add dt binding header for mt7621-pll
2019-07-09 18:20 [PATCH 0/5] MIPS: ralink: add CPU clock detection for MT7621 Chuanhong Guo
@ 2019-07-09 18:20 ` Chuanhong Guo
2019-07-22 21:40 ` Stephen Boyd
2019-07-09 18:20 ` [PATCH 2/5] MIPS: ralink: fix cpu clock of mt7621 and add dt clk devices Chuanhong Guo
` (3 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Chuanhong Guo @ 2019-07-09 18:20 UTC (permalink / raw)
To: open list:COMMON CLK FRAMEWORK,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, open list:MIPS, open list:STAGING SUBSYSTEM
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Ralf Baechle, Paul Burton, James Hogan, John Crispin,
Greg Kroah-Hartman, Weijie Gao, NeilBrown, Chuanhong Guo,
Rob Herring
This patch adds dt binding header for mediatek,mt7621-pll
Signed-off-by: Weijie Gao <hackpascal@gmail.com>
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
include/dt-bindings/clock/mt7621-clk.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
create mode 100644 include/dt-bindings/clock/mt7621-clk.h
diff --git a/include/dt-bindings/clock/mt7621-clk.h b/include/dt-bindings/clock/mt7621-clk.h
new file mode 100644
index 000000000000..a29e14ee2efe
--- /dev/null
+++ b/include/dt-bindings/clock/mt7621-clk.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Weijie Gao <hackpascal@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_MT7621_CLK_H
+#define __DT_BINDINGS_MT7621_CLK_H
+
+#define MT7621_CLK_CPU 0
+#define MT7621_CLK_BUS 1
+
+#define MT7621_CLK_MAX 2
+
+#endif /* __DT_BINDINGS_MT7621_CLK_H */
--
2.21.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/5] MIPS: ralink: fix cpu clock of mt7621 and add dt clk devices
2019-07-09 18:20 [PATCH 0/5] MIPS: ralink: add CPU clock detection for MT7621 Chuanhong Guo
2019-07-09 18:20 ` [PATCH 1/5] MIPS: ralink: add dt binding header for mt7621-pll Chuanhong Guo
@ 2019-07-09 18:20 ` Chuanhong Guo
2019-07-22 21:50 ` Stephen Boyd
2019-07-09 18:20 ` [PATCH 3/5] dt: bindings: add mt7621-pll dt binding documentation Chuanhong Guo
` (2 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Chuanhong Guo @ 2019-07-09 18:20 UTC (permalink / raw)
To: open list:COMMON CLK FRAMEWORK,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, open list:MIPS, open list:STAGING SUBSYSTEM
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Ralf Baechle, Paul Burton, James Hogan, John Crispin,
Greg Kroah-Hartman, Weijie Gao, NeilBrown, Chuanhong Guo
For a long time the mt7621 uses a fixed cpu clock which causes a problem
if the cpu frequency is not 880MHz.
This patch fixes the cpu clock calculation and adds the cpu/bus clkdev
which will be used in dts.
Ported from OpenWrt:
c7ca224299 ramips: fix cpu clock of mt7621 and add dt clk devices
Signed-off-by: Weijie Gao <hackpascal@gmail.com>
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
---
arch/mips/include/asm/mach-ralink/mt7621.h | 20 ++++
arch/mips/ralink/mt7621.c | 102 ++++++++++++++-------
arch/mips/ralink/timer-gic.c | 4 +-
3 files changed, 93 insertions(+), 33 deletions(-)
diff --git a/arch/mips/include/asm/mach-ralink/mt7621.h b/arch/mips/include/asm/mach-ralink/mt7621.h
index 65483a4681ab..51a6e51aef3f 100644
--- a/arch/mips/include/asm/mach-ralink/mt7621.h
+++ b/arch/mips/include/asm/mach-ralink/mt7621.h
@@ -17,6 +17,10 @@
#define SYSC_REG_CHIP_REV 0x0c
#define SYSC_REG_SYSTEM_CONFIG0 0x10
#define SYSC_REG_SYSTEM_CONFIG1 0x14
+#define SYSC_REG_CLKCFG0 0x2c
+#define SYSC_REG_CUR_CLK_STS 0x44
+
+#define MEMC_REG_CPU_PLL 0x648
#define CHIP_REV_PKG_MASK 0x1
#define CHIP_REV_PKG_SHIFT 16
@@ -24,6 +28,22 @@
#define CHIP_REV_VER_SHIFT 8
#define CHIP_REV_ECO_MASK 0xf
+#define XTAL_MODE_SEL_MASK 0x7
+#define XTAL_MODE_SEL_SHIFT 6
+
+#define CPU_CLK_SEL_MASK 0x3
+#define CPU_CLK_SEL_SHIFT 30
+
+#define CUR_CPU_FDIV_MASK 0x1f
+#define CUR_CPU_FDIV_SHIFT 8
+#define CUR_CPU_FFRAC_MASK 0x1f
+#define CUR_CPU_FFRAC_SHIFT 0
+
+#define CPU_PLL_PREDIV_MASK 0x3
+#define CPU_PLL_PREDIV_SHIFT 12
+#define CPU_PLL_FBDIV_MASK 0x7f
+#define CPU_PLL_FBDIV_SHIFT 4
+
#define MT7621_DRAM_BASE 0x0
#define MT7621_DDR2_SIZE_MIN 32
#define MT7621_DDR2_SIZE_MAX 256
diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
index 9415be0d57b8..31158b88bcb6 100644
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -7,22 +7,22 @@
#include <linux/kernel.h>
#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <dt-bindings/clock/mt7621-clk.h>
#include <asm/mipsregs.h>
#include <asm/smp-ops.h>
#include <asm/mips-cps.h>
#include <asm/mach-ralink/ralink_regs.h>
#include <asm/mach-ralink/mt7621.h>
+#include <asm/time.h>
#include <pinmux.h>
#include "common.h"
-#define SYSC_REG_SYSCFG 0x10
-#define SYSC_REG_CPLL_CLKCFG0 0x2c
-#define SYSC_REG_CUR_CLK_STS 0x44
-#define CPU_CLK_SEL (BIT(30) | BIT(31))
-
#define MT7621_GPIO_MODE_UART1 1
#define MT7621_GPIO_MODE_I2C 2
#define MT7621_GPIO_MODE_UART3_MASK 0x3
@@ -108,49 +108,89 @@ static struct rt2880_pmx_group mt7621_pinmux_data[] = {
{ 0 }
};
+static struct clk *clks[MT7621_CLK_MAX];
+static struct clk_onecell_data clk_data = {
+ .clks = clks,
+ .clk_num = ARRAY_SIZE(clks),
+};
+
phys_addr_t mips_cpc_default_phys_base(void)
{
panic("Cannot detect cpc address");
}
+static struct clk *__init mt7621_add_sys_clkdev(
+ const char *id, unsigned long rate)
+{
+ struct clk *clk;
+ int err;
+
+ clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
+ if (IS_ERR(clk))
+ panic("failed to allocate %s clock structure", id);
+
+ err = clk_register_clkdev(clk, id, NULL);
+ if (err)
+ panic("unable to register %s clock device", id);
+
+ return clk;
+}
+
void __init ralink_clk_init(void)
{
- int cpu_fdiv = 0;
- int cpu_ffrac = 0;
- int fbdiv = 0;
- u32 clk_sts, syscfg;
- u8 clk_sel = 0, xtal_mode;
- u32 cpu_clk;
+ const static u32 prediv_tbl[] = {0, 1, 2, 2};
+ u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;
+ u32 pll, prediv, fbdiv;
+ u32 xtal_clk, cpu_clk, bus_clk;
+
+ syscfg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
+ xtal_sel = (syscfg >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK;
- if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
- clk_sel = 1;
+ clkcfg = rt_sysc_r32(SYSC_REG_CLKCFG0);
+ clk_sel = (clkcfg >> CPU_CLK_SEL_SHIFT) & CPU_CLK_SEL_MASK;
+
+ curclk = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
+ ffiv = (curclk >> CUR_CPU_FDIV_SHIFT) & CUR_CPU_FDIV_MASK;
+ ffrac = (curclk >> CUR_CPU_FFRAC_SHIFT) & CUR_CPU_FFRAC_MASK;
+
+ if (xtal_sel <= 2)
+ xtal_clk = 20 * 1000 * 1000;
+ else if (xtal_sel <= 5)
+ xtal_clk = 40 * 1000 * 1000;
+ else
+ xtal_clk = 25 * 1000 * 1000;
switch (clk_sel) {
case 0:
- clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
- cpu_fdiv = ((clk_sts >> 8) & 0x1F);
- cpu_ffrac = (clk_sts & 0x1F);
- cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
+ cpu_clk = 500 * 1000 * 1000;
break;
-
case 1:
- fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
- syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
- xtal_mode = (syscfg >> 6) & 0x7;
- if (xtal_mode >= 6) {
- /* 25Mhz Xtal */
- cpu_clk = 25 * fbdiv * 1000 * 1000;
- } else if (xtal_mode >= 3) {
- /* 40Mhz Xtal */
- cpu_clk = 40 * fbdiv * 1000 * 1000;
- } else {
- /* 20Mhz Xtal */
- cpu_clk = 20 * fbdiv * 1000 * 1000;
- }
+ pll = rt_memc_r32(MEMC_REG_CPU_PLL);
+ fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK;
+ prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK;
+ cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];
break;
+ default:
+ cpu_clk = xtal_clk;
}
+
+ cpu_clk = cpu_clk / ffiv * ffrac;
+ bus_clk = cpu_clk / 4;
+
+ clks[MT7621_CLK_CPU] = mt7621_add_sys_clkdev("cpu", cpu_clk);
+ clks[MT7621_CLK_BUS] = mt7621_add_sys_clkdev("bus", bus_clk);
+
+ pr_info("CPU Clock: %dMHz\n", cpu_clk / 1000000);
+ mips_hpt_frequency = cpu_clk / 2;
}
+static void __init mt7621_clocks_init_dt(struct device_node *np)
+{
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+CLK_OF_DECLARE(mt7621_clk, "mediatek,mt7621-pll", mt7621_clocks_init_dt);
+
void __init ralink_of_remap(void)
{
rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
diff --git a/arch/mips/ralink/timer-gic.c b/arch/mips/ralink/timer-gic.c
index 944fbe0fc741..9bbaa37a0da1 100644
--- a/arch/mips/ralink/timer-gic.c
+++ b/arch/mips/ralink/timer-gic.c
@@ -9,14 +9,14 @@
#include <linux/of.h>
#include <linux/clk-provider.h>
-#include <linux/clocksource.h>
+#include <asm/time.h>
#include "common.h"
void __init plat_time_init(void)
{
ralink_of_remap();
-
+ ralink_clk_init();
of_clk_init(NULL);
timer_probe();
}
--
2.21.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/5] dt: bindings: add mt7621-pll dt binding documentation
2019-07-09 18:20 [PATCH 0/5] MIPS: ralink: add CPU clock detection for MT7621 Chuanhong Guo
2019-07-09 18:20 ` [PATCH 1/5] MIPS: ralink: add dt binding header for mt7621-pll Chuanhong Guo
2019-07-09 18:20 ` [PATCH 2/5] MIPS: ralink: fix cpu clock of mt7621 and add dt clk devices Chuanhong Guo
@ 2019-07-09 18:20 ` Chuanhong Guo
2019-07-22 21:51 ` Stephen Boyd
2019-07-09 18:20 ` [PATCH 4/5] staging: mt7621-dts: add dt nodes for mt7621-pll Chuanhong Guo
2019-07-09 18:20 ` [PATCH 5/5] staging: mt7621-dts: fix register range of memc node in mt7621.dtsi Chuanhong Guo
4 siblings, 1 reply; 10+ messages in thread
From: Chuanhong Guo @ 2019-07-09 18:20 UTC (permalink / raw)
To: open list:COMMON CLK FRAMEWORK,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, open list:MIPS, open list:STAGING SUBSYSTEM
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Ralf Baechle, Paul Burton, James Hogan, John Crispin,
Greg Kroah-Hartman, Weijie Gao, NeilBrown, Chuanhong Guo
This commit adds device tree binding documentation for MT7621
PLL controller.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
---
.../bindings/clock/mediatek,mt7621-pll.txt | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
new file mode 100644
index 000000000000..05c15062cd20
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
@@ -0,0 +1,19 @@
+Binding for Mediatek MT7621 PLL controller
+
+The PLL controller provides the 2 main clocks of the SoC: CPU and BUS.
+
+Required Properties:
+- compatible: has to be "mediatek,mt7621-pll"
+- #clock-cells: has to be one
+
+Optional properties:
+- clock-output-names: should be "cpu", "bus"
+
+Example:
+ pll {
+ compatible = "mediatek,mt7621-pll", "syscon";
+
+ #clock-cells = <1>;
+ clock-output-names = "cpu", "bus";
+ };
+
--
2.21.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 4/5] staging: mt7621-dts: add dt nodes for mt7621-pll
2019-07-09 18:20 [PATCH 0/5] MIPS: ralink: add CPU clock detection for MT7621 Chuanhong Guo
` (2 preceding siblings ...)
2019-07-09 18:20 ` [PATCH 3/5] dt: bindings: add mt7621-pll dt binding documentation Chuanhong Guo
@ 2019-07-09 18:20 ` Chuanhong Guo
2019-07-10 6:46 ` Chuanhong Guo
2019-07-09 18:20 ` [PATCH 5/5] staging: mt7621-dts: fix register range of memc node in mt7621.dtsi Chuanhong Guo
4 siblings, 1 reply; 10+ messages in thread
From: Chuanhong Guo @ 2019-07-09 18:20 UTC (permalink / raw)
To: open list:COMMON CLK FRAMEWORK,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, open list:MIPS, open list:STAGING SUBSYSTEM
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Ralf Baechle, Paul Burton, James Hogan, John Crispin,
Greg Kroah-Hartman, Weijie Gao, NeilBrown, Chuanhong Guo
This commit adds device-tree node for mt7621-pll and use its clock
accordingly.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
---
drivers/staging/mt7621-dts/mt7621.dtsi | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index a4c08110094b..12717f570ceb 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -1,4 +1,5 @@
#include <dt-bindings/interrupt-controller/mips-gic.h>
+#include <dt-bindings/clock/mt7621-clk.h>
#include <dt-bindings/gpio/gpio.h>
/ {
@@ -27,12 +28,11 @@
serial0 = &uartlite;
};
- cpuclock: cpuclock@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
+ pll: pll {
+ compatible = "mediatek,mt7621-pll", "syscon";
- /* FIXME: there should be way to detect this */
- clock-frequency = <880000000>;
+ #clock-cells = <1>;
+ clock-output-names = "cpu", "bus";
};
sysclock: sysclock@0 {
@@ -155,7 +155,6 @@
compatible = "ns16550a";
reg = <0xc00 0x100>;
- clocks = <&sysclock>;
clock-frequency = <50000000>;
interrupt-parent = <&gic>;
@@ -172,7 +171,7 @@
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
- clocks = <&sysclock>;
+ clocks = <&pll MT7621_CLK_BUS>;
resets = <&rstctrl 18>;
reset-names = "spi";
@@ -372,7 +371,7 @@
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
- clocks = <&cpuclock>;
+ clocks = <&pll MT7621_CLK_CPU>;
};
};
--
2.21.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 5/5] staging: mt7621-dts: fix register range of memc node in mt7621.dtsi
2019-07-09 18:20 [PATCH 0/5] MIPS: ralink: add CPU clock detection for MT7621 Chuanhong Guo
` (3 preceding siblings ...)
2019-07-09 18:20 ` [PATCH 4/5] staging: mt7621-dts: add dt nodes for mt7621-pll Chuanhong Guo
@ 2019-07-09 18:20 ` Chuanhong Guo
4 siblings, 0 replies; 10+ messages in thread
From: Chuanhong Guo @ 2019-07-09 18:20 UTC (permalink / raw)
To: open list:COMMON CLK FRAMEWORK,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, open list:MIPS, open list:STAGING SUBSYSTEM
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Ralf Baechle, Paul Burton, James Hogan, John Crispin,
Greg Kroah-Hartman, Weijie Gao, NeilBrown, Chuanhong Guo
The memc node from mt7621.dtsi has incorrect register resource.
Fix it according to the programming guide.
Signed-off-by: Weijie Gao <hackpascal@gmail.com>
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
---
drivers/staging/mt7621-dts/mt7621.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index 12717f570ceb..ac9189276590 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -138,7 +138,7 @@
memc: memc@5000 {
compatible = "mtk,mt7621-memc";
- reg = <0x300 0x100>;
+ reg = <0x5000 0x1000>;
};
cpc: cpc@1fbf0000 {
--
2.21.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 4/5] staging: mt7621-dts: add dt nodes for mt7621-pll
2019-07-09 18:20 ` [PATCH 4/5] staging: mt7621-dts: add dt nodes for mt7621-pll Chuanhong Guo
@ 2019-07-10 6:46 ` Chuanhong Guo
0 siblings, 0 replies; 10+ messages in thread
From: Chuanhong Guo @ 2019-07-10 6:46 UTC (permalink / raw)
To: open list:COMMON CLK FRAMEWORK,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, open list:MIPS, open list:STAGING SUBSYSTEM
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Ralf Baechle, Paul Burton, James Hogan, John Crispin,
Greg Kroah-Hartman, Weijie Gao, NeilBrown
On Wed, Jul 10, 2019 at 2:22 AM Chuanhong Guo <gch981213@gmail.com> wrote:
>
> This commit adds device-tree node for mt7621-pll and use its clock
> accordingly.
>
> Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Oops. Please ignore this single patch for now. I forgot to drop
cpuclock node in drivers/staging/mt7621-dts/gbpc1.dts
I'll resend this patch with changes for gbpc1.dts after the other four
patches are applied.
> ---
> drivers/staging/mt7621-dts/mt7621.dtsi | 15 +++++++--------
> 1 file changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
> index a4c08110094b..12717f570ceb 100644
> --- a/drivers/staging/mt7621-dts/mt7621.dtsi
> +++ b/drivers/staging/mt7621-dts/mt7621.dtsi
> @@ -1,4 +1,5 @@
> #include <dt-bindings/interrupt-controller/mips-gic.h>
> +#include <dt-bindings/clock/mt7621-clk.h>
> #include <dt-bindings/gpio/gpio.h>
>
> / {
> @@ -27,12 +28,11 @@
> serial0 = &uartlite;
> };
>
> - cpuclock: cpuclock@0 {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> + pll: pll {
> + compatible = "mediatek,mt7621-pll", "syscon";
>
> - /* FIXME: there should be way to detect this */
> - clock-frequency = <880000000>;
> + #clock-cells = <1>;
> + clock-output-names = "cpu", "bus";
> };
>
> sysclock: sysclock@0 {
> @@ -155,7 +155,6 @@
> compatible = "ns16550a";
> reg = <0xc00 0x100>;
>
> - clocks = <&sysclock>;
> clock-frequency = <50000000>;
>
> interrupt-parent = <&gic>;
> @@ -172,7 +171,7 @@
> compatible = "ralink,mt7621-spi";
> reg = <0xb00 0x100>;
>
> - clocks = <&sysclock>;
> + clocks = <&pll MT7621_CLK_BUS>;
>
> resets = <&rstctrl 18>;
> reset-names = "spi";
> @@ -372,7 +371,7 @@
> timer {
> compatible = "mti,gic-timer";
> interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
> - clocks = <&cpuclock>;
> + clocks = <&pll MT7621_CLK_CPU>;
> };
> };
>
> --
> 2.21.0
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/5] MIPS: ralink: add dt binding header for mt7621-pll
2019-07-09 18:20 ` [PATCH 1/5] MIPS: ralink: add dt binding header for mt7621-pll Chuanhong Guo
@ 2019-07-22 21:40 ` Stephen Boyd
0 siblings, 0 replies; 10+ messages in thread
From: Stephen Boyd @ 2019-07-22 21:40 UTC (permalink / raw)
To: open list:COMMON CLK FRAMEWORK, open list:MIPS,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:STAGING SUBSYSTEM, Chuanhong Guo, open list
Cc: Michael Turquette, Rob Herring, Mark Rutland, Ralf Baechle,
Paul Burton, James Hogan, John Crispin, Greg Kroah-Hartman,
Weijie Gao, NeilBrown, Chuanhong Guo, Rob Herring
The subject of this patch is confusing. Not sure what it has to do with
"MIPS:" so maybe remove that and prefix it "dt-bindings: clock:"
instead.
Quoting Chuanhong Guo (2019-07-09 11:20:14)
> This patch adds dt binding header for mediatek,mt7621-pll
>
> Signed-off-by: Weijie Gao <hackpascal@gmail.com>
> Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
Otherwise looks ok to me. Should I apply it to clk tree?
> include/dt-bindings/clock/mt7621-clk.h | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
> create mode 100644 include/dt-bindings/clock/mt7621-clk.h
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/5] MIPS: ralink: fix cpu clock of mt7621 and add dt clk devices
2019-07-09 18:20 ` [PATCH 2/5] MIPS: ralink: fix cpu clock of mt7621 and add dt clk devices Chuanhong Guo
@ 2019-07-22 21:50 ` Stephen Boyd
0 siblings, 0 replies; 10+ messages in thread
From: Stephen Boyd @ 2019-07-22 21:50 UTC (permalink / raw)
To: open list:COMMON CLK FRAMEWORK, open list:MIPS,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:STAGING SUBSYSTEM, Chuanhong Guo, open list
Cc: Michael Turquette, Rob Herring, Mark Rutland, Ralf Baechle,
Paul Burton, James Hogan, John Crispin, Greg Kroah-Hartman,
Weijie Gao, NeilBrown, Chuanhong Guo
Quoting Chuanhong Guo (2019-07-09 11:20:15)
> For a long time the mt7621 uses a fixed cpu clock which causes a problem
> if the cpu frequency is not 880MHz.
>
> This patch fixes the cpu clock calculation and adds the cpu/bus clkdev
> which will be used in dts.
>
> Ported from OpenWrt:
> c7ca224299 ramips: fix cpu clock of mt7621 and add dt clk devices
>
> Signed-off-by: Weijie Gao <hackpascal@gmail.com>
> Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
[...]
> diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
> index 9415be0d57b8..31158b88bcb6 100644
> --- a/arch/mips/ralink/mt7621.c
> +++ b/arch/mips/ralink/mt7621.c
> @@ -7,22 +7,22 @@
>
> #include <linux/kernel.h>
> #include <linux/init.h>
> +#include <linux/clk.h>
Is this include used?
> +#include <linux/clkdev.h>
> +#include <linux/clk-provider.h>
> +#include <dt-bindings/clock/mt7621-clk.h>
>
> #include <asm/mipsregs.h>
> #include <asm/smp-ops.h>
> #include <asm/mips-cps.h>
> #include <asm/mach-ralink/ralink_regs.h>
> #include <asm/mach-ralink/mt7621.h>
> +#include <asm/time.h>
>
> #include <pinmux.h>
>
> #include "common.h"
>
> -#define SYSC_REG_SYSCFG 0x10
> -#define SYSC_REG_CPLL_CLKCFG0 0x2c
> -#define SYSC_REG_CUR_CLK_STS 0x44
> -#define CPU_CLK_SEL (BIT(30) | BIT(31))
> -
> #define MT7621_GPIO_MODE_UART1 1
> #define MT7621_GPIO_MODE_I2C 2
> #define MT7621_GPIO_MODE_UART3_MASK 0x3
> @@ -108,49 +108,89 @@ static struct rt2880_pmx_group mt7621_pinmux_data[] = {
> { 0 }
> };
>
> +static struct clk *clks[MT7621_CLK_MAX];
> +static struct clk_onecell_data clk_data = {
> + .clks = clks,
> + .clk_num = ARRAY_SIZE(clks),
> +};
> +
> phys_addr_t mips_cpc_default_phys_base(void)
> {
> panic("Cannot detect cpc address");
> }
>
> +static struct clk *__init mt7621_add_sys_clkdev(
> + const char *id, unsigned long rate)
> +{
> + struct clk *clk;
> + int err;
> +
> + clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
> + if (IS_ERR(clk))
> + panic("failed to allocate %s clock structure", id);
> +
> + err = clk_register_clkdev(clk, id, NULL);
What's the need to use clkdev? i.e. why can't we just use clk_get() with
proper DT definitions and by passing in the right device pointer?
> + if (err)
> + panic("unable to register %s clock device", id);
> +
> + return clk;
> +}
> +
> void __init ralink_clk_init(void)
> {
> - int cpu_fdiv = 0;
> - int cpu_ffrac = 0;
> - int fbdiv = 0;
> - u32 clk_sts, syscfg;
> - u8 clk_sel = 0, xtal_mode;
> - u32 cpu_clk;
> + const static u32 prediv_tbl[] = {0, 1, 2, 2};
> + u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;
> + u32 pll, prediv, fbdiv;
> + u32 xtal_clk, cpu_clk, bus_clk;
> +
> + syscfg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
> + xtal_sel = (syscfg >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK;
>
> - if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
> - clk_sel = 1;
> + clkcfg = rt_sysc_r32(SYSC_REG_CLKCFG0);
> + clk_sel = (clkcfg >> CPU_CLK_SEL_SHIFT) & CPU_CLK_SEL_MASK;
> +
> + curclk = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
> + ffiv = (curclk >> CUR_CPU_FDIV_SHIFT) & CUR_CPU_FDIV_MASK;
> + ffrac = (curclk >> CUR_CPU_FFRAC_SHIFT) & CUR_CPU_FFRAC_MASK;
> +
> + if (xtal_sel <= 2)
> + xtal_clk = 20 * 1000 * 1000;
> + else if (xtal_sel <= 5)
> + xtal_clk = 40 * 1000 * 1000;
> + else
> + xtal_clk = 25 * 1000 * 1000;
>
> switch (clk_sel) {
> case 0:
> - clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
> - cpu_fdiv = ((clk_sts >> 8) & 0x1F);
> - cpu_ffrac = (clk_sts & 0x1F);
> - cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
> + cpu_clk = 500 * 1000 * 1000;
> break;
> -
> case 1:
> - fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
> - syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
> - xtal_mode = (syscfg >> 6) & 0x7;
> - if (xtal_mode >= 6) {
> - /* 25Mhz Xtal */
> - cpu_clk = 25 * fbdiv * 1000 * 1000;
> - } else if (xtal_mode >= 3) {
> - /* 40Mhz Xtal */
> - cpu_clk = 40 * fbdiv * 1000 * 1000;
> - } else {
> - /* 20Mhz Xtal */
> - cpu_clk = 20 * fbdiv * 1000 * 1000;
> - }
> + pll = rt_memc_r32(MEMC_REG_CPU_PLL);
> + fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK;
> + prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK;
> + cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];
> break;
> + default:
> + cpu_clk = xtal_clk;
> }
> +
> + cpu_clk = cpu_clk / ffiv * ffrac;
> + bus_clk = cpu_clk / 4;
> +
> + clks[MT7621_CLK_CPU] = mt7621_add_sys_clkdev("cpu", cpu_clk);
> + clks[MT7621_CLK_BUS] = mt7621_add_sys_clkdev("bus", bus_clk);
> +
> + pr_info("CPU Clock: %dMHz\n", cpu_clk / 1000000);
> + mips_hpt_frequency = cpu_clk / 2;
There are a few changes here. Probably the patch should be split up a
bit more to only do one thing at a time, instead of assign
mips_hpt_frequency, change the calculation code, and change the way clks
are provided on this platform.
> }
>
> +static void __init mt7621_clocks_init_dt(struct device_node *np)
> +{
> + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
> +}
> +
> +CLK_OF_DECLARE(mt7621_clk, "mediatek,mt7621-pll", mt7621_clocks_init_dt);
> +
> void __init ralink_of_remap(void)
> {
> rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
> diff --git a/arch/mips/ralink/timer-gic.c b/arch/mips/ralink/timer-gic.c
> index 944fbe0fc741..9bbaa37a0da1 100644
> --- a/arch/mips/ralink/timer-gic.c
> +++ b/arch/mips/ralink/timer-gic.c
> @@ -9,14 +9,14 @@
>
> #include <linux/of.h>
> #include <linux/clk-provider.h>
> -#include <linux/clocksource.h>
> +#include <asm/time.h>
>
> #include "common.h"
>
> void __init plat_time_init(void)
> {
> ralink_of_remap();
> -
> + ralink_clk_init();
Why can't everything flow from CLK_OF_DECLARE() for a particular node?
Even better would be to make a device driver instead of using
CLK_OF_DECLARE(), but either way this doesn't look necessary to make a
direct function call here.
> of_clk_init(NULL);
> timer_probe();
> }
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/5] dt: bindings: add mt7621-pll dt binding documentation
2019-07-09 18:20 ` [PATCH 3/5] dt: bindings: add mt7621-pll dt binding documentation Chuanhong Guo
@ 2019-07-22 21:51 ` Stephen Boyd
0 siblings, 0 replies; 10+ messages in thread
From: Stephen Boyd @ 2019-07-22 21:51 UTC (permalink / raw)
To: open list:COMMON CLK FRAMEWORK, open list:MIPS,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:STAGING SUBSYSTEM, Chuanhong Guo, open list
Cc: Michael Turquette, Rob Herring, Mark Rutland, Ralf Baechle,
Paul Burton, James Hogan, John Crispin, Greg Kroah-Hartman,
Weijie Gao, NeilBrown, Chuanhong Guo
Quoting Chuanhong Guo (2019-07-09 11:20:16)
> This commit adds device tree binding documentation for MT7621
> PLL controller.
>
> Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
> ---
> .../bindings/clock/mediatek,mt7621-pll.txt | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
> new file mode 100644
> index 000000000000..05c15062cd20
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
> @@ -0,0 +1,19 @@
> +Binding for Mediatek MT7621 PLL controller
> +
> +The PLL controller provides the 2 main clocks of the SoC: CPU and BUS.
> +
> +Required Properties:
> +- compatible: has to be "mediatek,mt7621-pll"
> +- #clock-cells: has to be one
> +
> +Optional properties:
> +- clock-output-names: should be "cpu", "bus"
> +
> +Example:
> + pll {
> + compatible = "mediatek,mt7621-pll", "syscon";
Why is this a syscon and not just part of some larger mt7621 clk
provider node?
> +
> + #clock-cells = <1>;
> + clock-output-names = "cpu", "bus";
> + };
> +
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-07-22 21:51 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-07-09 18:20 [PATCH 0/5] MIPS: ralink: add CPU clock detection for MT7621 Chuanhong Guo
2019-07-09 18:20 ` [PATCH 1/5] MIPS: ralink: add dt binding header for mt7621-pll Chuanhong Guo
2019-07-22 21:40 ` Stephen Boyd
2019-07-09 18:20 ` [PATCH 2/5] MIPS: ralink: fix cpu clock of mt7621 and add dt clk devices Chuanhong Guo
2019-07-22 21:50 ` Stephen Boyd
2019-07-09 18:20 ` [PATCH 3/5] dt: bindings: add mt7621-pll dt binding documentation Chuanhong Guo
2019-07-22 21:51 ` Stephen Boyd
2019-07-09 18:20 ` [PATCH 4/5] staging: mt7621-dts: add dt nodes for mt7621-pll Chuanhong Guo
2019-07-10 6:46 ` Chuanhong Guo
2019-07-09 18:20 ` [PATCH 5/5] staging: mt7621-dts: fix register range of memc node in mt7621.dtsi Chuanhong Guo
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