From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>,
<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<kishon@ti.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>,
<jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>
Cc: <digetx@gmail.com>, <mperttunen@nvidia.com>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
<mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
<sagar.tv@gmail.com>
Subject: [PATCH V13 08/12] dt-bindings: Add PCIe supports-clkreq property
Date: Wed, 10 Jul 2019 11:52:08 +0530 [thread overview]
Message-ID: <20190710062212.1745-9-vidyas@nvidia.com> (raw)
In-Reply-To: <20190710062212.1745-1-vidyas@nvidia.com>
Some host controllers need to know the existence of clkreq signal routing to
downstream devices to be able to advertise low power features like ASPM L1
substates. Without clkreq signal routing being present, enabling ASPM L1 sub
states might lead to downstream devices falling off the bus. Hence a new device
tree property 'supports-clkreq' is added to make such host controllers
aware of clkreq signal routing to downstream devices.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Thierry Reding <treding@nvidia.com>
---
V13:
* None
V12:
* Rebased on top of linux-next top of the tree
V11:
* None
V10:
* None
V9:
* None
V8:
* None
V7:
* None
V6:
* s/Documentation\/devicetree/dt-bindings/ in the subject
V5:
* None
V4:
* Rebased on top of linux-next top of the tree
V3:
* None
V2:
* This is a new patch in v2 series
Documentation/devicetree/bindings/pci/pci.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt
index 2a5d91024059..29bcbd88f457 100644
--- a/Documentation/devicetree/bindings/pci/pci.txt
+++ b/Documentation/devicetree/bindings/pci/pci.txt
@@ -27,6 +27,11 @@ driver implementation may support the following properties:
- reset-gpios:
If present this property specifies PERST# GPIO. Host drivers can parse the
GPIO and apply fundamental reset to endpoints.
+- supports-clkreq:
+ If present this property specifies that CLKREQ signal routing exists from
+ root port to downstream device and host bridge drivers can do programming
+ which depends on CLKREQ signal existence. For example, programming root port
+ not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
PCI-PCI Bridge properties
-------------------------
--
2.17.1
next prev parent reply other threads:[~2019-07-10 6:23 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-10 6:22 [PATCH V13 00/12] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-07-10 6:22 ` [PATCH V13 01/12] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-07-10 20:14 ` Bjorn Helgaas
2019-07-10 6:22 ` [PATCH V13 02/12] PCI: Disable MSI for Tegra root ports Vidya Sagar
2019-07-10 6:22 ` [PATCH V13 03/12] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-07-10 6:22 ` [PATCH V13 04/12] PCI: dwc: Move config space capability search API Vidya Sagar
2019-07-10 6:22 ` [PATCH V13 05/12] PCI: dwc: Add ext " Vidya Sagar
2019-07-10 10:37 ` Lorenzo Pieralisi
2019-07-10 11:27 ` Vidya Sagar
2019-07-10 14:19 ` Lorenzo Pieralisi
2019-07-10 6:22 ` [PATCH V13 06/12] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-07-10 6:22 ` [PATCH V13 07/12] PCI: dwc: Add support to enable " Vidya Sagar
2019-07-10 6:22 ` Vidya Sagar [this message]
2019-07-10 15:28 ` [PATCH V13 08/12] dt-bindings: Add PCIe supports-clkreq property Lorenzo Pieralisi
2019-07-10 17:14 ` Vidya Sagar
2019-07-10 6:22 ` [PATCH V13 09/12] dt-bindings: PCI: tegra: Add device tree support for Tegra194 Vidya Sagar
2019-07-10 6:22 ` [PATCH V13 10/12] dt-bindings: PHY: P2U: Add Tegra194 P2U block Vidya Sagar
2019-07-10 6:22 ` [PATCH V13 11/12] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-07-10 6:22 ` [PATCH V13 12/12] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-07-10 17:02 ` Lorenzo Pieralisi
2019-07-10 17:26 ` Vidya Sagar
2019-07-11 12:54 ` Lorenzo Pieralisi
2019-07-12 15:32 ` Vidya Sagar
2019-07-12 16:07 ` Lorenzo Pieralisi
2019-07-13 7:04 ` Vidya Sagar
2019-07-16 11:22 ` Lorenzo Pieralisi
2019-07-16 19:00 ` Bjorn Helgaas
2019-07-23 14:28 ` Vidya Sagar
2019-07-23 14:44 ` Vidya Sagar
2019-07-30 15:49 ` Lorenzo Pieralisi
2019-08-02 12:06 ` Vidya Sagar
2019-08-05 14:01 ` Lorenzo Pieralisi
2019-08-05 16:54 ` Vidya Sagar
2019-08-06 14:51 ` Lorenzo Pieralisi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190710062212.1745-9-vidyas@nvidia.com \
--to=vidyas@nvidia.com \
--cc=bhelgaas@google.com \
--cc=catalin.marinas@arm.com \
--cc=devicetree@vger.kernel.org \
--cc=digetx@gmail.com \
--cc=gustavo.pimentel@synopsys.com \
--cc=jingoohan1@gmail.com \
--cc=jonathanh@nvidia.com \
--cc=kishon@ti.com \
--cc=kthota@nvidia.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=mark.rutland@arm.com \
--cc=mmaddireddy@nvidia.com \
--cc=mperttunen@nvidia.com \
--cc=robh+dt@kernel.org \
--cc=sagar.tv@gmail.com \
--cc=thierry.reding@gmail.com \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).