From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57B2FC74A21 for ; Wed, 10 Jul 2019 14:19:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 354B52064B for ; Wed, 10 Jul 2019 14:19:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727363AbfGJOTW (ORCPT ); Wed, 10 Jul 2019 10:19:22 -0400 Received: from foss.arm.com ([217.140.110.172]:34390 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725911AbfGJOTV (ORCPT ); Wed, 10 Jul 2019 10:19:21 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A34B72B; Wed, 10 Jul 2019 07:19:20 -0700 (PDT) Received: from e121166-lin.cambridge.arm.com (unknown [10.1.196.255]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 17BC03F71F; Wed, 10 Jul 2019 07:19:17 -0700 (PDT) Date: Wed, 10 Jul 2019 15:19:08 +0100 From: Lorenzo Pieralisi To: Vidya Sagar Cc: bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, thierry.reding@gmail.com, jonathanh@nvidia.com, kishon@ti.com, catalin.marinas@arm.com, will.deacon@arm.com, jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, digetx@gmail.com, mperttunen@nvidia.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kthota@nvidia.com, mmaddireddy@nvidia.com, sagar.tv@gmail.com Subject: Re: [PATCH V13 05/12] PCI: dwc: Add ext config space capability search API Message-ID: <20190710141900.GA8781@e121166-lin.cambridge.arm.com> References: <20190710062212.1745-1-vidyas@nvidia.com> <20190710062212.1745-6-vidyas@nvidia.com> <20190710103709.GA4063@e121166-lin.cambridge.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jul 10, 2019 at 04:57:23PM +0530, Vidya Sagar wrote: > On 7/10/2019 4:07 PM, Lorenzo Pieralisi wrote: > > On Wed, Jul 10, 2019 at 11:52:05AM +0530, Vidya Sagar wrote: > > > Add extended configuration space capability search API using struct dw_pcie * > > > pointer > > > > Sentences are terminated with a period and this is v13 not v1, which > > proves that you do not read the commit logs you write. > > > > I need you guys to understand that I can't rewrite commit logs all > > the time, I do not want to go as far as not accepting your patches > > anymore so please do pay attention to commit log details they > > are as important as the code itself. > > > > https://lore.kernel.org/linux-pci/20171026223701.GA25649@bhelgaas-glaptop.roam.corp.google.com/ > My sincere apologies. > Since I didn't touch this patch much all through this series, I missed it. > I'll make a point to not make such mistakes again. > Do you want me to send a new version fixing it? I will update it, I just wanted to get the point across, no problems. Lorenzo > Thanks, > Vidya Sagar > > > > > Thanks, > > Lorenzo > > > > > Signed-off-by: Vidya Sagar > > > Acked-by: Gustavo Pimentel > > > Acked-by: Thierry Reding > > > --- > > > V13: > > > * None > > > > > > V12: > > > * None > > > > > > V11: > > > * None > > > > > > V10: > > > * None > > > > > > V9: > > > * Added Acked-by from Thierry > > > > > > V8: > > > * Changed data types of return and arguments to be inline with data being returned > > > and passed. > > > > > > V7: > > > * None > > > > > > V6: > > > * None > > > > > > V5: > > > * None > > > > > > V4: > > > * None > > > > > > V3: > > > * None > > > > > > V2: > > > * This is a new patch in v2 series > > > > > > drivers/pci/controller/dwc/pcie-designware.c | 41 ++++++++++++++++++++ > > > drivers/pci/controller/dwc/pcie-designware.h | 1 + > > > 2 files changed, 42 insertions(+) > > > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > > > index 7818b4febb08..181449e342f1 100644 > > > --- a/drivers/pci/controller/dwc/pcie-designware.c > > > +++ b/drivers/pci/controller/dwc/pcie-designware.c > > > @@ -53,6 +53,47 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) > > > } > > > EXPORT_SYMBOL_GPL(dw_pcie_find_capability); > > > +static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, > > > + u8 cap) > > > +{ > > > + u32 header; > > > + int ttl; > > > + int pos = PCI_CFG_SPACE_SIZE; > > > + > > > + /* minimum 8 bytes per capability */ > > > + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; > > > + > > > + if (start) > > > + pos = start; > > > + > > > + header = dw_pcie_readl_dbi(pci, pos); > > > + /* > > > + * If we have no capabilities, this is indicated by cap ID, > > > + * cap version and next pointer all being 0. > > > + */ > > > + if (header == 0) > > > + return 0; > > > + > > > + while (ttl-- > 0) { > > > + if (PCI_EXT_CAP_ID(header) == cap && pos != start) > > > + return pos; > > > + > > > + pos = PCI_EXT_CAP_NEXT(header); > > > + if (pos < PCI_CFG_SPACE_SIZE) > > > + break; > > > + > > > + header = dw_pcie_readl_dbi(pci, pos); > > > + } > > > + > > > + return 0; > > > +} > > > + > > > +u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) > > > +{ > > > + return dw_pcie_find_next_ext_capability(pci, 0, cap); > > > +} > > > +EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); > > > + > > > int dw_pcie_read(void __iomem *addr, int size, u32 *val) > > > { > > > if (!IS_ALIGNED((uintptr_t)addr, size)) { > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > > > index d8c66a6827dc..11c223471416 100644 > > > --- a/drivers/pci/controller/dwc/pcie-designware.h > > > +++ b/drivers/pci/controller/dwc/pcie-designware.h > > > @@ -252,6 +252,7 @@ struct dw_pcie { > > > container_of((endpoint), struct dw_pcie, ep) > > > u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); > > > +u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap); > > > int dw_pcie_read(void __iomem *addr, int size, u32 *val); > > > int dw_pcie_write(void __iomem *addr, int size, u32 val); > > > -- > > > 2.17.1 > > > >