From: Stephen Boyd <sboyd@kernel.org>
To: "open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>,
"open list:MIPS" <linux-mips@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
"open list:STAGING SUBSYSTEM" <devel@driverdev.osuosl.org>,
Chuanhong Guo <gch981213@gmail.com>,
open list <linux-kernel@vger.kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Ralf Baechle <ralf@linux-mips.org>,
Paul Burton <paul.burton@mips.com>,
James Hogan <jhogan@kernel.org>, John Crispin <john@phrozen.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Weijie Gao <hackpascal@gmail.com>, NeilBrown <neil@brown.name>,
Chuanhong Guo <gch981213@gmail.com>
Subject: Re: [PATCH 3/5] dt: bindings: add mt7621-pll dt binding documentation
Date: Mon, 22 Jul 2019 14:51:35 -0700 [thread overview]
Message-ID: <20190722215136.1FC9121951@mail.kernel.org> (raw)
In-Reply-To: <20190709182018.23193-4-gch981213@gmail.com>
Quoting Chuanhong Guo (2019-07-09 11:20:16)
> This commit adds device tree binding documentation for MT7621
> PLL controller.
>
> Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
> ---
> .../bindings/clock/mediatek,mt7621-pll.txt | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
> new file mode 100644
> index 000000000000..05c15062cd20
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
> @@ -0,0 +1,19 @@
> +Binding for Mediatek MT7621 PLL controller
> +
> +The PLL controller provides the 2 main clocks of the SoC: CPU and BUS.
> +
> +Required Properties:
> +- compatible: has to be "mediatek,mt7621-pll"
> +- #clock-cells: has to be one
> +
> +Optional properties:
> +- clock-output-names: should be "cpu", "bus"
> +
> +Example:
> + pll {
> + compatible = "mediatek,mt7621-pll", "syscon";
Why is this a syscon and not just part of some larger mt7621 clk
provider node?
> +
> + #clock-cells = <1>;
> + clock-output-names = "cpu", "bus";
> + };
> +
next prev parent reply other threads:[~2019-07-22 21:51 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-09 18:20 [PATCH 0/5] MIPS: ralink: add CPU clock detection for MT7621 Chuanhong Guo
2019-07-09 18:20 ` [PATCH 1/5] MIPS: ralink: add dt binding header for mt7621-pll Chuanhong Guo
2019-07-22 21:40 ` Stephen Boyd
2019-07-09 18:20 ` [PATCH 2/5] MIPS: ralink: fix cpu clock of mt7621 and add dt clk devices Chuanhong Guo
2019-07-22 21:50 ` Stephen Boyd
2019-07-09 18:20 ` [PATCH 3/5] dt: bindings: add mt7621-pll dt binding documentation Chuanhong Guo
2019-07-22 21:51 ` Stephen Boyd [this message]
2019-07-09 18:20 ` [PATCH 4/5] staging: mt7621-dts: add dt nodes for mt7621-pll Chuanhong Guo
2019-07-10 6:46 ` Chuanhong Guo
2019-07-09 18:20 ` [PATCH 5/5] staging: mt7621-dts: fix register range of memc node in mt7621.dtsi Chuanhong Guo
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