From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 231A6C7618B for ; Tue, 23 Jul 2019 09:27:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EB3A7223BA for ; Tue, 23 Jul 2019 09:27:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=amazon.com header.i=@amazon.com header.b="qcASuAkI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387984AbfGWJ1l (ORCPT ); Tue, 23 Jul 2019 05:27:41 -0400 Received: from smtp-fw-33001.amazon.com ([207.171.190.10]:21677 "EHLO smtp-fw-33001.amazon.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727408AbfGWJ1j (ORCPT ); Tue, 23 Jul 2019 05:27:39 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1563874058; x=1595410058; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=sNQOZhJUfbz+nC7+KNBC3O+NbzfXKJgSiWivUBW5VoI=; b=qcASuAkIsMZsG9v/nw6IcqIhr3Y/1w/FqHW1qY2T1aWFj2nocQS0/N9q gflEIeS6gDssttBZ32bdi8ZnIq4rqFQssQSYETY9x2QfbWlXI/kkCgQQ2 bGgraaEsjeQFuJ5SJof6tzvdd+baQCu9mDzSE8Cg05J5wu8JDAfPzRfAd s=; X-IronPort-AV: E=Sophos;i="5.64,298,1559520000"; d="scan'208";a="812905282" Received: from sea3-co-svc-lb6-vlan3.sea.amazon.com (HELO email-inbound-relay-2c-6f38efd9.us-west-2.amazon.com) ([10.47.22.38]) by smtp-border-fw-out-33001.sea14.amazon.com with ESMTP; 23 Jul 2019 09:27:38 +0000 Received: from EX13MTAUWA001.ant.amazon.com (pdx4-ws-svc-p6-lb7-vlan3.pdx.amazon.com [10.170.41.166]) by email-inbound-relay-2c-6f38efd9.us-west-2.amazon.com (Postfix) with ESMTPS id D4609A1C2A; Tue, 23 Jul 2019 09:27:37 +0000 (UTC) Received: from EX13D13UWA001.ant.amazon.com (10.43.160.136) by EX13MTAUWA001.ant.amazon.com (10.43.160.58) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Tue, 23 Jul 2019 09:27:37 +0000 Received: from u9ff250417f405e.ant.amazon.com (10.43.161.85) by EX13D13UWA001.ant.amazon.com (10.43.160.136) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Tue, 23 Jul 2019 09:27:32 +0000 From: Jonathan Chocron To: , , , , , CC: , , , , , , , , , , , Subject: [PATCH v3 7/8] PCI: dw: Add validation that PCIe core is set to correct mode Date: Tue, 23 Jul 2019 12:27:10 +0300 Message-ID: <20190723092711.11786-3-jonnyc@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190723092529.11310-1-jonnyc@amazon.com> References: <20190723092529.11310-1-jonnyc@amazon.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.43.161.85] X-ClientProxiedBy: EX13D27UWB003.ant.amazon.com (10.43.161.195) To EX13D13UWA001.ant.amazon.com (10.43.160.136) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some PCIe controllers can be set to either Host or EP according to some early boot FW. To make sure there is no discrepancy (e.g. FW configured the port to EP mode while the DT specifies it as a host bridge or vice versa), a check has been added for each mode. Signed-off-by: Jonathan Chocron Acked-by: Gustavo Pimentel --- drivers/pci/controller/dwc/pcie-designware-ep.c | 8 ++++++++ drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 2bf5a35c0570..00e59a134b93 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -531,6 +531,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) int ret; u32 reg; void *addr; + u8 hdr_type; unsigned int nbars; unsigned int offset; struct pci_epc *epc; @@ -543,6 +544,13 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) return -EINVAL; } + hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE); + if (hdr_type != PCI_HEADER_TYPE_NORMAL) { + dev_err(pci->dev, "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n", + hdr_type); + return -EIO; + } + ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows); if (ret < 0) { dev_err(dev, "Unable to read *num-ib-windows* property\n"); diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index f93252d0da5b..d2ca748e4c85 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -323,6 +323,7 @@ int dw_pcie_host_init(struct pcie_port *pp) struct pci_bus *child; struct pci_host_bridge *bridge; struct resource *cfg_res; + u8 hdr_type; int ret; raw_spin_lock_init(&pci->pp.lock); @@ -396,6 +397,13 @@ int dw_pcie_host_init(struct pcie_port *pp) } } + hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE); + if (hdr_type != PCI_HEADER_TYPE_BRIDGE) { + dev_err(pci->dev, "PCIe controller is not set to bridge type (hdr_type: 0x%x)!\n", + hdr_type); + return -EIO; + } + pp->mem_base = pp->mem->start; if (!pp->va_cfg0_base) { -- 2.17.1