From: Tony Lindgren <tony@atomide.com>
To: Suman Anna <s-anna@ti.com>
Cc: linux-omap@vger.kernel.org, Dave Gerlach <d-gerlach@ti.com>,
Faiz Abbas <faiz_abbas@ti.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Keerthy <j-keerthy@ti.com>, Nishanth Menon <nm@ti.com>,
Peter Ujfalusi <peter.ujfalusi@ti.com>,
Roger Quadros <rogerq@ti.com>, Tero Kristo <t-kristo@ti.com>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 5/8] ARM: dts: Drop bogus ahclkr clocks for dra7 mcasp 3 to 8
Date: Tue, 23 Jul 2019 23:47:58 -0700 [thread overview]
Message-ID: <20190724064758.GU5447@atomide.com> (raw)
In-Reply-To: <2c750847-700e-c835-ee53-a656b363c36c@ti.com>
* Suman Anna <s-anna@ti.com> [190723 21:02]:
> Hi Tony,
>
> On 7/23/19 6:28 AM, Tony Lindgren wrote:
> > The ahclkr clkctrl clock bit 28 only exists for mcasp 1 and 2 on dra7.
> > Otherwise we get the following warning on beagle-x15:
...
> > @@ -2962,9 +2958,8 @@
> > <SYSC_IDLE_SMART>;
> > /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
> > clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
> > - <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>,
> > - <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 28>;
> > - clock-names = "fck", "ahclkx", "ahclkr";
> > + <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
> > + clock-names = "fck", "ahclkx";
>
> The equivalent change to MCASP8 is missing.
Thanks for spotting it, probably should be set up the same way as
MCASP4 too looking at the TRM.
Tero, care to check the dra7 mcasp clocks we have defined?
$ grep MCASP drivers/clk/ti/clk-7xx.c
{ DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0000:22" },
{ DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" },
{ DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" },
{ DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" },
{ DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:24" },
{ DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" },
{ DRA7_L4PER2_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01f8:22" },
{ DRA7_L4PER2_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01fc:22" },
Is bit 24 above correct for MCASP8 or should it too be 22 like
adjacent MCASP4 in the TRM?
Regards,
Tony
next prev parent reply other threads:[~2019-07-24 6:48 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-23 11:28 [PATCH 0/8] ti-sysc related warning fixes for v5.3-rc cycle Tony Lindgren
2019-07-23 11:28 ` [PATCH 1/8] ARM: OMAP2+: Fix missing SYSC_HAS_RESET_STATUS for dra7 epwmss Tony Lindgren
2019-07-23 18:16 ` Suman Anna
2019-07-23 11:28 ` [PATCH 2/8] ARM: OMAP2+: Remove unconfigured midlemode for am3 lcdc Tony Lindgren
2019-07-23 19:03 ` Suman Anna
2019-07-24 5:50 ` Keerthy
2019-07-24 6:31 ` Tony Lindgren
2019-07-24 18:28 ` Suman Anna
2019-08-13 10:47 ` Tony Lindgren
2019-08-13 11:04 ` Jyri Sarha
2019-08-13 11:29 ` Tony Lindgren
2019-07-23 11:28 ` [PATCH 3/8] bus: ti-sysc: Fix handling of forced idle Tony Lindgren
2019-07-23 18:31 ` Suman Anna
2019-07-23 11:28 ` [PATCH 4/8] bus: ti-sysc: Fix using configured sysc mask value Tony Lindgren
2019-07-23 11:28 ` [PATCH 5/8] ARM: dts: Drop bogus ahclkr clocks for dra7 mcasp 3 to 8 Tony Lindgren
2019-07-23 21:01 ` Suman Anna
2019-07-24 6:47 ` Tony Lindgren [this message]
2019-09-17 7:21 ` Tero Kristo
2019-09-18 15:51 ` Tony Lindgren
2019-07-23 11:28 ` [PATCH 6/8] ARM: dts: Fix flags for gpio7 Tony Lindgren
2019-07-23 21:58 ` Suman Anna
2019-07-23 11:28 ` [PATCH 7/8] ARM: dts: Fix incorrect dcan register mapping for am3, am4 and dra7 Tony Lindgren
2019-07-23 11:28 ` [PATCH 8/8] ARM: dts: Fix lcdc sysc flags for am3 Tony Lindgren
2019-07-24 5:52 ` [PATCH 0/8] ti-sysc related warning fixes for v5.3-rc cycle Keerthy
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