From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.6 required=3.0 tests=DATE_IN_PAST_06_12, DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C0F9C7618B for ; Thu, 25 Jul 2019 05:49:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E50F220657 for ; Thu, 25 Jul 2019 05:49:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1564033753; bh=kkM3PYHvESHIAMs0LP+YjVPBtapyrJucRdUp2CIYp7o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=r2eazFRu6KnySVULy7z0+QbvX6k86PiPjsYcbNCqCe0wGc5h5vMauoceCSPI07E1X 3D6sBDQSa5QZ5Hi4r5NWNzC4GV9TaVqLGwkuZ3op1g4WTUM6zl3s8wi7d9sfNgcGU3 Ee3vlgor06fC1ACsyvwJnWLD2Pz6n5omgNFv/pSI= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728991AbfGYFtL (ORCPT ); Thu, 25 Jul 2019 01:49:11 -0400 Received: from mail.kernel.org ([198.145.29.99]:59998 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405032AbfGYFoq (ORCPT ); Thu, 25 Jul 2019 01:44:46 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 4D87621850; Thu, 25 Jul 2019 05:44:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1564033485; bh=kkM3PYHvESHIAMs0LP+YjVPBtapyrJucRdUp2CIYp7o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JcqWml9YZR5MhY+UNsihMkVOEaXv7toL3ai5PeT0clCB68RbAaCz6sNRjARTi/SIW 4KK5hCitkJzhwakJi6rPaFArcuNrXUhuBqKZ+hNnDZ/QvVax8mwBS7NeggOhji/k5t r5LCk1gz2IYqjs/qkj/eMFfqVXt6qlQQ/6D5b/dc= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Kim Phillips , "Peter Zijlstra (Intel)" , Alexander Shishkin , Arnaldo Carvalho de Melo , Borislav Petkov , Gary Hook , "H. Peter Anvin" , Janakarajan Natarajan , Jiri Olsa , Linus Torvalds , Martin Liska , Namhyung Kim , Pu Wen , Stephane Eranian , Suravee Suthikulpanit , Thomas Gleixner , Vince Weaver , Ingo Molnar Subject: [PATCH 4.19 226/271] perf/x86/amd/uncore: Set the thread mask for F17h L3 PMCs Date: Wed, 24 Jul 2019 21:21:35 +0200 Message-Id: <20190724191714.528520010@linuxfoundation.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190724191655.268628197@linuxfoundation.org> References: <20190724191655.268628197@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kim Phillips commit 2f217d58a8a086d3399fecce39fb358848e799c4 upstream. Fill in the L3 performance event select register ThreadMask bitfield, to enable per hardware thread accounting. Signed-off-by: Kim Phillips Signed-off-by: Peter Zijlstra (Intel) Cc: Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Borislav Petkov Cc: Gary Hook Cc: H. Peter Anvin Cc: Janakarajan Natarajan Cc: Jiri Olsa Cc: Linus Torvalds Cc: Martin Liska Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Pu Wen Cc: Stephane Eranian Cc: Suravee Suthikulpanit Cc: Thomas Gleixner Cc: Vince Weaver Link: https://lkml.kernel.org/r/20190628215906.4276-2-kim.phillips@amd.com Signed-off-by: Ingo Molnar Signed-off-by: Greg Kroah-Hartman --- arch/x86/events/amd/uncore.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -210,15 +210,22 @@ static int amd_uncore_event_init(struct hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB; hwc->idx = -1; + if (event->cpu < 0) + return -EINVAL; + /* * SliceMask and ThreadMask need to be set for certain L3 events in * Family 17h. For other events, the two fields do not affect the count. */ - if (l3_mask && is_llc_event(event)) - hwc->config |= (AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK); + if (l3_mask && is_llc_event(event)) { + int thread = 2 * (cpu_data(event->cpu).cpu_core_id % 4); - if (event->cpu < 0) - return -EINVAL; + if (smp_num_siblings > 1) + thread += cpu_data(event->cpu).apicid & 1; + + hwc->config |= (1ULL << (AMD64_L3_THREAD_SHIFT + thread) & + AMD64_L3_THREAD_MASK) | AMD64_L3_SLICE_MASK; + } uncore = event_to_amd_uncore(event); if (!uncore)