From: Yang Weijiang <weijiang.yang@intel.com>
To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
sean.j.christopherson@intel.com, pbonzini@redhat.com
Cc: mst@redhat.com, rkrcmar@redhat.com, jmattson@google.com,
Yang Weijiang <weijiang.yang@intel.com>
Subject: [PATCH v6 1/8] KVM: VMX: Define CET VMCS fields and control bits
Date: Thu, 25 Jul 2019 11:12:39 +0800 [thread overview]
Message-ID: <20190725031246.8296-2-weijiang.yang@intel.com> (raw)
In-Reply-To: <20190725031246.8296-1-weijiang.yang@intel.com>
CET(Control-flow Enforcement Technology) is an upcoming Intel(R)
processor feature that blocks Return/Jump-Oriented Programming(ROP)
attacks. It provides the following capabilities to defend
against ROP/JOP style control-flow subversion attacks:
Shadow Stack (SHSTK):
A second stack for program which is used exclusively for
control transfer operations.
Indirect Branch Tracking (IBT):
Code branching protection to defend against jump/call oriented
programming.
Several new CET MSRs are defined in kernel to support CET:
MSR_IA32_{U,S}_CET: Controls the CET settings for user
mode and suervisor mode respectively.
MSR_IA32_PL{0,1,2,3}_SSP: Stores shadow stack pointers for
CPL-0,1,2,3 level respectively.
MSR_IA32_INT_SSP_TAB: Stores base address of shadow stack
pointer table.
Two XSAVES state bits are introduced for CET:
IA32_XSS:[bit 11]: For saving/restoring user mode CET states
IA32_XSS:[bit 12]: For saving/restoring supervisor mode CET states.
Six VMCS fields are introduced for CET:
{HOST,GUEST}_S_CET: Stores CET settings for supervisor mode.
{HOST,GUEST}_SSP: Stores shadow stack pointer for supervisor mode.
{HOST,GUEST}_INTR_SSP_TABLE: Stores base address of shadow stack pointer
table.
If VM_EXIT_LOAD_HOST_CET_STATE = 1, the host's CET MSRs are restored
from below VMCS fields at VM-Exit:
HOST_S_CET
HOST_SSP
HOST_INTR_SSP_TABLE
If VM_ENTRY_LOAD_GUEST_CET_STATE = 1, the guest's CET MSRs are loaded
from below VMCS fields at VM-Entry:
GUEST_S_CET
GUEST_SSP
GUEST_INTR_SSP_TABLE
Co-developed-by: Zhang Yi Z <yi.z.zhang@linux.intel.com>
Signed-off-by: Zhang Yi Z <yi.z.zhang@linux.intel.com>
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
---
arch/x86/include/asm/vmx.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index a39136b0d509..68bca290a203 100644
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -90,6 +90,7 @@
#define VM_EXIT_CLEAR_BNDCFGS 0x00800000
#define VM_EXIT_PT_CONCEAL_PIP 0x01000000
#define VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
+#define VM_EXIT_LOAD_HOST_CET_STATE 0x10000000
#define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff
@@ -103,6 +104,7 @@
#define VM_ENTRY_LOAD_BNDCFGS 0x00010000
#define VM_ENTRY_PT_CONCEAL_PIP 0x00020000
#define VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
+#define VM_ENTRY_LOAD_GUEST_CET_STATE 0x00100000
#define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff
@@ -321,6 +323,9 @@ enum vmcs_field {
GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
GUEST_SYSENTER_ESP = 0x00006824,
GUEST_SYSENTER_EIP = 0x00006826,
+ GUEST_S_CET = 0x00006828,
+ GUEST_SSP = 0x0000682a,
+ GUEST_INTR_SSP_TABLE = 0x0000682c,
HOST_CR0 = 0x00006c00,
HOST_CR3 = 0x00006c02,
HOST_CR4 = 0x00006c04,
@@ -333,6 +338,9 @@ enum vmcs_field {
HOST_IA32_SYSENTER_EIP = 0x00006c12,
HOST_RSP = 0x00006c14,
HOST_RIP = 0x00006c16,
+ HOST_S_CET = 0x00006c18,
+ HOST_SSP = 0x00006c1a,
+ HOST_INTR_SSP_TABLE = 0x00006c1c
};
/*
--
2.17.2
next prev parent reply other threads:[~2019-07-25 3:11 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-25 3:12 [PATCH v6 0/8] Introduce support for Guest CET feature Yang Weijiang
2019-07-25 3:12 ` Yang Weijiang [this message]
2019-07-25 3:12 ` [PATCH v6 2/8] KVM: x86: Add a helper function for CPUID(0xD,n>=1) enumeration Yang Weijiang
2019-08-12 22:18 ` Sean Christopherson
2019-08-13 6:11 ` Yang Weijiang
2019-07-25 3:12 ` [PATCH v6 3/8] KVM: x86: Implement CET CPUID enumeration for Guest Yang Weijiang
2019-08-13 0:06 ` Sean Christopherson
2019-08-13 5:27 ` Yang Weijiang
2019-07-25 3:12 ` [PATCH v6 4/8] KVM: VMX: Pass through CET related MSRs to Guest Yang Weijiang
2019-08-12 23:53 ` Sean Christopherson
2019-08-13 5:49 ` Yang Weijiang
2019-07-25 3:12 ` [PATCH v6 5/8] KVM: VMX: Load Guest CET via VMCS when CET is enabled in Guest Yang Weijiang
2019-08-12 23:56 ` Sean Christopherson
2019-08-13 5:38 ` Yang Weijiang
2019-07-25 3:12 ` [PATCH v6 6/8] KVM: x86: Add CET bits setting in CR4 and XSS Yang Weijiang
2019-07-25 3:12 ` [PATCH v6 7/8] KVM: x86: Load Guest fpu state when accessing MSRs managed by XSAVES Yang Weijiang
2019-08-12 23:02 ` Sean Christopherson
2019-08-12 23:04 ` Sean Christopherson
2019-08-12 23:29 ` Sean Christopherson
2019-08-13 6:06 ` Yang Weijiang
2019-08-13 6:05 ` Yang Weijiang
2019-07-25 3:12 ` [PATCH v6 8/8] KVM: x86: Add user-space access interface for CET MSRs Yang Weijiang
2019-08-12 23:43 ` Sean Christopherson
2019-08-13 5:41 ` Yang Weijiang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190725031246.8296-2-weijiang.yang@intel.com \
--to=weijiang.yang@intel.com \
--cc=jmattson@google.com \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mst@redhat.com \
--cc=pbonzini@redhat.com \
--cc=rkrcmar@redhat.com \
--cc=sean.j.christopherson@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).