From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0912C76186 for ; Sun, 28 Jul 2019 03:14:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AA2862081B for ; Sun, 28 Jul 2019 03:14:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726366AbfG1DOM (ORCPT ); Sat, 27 Jul 2019 23:14:12 -0400 Received: from hermes.aosc.io ([199.195.250.187]:52434 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725440AbfG1DOL (ORCPT ); Sat, 27 Jul 2019 23:14:11 -0400 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 9D1716F929; Sun, 28 Jul 2019 03:14:06 +0000 (UTC) From: Icenowy Zheng To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Linus Walleij Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng , Rob Herring Subject: [PATCH v5 5/6] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board Date: Sun, 28 Jul 2019 11:12:26 +0800 Message-Id: <20190728031227.49140-6-icenowy@aosc.io> In-Reply-To: <20190728031227.49140-1-icenowy@aosc.io> References: <20190728031227.49140-1-icenowy@aosc.io> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Lichee Zero Plus is a core board made by Sipeed, with a microUSB connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash. It has a gold finger connector for expansion, and UART is available from reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or Allwinner V3L SoCs. Add the device tree binding of the basic version of the core board -- w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. Signed-off-by: Icenowy Zheng Reviewed-by: Rob Herring --- Changes in v5: - Added V3 compatible to S3 board. - Fixed S3 compatible string. No changes until v5. Patch introduced in v2. Documentation/devicetree/bindings/arm/sunxi.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 000a00d12d6a..8888f6fc68ad 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -353,6 +353,12 @@ properties: - const: licheepi,licheepi-zero - const: allwinner,sun8i-v3s + - description: Lichee Zero Plus (with S3, without eMMC/SPI Flash) + items: + - const: sipeed,lichee-zero-plus + - const: sochip,s3 + - const: allwinner,sun8i-v3 + - description: Linksprite PCDuino items: - const: linksprite,a10-pcduino -- 2.21.0