* [PATCH] arm64: dts: imx8mq-evk: Unbypass audio_pll1
@ 2019-07-28 14:08 Daniel Baluta
2019-08-03 14:56 ` Shawn Guo
0 siblings, 1 reply; 2+ messages in thread
From: Daniel Baluta @ 2019-07-28 14:08 UTC (permalink / raw)
To: shawnguo
Cc: s.hauer, festevam, linux-imx, l.stach, ccaione, abel.vesa,
baruch, andrew.smirnov, devicetree, linux-arm-kernel,
linux-kernel, shengjiu.wang, angus, Daniel Baluta
Making audio_pll1 parent of audio_pll1_bypass, will allow
setting rates multiple of 8000 for children.
After unbypass clk hierarchy looks like this:
* osc_25m
* audio_pll1
* audio_pll1_bypass
* audio_pll1_out
* sai2
* sai2_root_clk
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index e3df9b8cd9ca..05958124f173 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -118,9 +118,9 @@
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
- assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <24576000>;
+ assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <0>, <24576000>;
status = "okay";
};
--
2.17.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] arm64: dts: imx8mq-evk: Unbypass audio_pll1
2019-07-28 14:08 [PATCH] arm64: dts: imx8mq-evk: Unbypass audio_pll1 Daniel Baluta
@ 2019-08-03 14:56 ` Shawn Guo
0 siblings, 0 replies; 2+ messages in thread
From: Shawn Guo @ 2019-08-03 14:56 UTC (permalink / raw)
To: Daniel Baluta
Cc: s.hauer, festevam, linux-imx, l.stach, ccaione, abel.vesa,
baruch, andrew.smirnov, devicetree, linux-arm-kernel,
linux-kernel, shengjiu.wang, angus
On Sun, Jul 28, 2019 at 05:08:17PM +0300, Daniel Baluta wrote:
> Making audio_pll1 parent of audio_pll1_bypass, will allow
> setting rates multiple of 8000 for children.
>
> After unbypass clk hierarchy looks like this:
> * osc_25m
> * audio_pll1
> * audio_pll1_bypass
> * audio_pll1_out
> * sai2
> * sai2_root_clk
>
> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Applied, thanks.
^ permalink raw reply [flat|nested] 2+ messages in thread
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