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* [PATCH] [v5] clocksource/drivers/npcm: fix GENMASK and timer operation
@ 2019-07-29 17:03 Avi Fishman
  2019-08-21 10:11 ` Daniel Lezcano
  0 siblings, 1 reply; 3+ messages in thread
From: Avi Fishman @ 2019-07-29 17:03 UTC (permalink / raw)
  To: tmaimon77, tali.perry1, venture, yuenn, benjaminfair,
	daniel.lezcano, tglx, avifishman70
  Cc: openbmc, linux-kernel

NPCM7XX_Tx_OPER GENMASK bits where wrong,
Since NPCM7XX_REG_TICR0 register reset value of those bits was 0,
it did not cause an issue.
in npcm7xx_timer_oneshot() the original NPCM7XX_REG_TCSR0 register was
read again after masking it with ~NPCM7XX_Tx_OPER so the masking didn't
take effect.

npcm7xx_timer_periodic() was not wrong but it wrote to NPCM7XX_REG_TICR0
in a middle of read modify write to NPCM7XX_REG_TCSR0 which is
confusing.
npcm7xx_timer_oneshot() did wrong calculation

Signed-off-by: Avi Fishman <avifishman70@gmail.com>
---
 drivers/clocksource/timer-npcm7xx.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/clocksource/timer-npcm7xx.c b/drivers/clocksource/timer-npcm7xx.c
index 8a30da7f083b..9780ffd8010e 100644
--- a/drivers/clocksource/timer-npcm7xx.c
+++ b/drivers/clocksource/timer-npcm7xx.c
@@ -32,7 +32,7 @@
 #define NPCM7XX_Tx_INTEN		BIT(29)
 #define NPCM7XX_Tx_COUNTEN		BIT(30)
 #define NPCM7XX_Tx_ONESHOT		0x0
-#define NPCM7XX_Tx_OPER			GENMASK(27, 3)
+#define NPCM7XX_Tx_OPER			GENMASK(28, 27)
 #define NPCM7XX_Tx_MIN_PRESCALE		0x1
 #define NPCM7XX_Tx_TDR_MASK_BITS	24
 #define NPCM7XX_Tx_MAX_CNT		0xFFFFFF
@@ -84,8 +84,6 @@ static int npcm7xx_timer_oneshot(struct clock_event_device *evt)
 
 	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
 	val &= ~NPCM7XX_Tx_OPER;
-
-	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
 	val |= NPCM7XX_START_ONESHOT_Tx;
 	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
 
@@ -97,12 +95,11 @@ static int npcm7xx_timer_periodic(struct clock_event_device *evt)
 	struct timer_of *to = to_timer_of(evt);
 	u32 val;
 
+	writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
+
 	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
 	val &= ~NPCM7XX_Tx_OPER;
-
-	writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
 	val |= NPCM7XX_START_PERIODIC_Tx;
-
 	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
 
 	return 0;
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 3+ messages in thread
* Re: [PATCH] [v5] clocksource/drivers/npcm: fix GENMASK and timer operation
  2019-07-29 17:03 [PATCH] [v5] clocksource/drivers/npcm: fix GENMASK and timer operation Avi Fishman
@ 2019-08-21 10:11 ` Daniel Lezcano
  2019-08-21 10:42   ` Avi Fishman
  0 siblings, 1 reply; 3+ messages in thread
From: Daniel Lezcano @ 2019-08-21 10:11 UTC (permalink / raw)
  To: Avi Fishman, tmaimon77, tali.perry1, venture, yuenn, benjaminfair, tglx
  Cc: openbmc, linux-kernel

On 29/07/2019 19:03, Avi Fishman wrote:
> NPCM7XX_Tx_OPER GENMASK bits where wrong,
> Since NPCM7XX_REG_TICR0 register reset value of those bits was 0,
> it did not cause an issue.
> in npcm7xx_timer_oneshot() the original NPCM7XX_REG_TCSR0 register was
> read again after masking it with ~NPCM7XX_Tx_OPER so the masking didn't
> take effect.
> 
> npcm7xx_timer_periodic() was not wrong but it wrote to NPCM7XX_REG_TICR0
> in a middle of read modify write to NPCM7XX_REG_TCSR0 which is
> confusing.
> npcm7xx_timer_oneshot() did wrong calculation
> 
> Signed-off-by: Avi Fishman <avifishman70@gmail.com>

I've applied the patch and massaged the changelog [1].

Let me know if you disagree with it.

Please, in the future take care of adding the Fixes tag.

Thanks

  -- Daniel

[1]
https://git.linaro.org/people/daniel.lezcano/linux.git/commit/?h=clockevents/next&id=a5f6679fc81e42fcbef0184770d8a3b04c0f153e

> ---
>  drivers/clocksource/timer-npcm7xx.c | 9 +++------
>  1 file changed, 3 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/clocksource/timer-npcm7xx.c b/drivers/clocksource/timer-npcm7xx.c
> index 8a30da7f083b..9780ffd8010e 100644
> --- a/drivers/clocksource/timer-npcm7xx.c
> +++ b/drivers/clocksource/timer-npcm7xx.c
> @@ -32,7 +32,7 @@
>  #define NPCM7XX_Tx_INTEN		BIT(29)
>  #define NPCM7XX_Tx_COUNTEN		BIT(30)
>  #define NPCM7XX_Tx_ONESHOT		0x0
> -#define NPCM7XX_Tx_OPER			GENMASK(27, 3)
> +#define NPCM7XX_Tx_OPER			GENMASK(28, 27)
>  #define NPCM7XX_Tx_MIN_PRESCALE		0x1
>  #define NPCM7XX_Tx_TDR_MASK_BITS	24
>  #define NPCM7XX_Tx_MAX_CNT		0xFFFFFF
> @@ -84,8 +84,6 @@ static int npcm7xx_timer_oneshot(struct clock_event_device *evt)
>  
>  	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
>  	val &= ~NPCM7XX_Tx_OPER;
> -
> -	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
>  	val |= NPCM7XX_START_ONESHOT_Tx;
>  	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
>  
> @@ -97,12 +95,11 @@ static int npcm7xx_timer_periodic(struct clock_event_device *evt)
>  	struct timer_of *to = to_timer_of(evt);
>  	u32 val;
>  
> +	writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
> +
>  	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
>  	val &= ~NPCM7XX_Tx_OPER;
> -
> -	writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
>  	val |= NPCM7XX_START_PERIODIC_Tx;
> -
>  	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
>  
>  	return 0;
> 


-- 
 <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog


^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: [PATCH] [v5] clocksource/drivers/npcm: fix GENMASK and timer operation
  2019-08-21 10:11 ` Daniel Lezcano
@ 2019-08-21 10:42   ` Avi Fishman
  0 siblings, 0 replies; 3+ messages in thread
From: Avi Fishman @ 2019-08-21 10:42 UTC (permalink / raw)
  To: Daniel Lezcano
  Cc: Tomer Maimon, Tali Perry, Patrick Venture, Nancy Yuen,
	Benjamin Fair, Thomas Gleixner, OpenBMC Maillist,
	Linux Kernel Mailing List

Thanks Daniel,

It seems more clear now :)

Good to know about the need for Fixes tag.

On Wed, Aug 21, 2019 at 1:11 PM Daniel Lezcano
<daniel.lezcano@linaro.org> wrote:
>
> On 29/07/2019 19:03, Avi Fishman wrote:
> > NPCM7XX_Tx_OPER GENMASK bits where wrong,
> > Since NPCM7XX_REG_TICR0 register reset value of those bits was 0,
> > it did not cause an issue.
> > in npcm7xx_timer_oneshot() the original NPCM7XX_REG_TCSR0 register was
> > read again after masking it with ~NPCM7XX_Tx_OPER so the masking didn't
> > take effect.
> >
> > npcm7xx_timer_periodic() was not wrong but it wrote to NPCM7XX_REG_TICR0
> > in a middle of read modify write to NPCM7XX_REG_TCSR0 which is
> > confusing.
> > npcm7xx_timer_oneshot() did wrong calculation
> >
> > Signed-off-by: Avi Fishman <avifishman70@gmail.com>
>
> I've applied the patch and massaged the changelog [1].
>
> Let me know if you disagree with it.
>
> Please, in the future take care of adding the Fixes tag.
>
> Thanks
>
>   -- Daniel
>
> [1]
> https://git.linaro.org/people/daniel.lezcano/linux.git/commit/?h=clockevents/next&id=a5f6679fc81e42fcbef0184770d8a3b04c0f153e
>
> > ---
> >  drivers/clocksource/timer-npcm7xx.c | 9 +++------
> >  1 file changed, 3 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/clocksource/timer-npcm7xx.c b/drivers/clocksource/timer-npcm7xx.c
> > index 8a30da7f083b..9780ffd8010e 100644
> > --- a/drivers/clocksource/timer-npcm7xx.c
> > +++ b/drivers/clocksource/timer-npcm7xx.c
> > @@ -32,7 +32,7 @@
> >  #define NPCM7XX_Tx_INTEN             BIT(29)
> >  #define NPCM7XX_Tx_COUNTEN           BIT(30)
> >  #define NPCM7XX_Tx_ONESHOT           0x0
> > -#define NPCM7XX_Tx_OPER                      GENMASK(27, 3)
> > +#define NPCM7XX_Tx_OPER                      GENMASK(28, 27)
> >  #define NPCM7XX_Tx_MIN_PRESCALE              0x1
> >  #define NPCM7XX_Tx_TDR_MASK_BITS     24
> >  #define NPCM7XX_Tx_MAX_CNT           0xFFFFFF
> > @@ -84,8 +84,6 @@ static int npcm7xx_timer_oneshot(struct clock_event_device *evt)
> >
> >       val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
> >       val &= ~NPCM7XX_Tx_OPER;
> > -
> > -     val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
> >       val |= NPCM7XX_START_ONESHOT_Tx;
> >       writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
> >
> > @@ -97,12 +95,11 @@ static int npcm7xx_timer_periodic(struct clock_event_device *evt)
> >       struct timer_of *to = to_timer_of(evt);
> >       u32 val;
> >
> > +     writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
> > +
> >       val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
> >       val &= ~NPCM7XX_Tx_OPER;
> > -
> > -     writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
> >       val |= NPCM7XX_START_PERIODIC_Tx;
> > -
> >       writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
> >
> >       return 0;
> >
>
>
> --
>  <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
>
> Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
> <http://twitter.com/#!/linaroorg> Twitter |
> <http://www.linaro.org/linaro-blog/> Blog
>


-- 
Regards,
Avi

^ permalink raw reply	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2019-08-21 10:44 UTC | newest]

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2019-07-29 17:03 [PATCH] [v5] clocksource/drivers/npcm: fix GENMASK and timer operation Avi Fishman
2019-08-21 10:11 ` Daniel Lezcano
2019-08-21 10:42   ` Avi Fishman

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