From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE3C7C433FF for ; Mon, 29 Jul 2019 19:42:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AB89820C01 for ; Mon, 29 Jul 2019 19:42:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1564429347; bh=L8LWTTTAa3xAJp9P3YSmP/budIJojfLkiTbkPBeOfII=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=gspx6LLjGfqb+/zXnb73bRfG4ASNHd3h6mIKGP30XVC+u02UJKNR5mNFMiRfutxGx f3iB0F+VfD3Hl3IWUCWu8KsWsa6/cLFqYP/KQOf04r3cRWzbFa/I0UKmwaIeTjgvFg JuiacALiTRHXPMhAIV6fx3hAOLUz4VTW7PSkB4Nw= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389490AbfG2Tm0 (ORCPT ); Mon, 29 Jul 2019 15:42:26 -0400 Received: from mail.kernel.org ([198.145.29.99]:58102 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389454AbfG2TmW (ORCPT ); Mon, 29 Jul 2019 15:42:22 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 4ACDB2054F; Mon, 29 Jul 2019 19:42:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1564429341; bh=L8LWTTTAa3xAJp9P3YSmP/budIJojfLkiTbkPBeOfII=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GBLqRsYBIDGMkfO40QNF76TDPN+nwti0ugp4uiUZkF5l7YY61PZME0bMQMu7dfgCJ x5F2TPB0F6U9r2ZxJRUX3+Y1htSOyvRW0v7eru2uyoHXsEjSnh5M7eMql7F0+yVY/6 FyZqRjj/KgnCfw6wpo+v10gjNMbqdp+ghBmPcRXk= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Hou Zhiqiang , Lorenzo Pieralisi , Minghuan Lian , Subrahmanya Lingappa , Sasha Levin Subject: [PATCH 4.19 066/113] PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions Date: Mon, 29 Jul 2019 21:22:33 +0200 Message-Id: <20190729190711.292162347@linuxfoundation.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190729190655.455345569@linuxfoundation.org> References: <20190729190655.455345569@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org [ Upstream commit f7fee1b42fe4f8171a4b1cad05c61907c33c53f6 ] The inbound and outbound windows have completely separate control registers sets in the host controller MMIO space. Windows control register are accessed through an MMIO base address and an offset that depends on the window index. Since inbound and outbound windows control registers are completely separate there is no real need to use different window indexes in the inbound/outbound windows initialization routines to prevent clashing. To fix this inconsistency, change the MEM inbound window index to 0, mirroring the outbound window set-up. Signed-off-by: Hou Zhiqiang [lorenzo.pieralisi@arm.com: update commit log] Signed-off-by: Lorenzo Pieralisi Reviewed-by: Minghuan Lian Reviewed-by: Subrahmanya Lingappa Signed-off-by: Sasha Levin --- drivers/pci/controller/pcie-mobiveil.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index 2fe7ebdad2d2..a2d1e89d4867 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -553,7 +553,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) resource_size(pcie->ob_io_res)); /* memory inbound translation window */ - program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); + program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); /* Get the I/O and memory ranges from DT */ resource_list_for_each_entry_safe(win, tmp, &pcie->resources) { -- 2.20.1