From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AD78C76186 for ; Mon, 29 Jul 2019 19:31:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1877D217F4 for ; Mon, 29 Jul 2019 19:31:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1564428683; bh=L6AJrXGiOnr4csgCwVe6ZSzeFBWBhgSG7D8lgQsiOc8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=uDbWFuncNoHc19CgW6g2lzVihtWeAHMKKflGyY1jwK/tkYevPiKOJdtW5lHWYDUzw r1CmW0IgZgadoxWY/sEw2q9jzhHP9ODgPFbVzx9es3zzZfGSPzPGcj89x2lpYeDm6r 45JfUlipByI67OIRvvINcbnndhKnvUhGCa/F9GW0= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729365AbfG2TbW (ORCPT ); Mon, 29 Jul 2019 15:31:22 -0400 Received: from mail.kernel.org ([198.145.29.99]:44122 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727970AbfG2TbT (ORCPT ); Mon, 29 Jul 2019 15:31:19 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 3913F2070B; Mon, 29 Jul 2019 19:31:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1564428678; bh=L6AJrXGiOnr4csgCwVe6ZSzeFBWBhgSG7D8lgQsiOc8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LyopGth3iEc4zz+hWYJvpb4kH8PIR3ZF/SuF/s6fjN4wCxqGFkcZjJAXVQhKHDOU/ 2B3X1p+mCQqcTV/LTJfLi09X7qnZNPKosd5zxDEGqnxajim2cj6PzJX5Xskj9+aCjt fOaLG/5N675okMSscnoEYGO4YWXfrOOjwrU0fVDc= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Kim Phillips , "Peter Zijlstra (Intel)" , Alexander Shishkin , Arnaldo Carvalho de Melo , Borislav Petkov , Gary Hook , "H. Peter Anvin" , Janakarajan Natarajan , Jiri Olsa , Linus Torvalds , Martin Liska , Namhyung Kim , Pu Wen , Stephane Eranian , Suravee Suthikulpanit , Thomas Gleixner , Vince Weaver , Ingo Molnar Subject: [PATCH 4.14 153/293] perf/x86/amd/uncore: Do not set ThreadMask and SliceMask for non-L3 PMCs Date: Mon, 29 Jul 2019 21:20:44 +0200 Message-Id: <20190729190836.297738450@linuxfoundation.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190729190820.321094988@linuxfoundation.org> References: <20190729190820.321094988@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kim Phillips commit 16f4641166b10e199f0d7b68c2c5f004fef0bda3 upstream. The following commit: d7cbbe49a930 ("perf/x86/amd/uncore: Set ThreadMask and SliceMask for L3 Cache perf events") enables L3 PMC events for all threads and slices by writing 1's in 'ChL3PmcCfg' (L3 PMC PERF_CTL) register fields. Those bitfields overlap with high order event select bits in the Data Fabric PMC control register, however. So when a user requests raw Data Fabric events (-e amd_df/event=0xYYY/), the two highest order bits get inadvertently set, changing the counter select to events that don't exist, and for which no counts are read. This patch changes the logic to write the L3 masks only when dealing with L3 PMC counters. AMD Family 16h and below Northbridge (NB) counters were not affected. Signed-off-by: Kim Phillips Signed-off-by: Peter Zijlstra (Intel) Cc: Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Borislav Petkov Cc: Gary Hook Cc: H. Peter Anvin Cc: Janakarajan Natarajan Cc: Jiri Olsa Cc: Linus Torvalds Cc: Martin Liska Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Pu Wen Cc: Stephane Eranian Cc: Suravee Suthikulpanit Cc: Thomas Gleixner Cc: Vince Weaver Fixes: d7cbbe49a930 ("perf/x86/amd/uncore: Set ThreadMask and SliceMask for L3 Cache perf events") Link: https://lkml.kernel.org/r/20190628215906.4276-1-kim.phillips@amd.com Signed-off-by: Ingo Molnar Signed-off-by: Greg Kroah-Hartman --- arch/x86/events/amd/uncore.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -213,7 +213,7 @@ static int amd_uncore_event_init(struct * SliceMask and ThreadMask need to be set for certain L3 events in * Family 17h. For other events, the two fields do not affect the count. */ - if (l3_mask) + if (l3_mask && is_llc_event(event)) hwc->config |= (AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK); if (event->cpu < 0)