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From: Atish Patra <atish.patra@wdc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atish.patra@wdc.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexios Zavras <alexios.zavras@intel.com>,
	Allison Randal <allison@lohutok.net>,
	Anup Patel <anup.patel@wdc.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	devicetree@vger.kernel.org, Enrico Weigelt <info@metux.net>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Johan Hovold <johan@kernel.org>,
	linux-riscv@lists.infradead.org,
	Mark Rutland <mark.rutland@arm.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Rob Herring <robh+dt@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>
Subject: [PATCH v2 1/5] RISC-V: Remove per cpu clocksource
Date: Tue, 30 Jul 2019 18:24:14 -0700	[thread overview]
Message-ID: <20190731012418.24565-2-atish.patra@wdc.com> (raw)
In-Reply-To: <20190731012418.24565-1-atish.patra@wdc.com>

There is only one clocksource in RISC-V. The boot cpu initializes
that clocksource. No need to keep a percpu data structure.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
 drivers/clocksource/timer-riscv.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index 5e6038fbf115..09e031176bc6 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -55,7 +55,7 @@ static u64 riscv_sched_clock(void)
 	return get_cycles64();
 }
 
-static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = {
+static struct clocksource riscv_clocksource = {
 	.name		= "riscv_clocksource",
 	.rating		= 300,
 	.mask		= CLOCKSOURCE_MASK(64),
@@ -92,7 +92,6 @@ void riscv_timer_interrupt(void)
 static int __init riscv_timer_init_dt(struct device_node *n)
 {
 	int cpuid, hartid, error;
-	struct clocksource *cs;
 
 	hartid = riscv_of_processor_hartid(n);
 	if (hartid < 0) {
@@ -112,8 +111,7 @@ static int __init riscv_timer_init_dt(struct device_node *n)
 
 	pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n",
 	       __func__, cpuid, hartid);
-	cs = per_cpu_ptr(&riscv_clocksource, cpuid);
-	error = clocksource_register_hz(cs, riscv_timebase);
+	error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
 	if (error) {
 		pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
 		       error, cpuid);
-- 
2.21.0


  reply	other threads:[~2019-07-31  1:24 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-31  1:24 [PATCH v2 0/5] Miscellaneous fixes Atish Patra
2019-07-31  1:24 ` Atish Patra [this message]
2019-08-16 15:09   ` [PATCH v2 1/5] RISC-V: Remove per cpu clocksource Daniel Lezcano
2019-08-16 18:55     ` Atish Patra
2019-08-26 23:48       ` Palmer Dabbelt
2019-07-31  1:24 ` [PATCH v2 2/5] RISC-V: Add riscv_isa reprensenting ISA features common across CPUs Atish Patra
2019-07-31  4:23   ` Paul Walmsley
2019-07-31  6:27     ` Atish Patra
2019-07-31  1:24 ` [PATCH v2 3/5] RISC-V: Fix unsupported isa string info Atish Patra
2019-07-31  1:24 ` [PATCH v2 4/5] RISC-V: Export few kernel symbols Atish Patra
2019-07-31  1:24 ` [PATCH v2 5/5] dt-bindings: Update the isa string description Atish Patra
2019-07-31  4:52   ` Paul Walmsley
2019-07-31  6:43     ` Atish Patra

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