[PATCH v2 0/6] Add TI PRUSS Local Interrupt Controller IRQChip driver

[PATCH v2 0/6] Add TI PRUSS Local Interrupt Controller IRQChip driver

[Suman Anna]

Hi All,

The following is a v2 version of the series [1] that adds an IRQChip driver for
the local interrupt controller present within a Programmable Real-Time Unit and
Industrial Communication Subsystem (PRU-ICSS) present on a number of TI SoCs 
including OMAP architecture based AM335x, AM437x, AM57xx SoCs, Keystone 2 
architecture based 66AK2G SoCs, Davinci architecture based OMAP-L138/DA850 SoCs
and the latest K3 architecture based AM65x and J721E SoCs. Please see the
v1 cover-letter [1] for details about the features of this interrupt controller.
More details can be found in any of the supported SoC TRMs.
 Eg: Chapter 30.1.6 of AM5728 TRM [2]

Please see the individual patches for exact changes in each patch, following are
the main changes from v1:
 - Dropped the pruss_intc_trigger() API and patch and replaced it with a new
   patch achieving the same through irq_set_irqchip_state() callback (patch 5)
 - Added cleanup logic on INTC mapping fails and reset the mapping registers
   during unmap (patch 4)
 - Minor revisions to the bindings, no new properties introduced (patch 1)

regards
Suman

[1] https://patchwork.kernel.org/cover/11034561/
[2] http://www.ti.com/lit/pdf/spruhz6

Andrew F. Davis (1):
  irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS
    interrupts

David Lechner (1):
  irqchip/irq-pruss-intc: Implement irq_{get,set}_irqchip_state ops

Suman Anna (4):
  dt-bindings: irqchip: Add PRUSS interrupt controller bindings
  irqchip/irq-pruss-intc: Add support for shared and invalid interrupts
  irqchip/irq-pruss-intc: Add helper functions to configure internal
    mapping
  irqchip/irq-pruss-intc: Add support for ICSSG INTC on K3 SoCs

 .../interrupt-controller/ti,pruss-intc.txt    |  98 +++
 drivers/irqchip/Kconfig                       |  10 +
 drivers/irqchip/Makefile                      |   1 +
 drivers/irqchip/irq-pruss-intc.c              | 764 ++++++++++++++++++
 include/linux/irqchip/irq-pruss-intc.h        |  36 +
 5 files changed, 909 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt
 create mode 100644 drivers/irqchip/irq-pruss-intc.c
 create mode 100644 include/linux/irqchip/irq-pruss-intc.h

-- 
2.22.0

[PATCH v2 1/6] dt-bindings: irqchip: Add PRUSS interrupt controller bindings

[Suman Anna]

The Programmable Real-Time Unit Subsystem (PRUSS) contains an interrupt
controller (INTC) that can handle various system input events and post
interrupts back to the device-level initiators. The INTC can support
upto 64 input events on most SoCs with individual control configuration
and hardware prioritization. These events are mapped onto 10 output
interrupt lines through two levels of many-to-one mapping support.
Different interrupt lines are routed to the individual PRU cores or
to the host CPU or to other PRUSS instances.

The K3 AM65x and J721E SoCs have the next generation of the PRU-ICSS IP,
commonly called ICSSG. The ICSSG interrupt controller on K3 SoCs provide
a higher number of host interrupts (20 vs 10) and can handle an increased
number of input events (160 vs 64) from various SoC interrupt sources.

Add the bindings document for these interrupt controllers on all the
applicable SoCs. It covers the OMAP architecture SoCs - AM33xx, AM437x
and AM57xx; the Keystone 2 architecture based 66AK2G SoC; the Davinci
architecture based OMAPL138 SoCs, and the K3 architecture based AM65x
and J721E SoCs.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
v2:
 - Updated the interrupt-names from "hostX" to "host_intrX" and updated
   example accordingly
 - Updated the description for interrupts property
 - Used generic interrupt controller in descriptions rather than GIC
 - Added some clarifications about interrupt names to PRUSS INTC output
   interrupts
 - Picked up Rob's reviewed-by
v1: https://patchwork.kernel.org/patch/11034567/

 .../interrupt-controller/ti,pruss-intc.txt    | 98 +++++++++++++++++++
 1 file changed, 98 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt

diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt
new file mode 100644
index 000000000000..17c7b49a7f2e
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt
@@ -0,0 +1,98 @@
+PRU ICSS INTC on TI SoCs
+========================
+
+Each PRUSS has a single interrupt controller instance that is common to both
+the PRU cores. Most interrupt controllers can route 64 input events which are
+then mapped to 10 possible output interrupts through two levels of mapping.
+The input events can be triggered by either the PRUs and/or various other PRUSS
+internal and external peripherals. The first 2 output interrupts (0 & 1) are
+fed exclusively to the internal PRU cores, with the remaining 8 (2 through 9)
+connected to external interrupt controllers including the MPU and/or other
+PRUSS instances, DSPs or devices.
+
+The K3 family of SoCs can handle 160 input events that can be mapped to 20
+different possible output interrupts. The additional output interrupts (10
+through 19) are connected to new sub-modules within the ICSSG instances.
+
+This interrupt-controller node should be defined as a child node of the
+corresponding PRUSS node. The node should be named "interrupt-controller".
+Please see the overall PRUSS bindings document for additional details
+including a complete example,
+    Documentation/devicetree/bindings/soc/ti/ti,pruss.txt
+
+Required Properties:
+--------------------
+- compatible           : should be one of the following,
+                             "ti,pruss-intc" for OMAP-L13x/AM18x/DA850 SoCs,
+                                                 AM335x family of SoCs,
+                                                 AM437x family of SoCs,
+                                                 AM57xx family of SoCs
+                                                 66AK2G family of SoCs
+                             "ti,icssg-intc" for K3 AM65x & J721E family of SoCs
+- reg                  : base address and size for the PRUSS INTC sub-module
+- interrupts           : all the interrupts generated towards the main host
+                         processor in the SoC. The format depends on the
+                         interrupt specifier for the particular SoC's Arm
+                         parent interrupt controller. A shared interrupt can
+                         be skipped if the desired destination and usage is by
+                         a different processor/device.
+- interrupt-names      : should use one of the following names for each valid
+                         host event interrupt connected to Arm interrupt
+                         controller, the name should match the corresponding
+                         host event interrupt number,
+                             "host_intr0", "host_intr1", "host_intr2",
+                             "host_intr3", "host_intr4", "host_intr5",
+                             "host_intr6" or "host_intr7"
+- interrupt-controller : mark this node as an interrupt controller
+- #interrupt-cells     : should be 1. Client users shall use the PRU System
+                         event number (the interrupt source that the client
+                         is interested in) as the value of the interrupts
+                         property in their node
+
+Optional Properties:
+--------------------
+The following properties are _required_ only for some SoCs. If none of the below
+properties are defined, it implies that all the PRUSS INTC output interrupts 2
+through 9 (host_intr0 through host_intr7) are connected exclusively to the
+Arm interrupt controller.
+
+- ti,irqs-reserved     : an array of 8-bit elements of host interrupts between
+                         0 and 7 (corresponding to PRUSS INTC output interrupts
+                         2 through 9) that are not connected to the Arm
+                         interrupt controller.
+                           Eg: AM437x and 66AK2G SoCs do not have "host_intr5"
+                               interrupt connected to MPU
+- ti,irqs-shared       : an array of 8-bit elements of host interrupts between
+                         0 and 7 (corresponding to PRUSS INTC output interrupts
+                         2 through 9) that are also connected to other devices
+                         or processors in the SoC.
+                           Eg: AM65x and J721E SoCs have "host_intr5",
+                               "host_intr6" and "host_intr7" interrupts
+                               connected to MPU, and other ICSSG instances
+
+
+Example:
+--------
+
+1.	/* AM33xx PRU-ICSS */
+	pruss: pruss@0 {
+		compatible = "ti,am3356-pruss";
+		reg = <0x0 0x80000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		...
+
+		pruss_intc: interrupt-controller@20000 {
+			compatible = "ti,pruss-intc";
+			reg = <0x20000 0x2000>;
+			interrupts = <20 21 22 23 24 25 26 27>;
+			interrupt-names = "host_intr0", "host_intr1",
+					  "host_intr2", "host_intr3",
+					  "host_intr4", "host_intr5",
+					  "host_intr6", "host_intr7";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			ti,irqs-shared = /bits/ 8 <0 6 7>;
+		};
+	};
-- 
2.22.0

[PATCH v2 2/6] irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS interrupts

[Suman Anna]

From: "Andrew F. Davis" <afd@ti.com>

The Programmable Real-Time Unit Subsystem (PRUSS) contains a local
interrupt controller (INTC) that can handle various system input events
and post interrupts back to the device-level initiators. The INTC can
support upto 64 input events with individual control configuration and
hardware prioritization. These events are mapped onto 10 output interrupt
lines through two levels of many-to-one mapping support. Different
interrupt lines are routed to the individual PRU cores or to the host
CPU, or to other devices on the SoC. Some of these events are sourced
from peripherals or other sub-modules within that PRUSS, while a few
others are sourced from SoC-level peripherals/devices.

The PRUSS INTC platform driver manages this PRUSS interrupt controller
and implements an irqchip driver to provide a Linux standard way for
the PRU client users to enable/disable/ack/re-trigger a PRUSS system
event. The system events to interrupt channels and output interrupts
relies on the mapping configuration provided either through the PRU
firmware blob or via the PRU application's device tree node. The
mappings will be programmed during the boot/shutdown of a PRU core.

The PRUSS INTC module is reference counted during the interrupt
setup phase through the irqchip's irq_request_resources() and
irq_release_resources() ops. This restricts the module from being
removed as long as there are active interrupt users.

The driver currently supports and can be built for OMAP architecture
based AM335x, AM437x and AM57xx SoCs; Keystone2 architecture based
66AK2G SoCs and Davinci architecture based OMAP-L13x/AM18x/DA850 SoCs.
All of these SoCs support 64 system events, 10 interrupt channels and
10 output interrupt lines per PRUSS INTC with a few SoC integration
differences.

NOTE:
Each PRU-ICSS's INTC on AM57xx SoCs is preceded by a Crossbar that
enables multiple external events to be routed to a specific number
of input interrupt events. Any non-default external interrupt event
directed towards PRUSS needs this crossbar to be setup properly.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
v2: 
 - Addressed all of David Lechner's comments
 - Dropped irq_retrigger callback
 - Updated interrupt names from "hostX" to "host_intrX"
 - Moved host_mask variable to patch 4
v1: https://patchwork.kernel.org/patch/11034545/
v0: https://patchwork.kernel.org/patch/10795761/

 drivers/irqchip/Kconfig          |  10 +
 drivers/irqchip/Makefile         |   1 +
 drivers/irqchip/irq-pruss-intc.c | 338 +++++++++++++++++++++++++++++++
 3 files changed, 349 insertions(+)
 create mode 100644 drivers/irqchip/irq-pruss-intc.c

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 80e10f4e213a..dc6b5aa77a5d 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -471,6 +471,16 @@ config TI_SCI_INTA_IRQCHIP
 	  If you wish to use interrupt aggregator irq resources managed by the
 	  TI System Controller, say Y here. Otherwise, say N.
 
+config TI_PRUSS_INTC
+	tristate "TI PRU-ICSS Interrupt Controller"
+	depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM437X || SOC_DRA7XX || ARCH_KEYSTONE
+	select IRQ_DOMAIN
+	help
+	   This enables support for the PRU-ICSS Local Interrupt Controller
+	   present within a PRU-ICSS subsystem present on various TI SoCs.
+	   The PRUSS INTC enables various interrupts to be routed to multiple
+	   different processors within the SoC.
+
 endmenu
 
 config SIFIVE_PLIC
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 8d0fcec6ab23..a02e652ca805 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -102,3 +102,4 @@ obj-$(CONFIG_MADERA_IRQ)		+= irq-madera.o
 obj-$(CONFIG_LS1X_IRQ)			+= irq-ls1x.o
 obj-$(CONFIG_TI_SCI_INTR_IRQCHIP)	+= irq-ti-sci-intr.o
 obj-$(CONFIG_TI_SCI_INTA_IRQCHIP)	+= irq-ti-sci-inta.o
+obj-$(CONFIG_TI_PRUSS_INTC)		+= irq-pruss-intc.o
diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c
new file mode 100644
index 000000000000..4a9456544fd0
--- /dev/null
+++ b/drivers/irqchip/irq-pruss-intc.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PRU-ICSS INTC IRQChip driver for various TI SoCs
+ *
+ * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
+ *	Andrew F. Davis <afd@ti.com>
+ *	Suman Anna <s-anna@ti.com>
+ */
+
+#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+/*
+ * Number of host interrupts reaching the main MPU sub-system. Note that this
+ * is not the same as the total number of host interrupts supported by the PRUSS
+ * INTC instance
+ */
+#define MAX_NUM_HOST_IRQS	8
+
+/* minimum starting host interrupt number for MPU */
+#define MIN_PRU_HOST_INT	2
+
+/* maximum number of system events */
+#define MAX_PRU_SYS_EVENTS	64
+
+/* PRU_ICSS_INTC registers */
+#define PRU_INTC_REVID		0x0000
+#define PRU_INTC_CR		0x0004
+#define PRU_INTC_GER		0x0010
+#define PRU_INTC_GNLR		0x001c
+#define PRU_INTC_SISR		0x0020
+#define PRU_INTC_SICR		0x0024
+#define PRU_INTC_EISR		0x0028
+#define PRU_INTC_EICR		0x002c
+#define PRU_INTC_HIEISR		0x0034
+#define PRU_INTC_HIDISR		0x0038
+#define PRU_INTC_GPIR		0x0080
+#define PRU_INTC_SRSR0		0x0200
+#define PRU_INTC_SRSR1		0x0204
+#define PRU_INTC_SECR0		0x0280
+#define PRU_INTC_SECR1		0x0284
+#define PRU_INTC_ESR0		0x0300
+#define PRU_INTC_ESR1		0x0304
+#define PRU_INTC_ECR0		0x0380
+#define PRU_INTC_ECR1		0x0384
+#define PRU_INTC_CMR(x)		(0x0400 + (x) * 4)
+#define PRU_INTC_HMR(x)		(0x0800 + (x) * 4)
+#define PRU_INTC_HIPIR(x)	(0x0900 + (x) * 4)
+#define PRU_INTC_SIPR0		0x0d00
+#define PRU_INTC_SIPR1		0x0d04
+#define PRU_INTC_SITR0		0x0d80
+#define PRU_INTC_SITR1		0x0d84
+#define PRU_INTC_HINLR(x)	(0x1100 + (x) * 4)
+#define PRU_INTC_HIER		0x1500
+
+/* HIPIR register bit-fields */
+#define INTC_HIPIR_NONE_HINT	0x80000000
+
+/**
+ * struct pruss_intc - PRUSS interrupt controller structure
+ * @irqs: kernel irq numbers corresponding to PRUSS host interrupts
+ * @base: base virtual address of INTC register space
+ * @irqchip: irq chip for this interrupt controller
+ * @domain: irq domain for this interrupt controller
+ * @lock: mutex to serialize access to INTC
+ */
+struct pruss_intc {
+	unsigned int irqs[MAX_NUM_HOST_IRQS];
+	void __iomem *base;
+	struct irq_chip *irqchip;
+	struct irq_domain *domain;
+	struct mutex lock; /* PRUSS INTC lock */
+};
+
+static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned int reg)
+{
+	return readl_relaxed(intc->base + reg);
+}
+
+static inline void pruss_intc_write_reg(struct pruss_intc *intc,
+					unsigned int reg, u32 val)
+{
+	writel_relaxed(val, intc->base + reg);
+}
+
+static int pruss_intc_check_write(struct pruss_intc *intc, unsigned int reg,
+				  unsigned int sysevent)
+{
+	if (!intc)
+		return -EINVAL;
+
+	if (sysevent >= MAX_PRU_SYS_EVENTS)
+		return -EINVAL;
+
+	pruss_intc_write_reg(intc, reg, sysevent);
+
+	return 0;
+}
+
+static void pruss_intc_init(struct pruss_intc *intc)
+{
+	int i;
+
+	/* configure polarity to active high for all system interrupts */
+	pruss_intc_write_reg(intc, PRU_INTC_SIPR0, 0xffffffff);
+	pruss_intc_write_reg(intc, PRU_INTC_SIPR1, 0xffffffff);
+
+	/* configure type to pulse interrupt for all system interrupts */
+	pruss_intc_write_reg(intc, PRU_INTC_SITR0, 0);
+	pruss_intc_write_reg(intc, PRU_INTC_SITR1, 0);
+
+	/* clear all 16 interrupt channel map registers */
+	for (i = 0; i < 16; i++)
+		pruss_intc_write_reg(intc, PRU_INTC_CMR(i), 0);
+
+	/* clear all 3 host interrupt map registers */
+	for (i = 0; i < 3; i++)
+		pruss_intc_write_reg(intc, PRU_INTC_HMR(i), 0);
+}
+
+static void pruss_intc_irq_ack(struct irq_data *data)
+{
+	struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
+	unsigned int hwirq = data->hwirq;
+
+	pruss_intc_check_write(intc, PRU_INTC_SICR, hwirq);
+}
+
+static void pruss_intc_irq_mask(struct irq_data *data)
+{
+	struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
+	unsigned int hwirq = data->hwirq;
+
+	pruss_intc_check_write(intc, PRU_INTC_EICR, hwirq);
+}
+
+static void pruss_intc_irq_unmask(struct irq_data *data)
+{
+	struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
+	unsigned int hwirq = data->hwirq;
+
+	pruss_intc_check_write(intc, PRU_INTC_EISR, hwirq);
+}
+
+static int pruss_intc_irq_reqres(struct irq_data *data)
+{
+	if (!try_module_get(THIS_MODULE))
+		return -ENODEV;
+
+	return 0;
+}
+
+static void pruss_intc_irq_relres(struct irq_data *data)
+{
+	module_put(THIS_MODULE);
+}
+
+static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int virq,
+				     irq_hw_number_t hw)
+{
+	struct pruss_intc *intc = d->host_data;
+
+	irq_set_chip_data(virq, intc);
+	irq_set_chip_and_handler(virq, intc->irqchip, handle_level_irq);
+
+	return 0;
+}
+
+static void pruss_intc_irq_domain_unmap(struct irq_domain *d, unsigned int virq)
+{
+	irq_set_chip_and_handler(virq, NULL, NULL);
+	irq_set_chip_data(virq, NULL);
+}
+
+static const struct irq_domain_ops pruss_intc_irq_domain_ops = {
+	.xlate	= irq_domain_xlate_onecell,
+	.map	= pruss_intc_irq_domain_map,
+	.unmap	= pruss_intc_irq_domain_unmap,
+};
+
+static void pruss_intc_irq_handler(struct irq_desc *desc)
+{
+	unsigned int irq = irq_desc_get_irq(desc);
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	struct pruss_intc *intc = irq_get_handler_data(irq);
+	u32 hipir;
+	unsigned int virq;
+	int i, hwirq;
+
+	chained_irq_enter(chip, desc);
+
+	/* find our host irq number */
+	for (i = 0; i < MAX_NUM_HOST_IRQS; i++)
+		if (intc->irqs[i] == irq)
+			break;
+	if (i == MAX_NUM_HOST_IRQS)
+		goto err;
+
+	i += MIN_PRU_HOST_INT;
+
+	/* get highest priority pending PRUSS system event */
+	hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i));
+	while (!(hipir & INTC_HIPIR_NONE_HINT)) {
+		hwirq = hipir & GENMASK(9, 0);
+		virq = irq_linear_revmap(intc->domain, hwirq);
+
+		/*
+		 * NOTE: manually ACK any system events that do not have a
+		 * handler mapped yet
+		 */
+		if (unlikely(!virq))
+			pruss_intc_check_write(intc, PRU_INTC_SICR, hwirq);
+		else
+			generic_handle_irq(virq);
+
+		/* get next system event */
+		hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i));
+	}
+err:
+	chained_irq_exit(chip, desc);
+}
+
+static int pruss_intc_probe(struct platform_device *pdev)
+{
+	static const char * const irq_names[] = {
+		"host_intr0", "host_intr1", "host_intr2", "host_intr3",
+		"host_intr4", "host_intr5", "host_intr6", "host_intr7", };
+	struct device *dev = &pdev->dev;
+	struct pruss_intc *intc;
+	struct resource *res;
+	struct irq_chip *irqchip;
+	int i, irq;
+
+	intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL);
+	if (!intc)
+		return -ENOMEM;
+	platform_set_drvdata(pdev, intc);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	intc->base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(intc->base)) {
+		dev_err(dev, "failed to parse and map intc memory resource\n");
+		return PTR_ERR(intc->base);
+	}
+
+	dev_dbg(dev, "intc memory: pa %pa size 0x%zx va %pK\n", &res->start,
+		(size_t)resource_size(res), intc->base);
+
+	mutex_init(&intc->lock);
+
+	pruss_intc_init(intc);
+
+	irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL);
+	if (!irqchip)
+		return -ENOMEM;
+
+	irqchip->irq_ack = pruss_intc_irq_ack;
+	irqchip->irq_mask = pruss_intc_irq_mask;
+	irqchip->irq_unmask = pruss_intc_irq_unmask;
+	irqchip->irq_request_resources = pruss_intc_irq_reqres;
+	irqchip->irq_release_resources = pruss_intc_irq_relres;
+	irqchip->name = dev_name(dev);
+	intc->irqchip = irqchip;
+
+	/* always 64 events */
+	intc->domain = irq_domain_add_linear(dev->of_node, MAX_PRU_SYS_EVENTS,
+					     &pruss_intc_irq_domain_ops, intc);
+	if (!intc->domain)
+		return -ENOMEM;
+
+	for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
+		irq = platform_get_irq_byname(pdev, irq_names[i]);
+		if (irq < 0) {
+			dev_err(dev, "platform_get_irq_byname failed for %s : %d\n",
+				irq_names[i], irq);
+			goto fail_irq;
+		}
+
+		intc->irqs[i] = irq;
+		irq_set_handler_data(irq, intc);
+		irq_set_chained_handler(irq, pruss_intc_irq_handler);
+	}
+
+	return 0;
+
+fail_irq:
+	while (--i >= 0) {
+		if (intc->irqs[i])
+			irq_set_chained_handler_and_data(intc->irqs[i], NULL,
+							 NULL);
+	}
+	irq_domain_remove(intc->domain);
+	return irq;
+}
+
+static int pruss_intc_remove(struct platform_device *pdev)
+{
+	struct pruss_intc *intc = platform_get_drvdata(pdev);
+	unsigned int hwirq;
+	int i;
+
+	for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
+		if (intc->irqs[i])
+			irq_set_chained_handler_and_data(intc->irqs[i], NULL,
+							 NULL);
+	}
+
+	for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++)
+		irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq));
+	irq_domain_remove(intc->domain);
+
+	return 0;
+}
+
+static const struct of_device_id pruss_intc_of_match[] = {
+	{ .compatible = "ti,pruss-intc", },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, pruss_intc_of_match);
+
+static struct platform_driver pruss_intc_driver = {
+	.driver = {
+		.name = "pruss-intc",
+		.of_match_table = pruss_intc_of_match,
+	},
+	.probe  = pruss_intc_probe,
+	.remove = pruss_intc_remove,
+};
+module_platform_driver(pruss_intc_driver);
+
+MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
+MODULE_AUTHOR("Suman Anna <s-anna@ti.com>");
+MODULE_DESCRIPTION("TI PRU-ICSS INTC Driver");
+MODULE_LICENSE("GPL v2");
-- 
2.22.0

Re: [PATCH v2 2/6] irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS interrupts

[Marc Zyngier]

On 31/07/2019 23:41, Suman Anna wrote:
> From: "Andrew F. Davis" <afd@ti.com>
> 
> The Programmable Real-Time Unit Subsystem (PRUSS) contains a local
> interrupt controller (INTC) that can handle various system input events
> and post interrupts back to the device-level initiators. The INTC can
> support upto 64 input events with individual control configuration and
> hardware prioritization. These events are mapped onto 10 output interrupt
> lines through two levels of many-to-one mapping support. Different
> interrupt lines are routed to the individual PRU cores or to the host
> CPU, or to other devices on the SoC. Some of these events are sourced
> from peripherals or other sub-modules within that PRUSS, while a few
> others are sourced from SoC-level peripherals/devices.
> 
> The PRUSS INTC platform driver manages this PRUSS interrupt controller
> and implements an irqchip driver to provide a Linux standard way for
> the PRU client users to enable/disable/ack/re-trigger a PRUSS system
> event. The system events to interrupt channels and output interrupts
> relies on the mapping configuration provided either through the PRU
> firmware blob or via the PRU application's device tree node. The
> mappings will be programmed during the boot/shutdown of a PRU core.
> 
> The PRUSS INTC module is reference counted during the interrupt
> setup phase through the irqchip's irq_request_resources() and
> irq_release_resources() ops. This restricts the module from being
> removed as long as there are active interrupt users.
> 
> The driver currently supports and can be built for OMAP architecture
> based AM335x, AM437x and AM57xx SoCs; Keystone2 architecture based
> 66AK2G SoCs and Davinci architecture based OMAP-L13x/AM18x/DA850 SoCs.
> All of these SoCs support 64 system events, 10 interrupt channels and
> 10 output interrupt lines per PRUSS INTC with a few SoC integration
> differences.
> 
> NOTE:
> Each PRU-ICSS's INTC on AM57xx SoCs is preceded by a Crossbar that
> enables multiple external events to be routed to a specific number
> of input interrupt events. Any non-default external interrupt event
> directed towards PRUSS needs this crossbar to be setup properly.
> 
> Signed-off-by: Andrew F. Davis <afd@ti.com>
> Signed-off-by: Suman Anna <s-anna@ti.com>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
> v2: 
>  - Addressed all of David Lechner's comments
>  - Dropped irq_retrigger callback
>  - Updated interrupt names from "hostX" to "host_intrX"
>  - Moved host_mask variable to patch 4
> v1: https://patchwork.kernel.org/patch/11034545/
> v0: https://patchwork.kernel.org/patch/10795761/
> 
>  drivers/irqchip/Kconfig          |  10 +
>  drivers/irqchip/Makefile         |   1 +
>  drivers/irqchip/irq-pruss-intc.c | 338 +++++++++++++++++++++++++++++++
>  3 files changed, 349 insertions(+)
>  create mode 100644 drivers/irqchip/irq-pruss-intc.c
> 
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index 80e10f4e213a..dc6b5aa77a5d 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -471,6 +471,16 @@ config TI_SCI_INTA_IRQCHIP
>  	  If you wish to use interrupt aggregator irq resources managed by the
>  	  TI System Controller, say Y here. Otherwise, say N.
>  
> +config TI_PRUSS_INTC
> +	tristate "TI PRU-ICSS Interrupt Controller"
> +	depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM437X || SOC_DRA7XX || ARCH_KEYSTONE
> +	select IRQ_DOMAIN
> +	help
> +	   This enables support for the PRU-ICSS Local Interrupt Controller
> +	   present within a PRU-ICSS subsystem present on various TI SoCs.
> +	   The PRUSS INTC enables various interrupts to be routed to multiple
> +	   different processors within the SoC.
> +
>  endmenu
>  
>  config SIFIVE_PLIC
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index 8d0fcec6ab23..a02e652ca805 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -102,3 +102,4 @@ obj-$(CONFIG_MADERA_IRQ)		+= irq-madera.o
>  obj-$(CONFIG_LS1X_IRQ)			+= irq-ls1x.o
>  obj-$(CONFIG_TI_SCI_INTR_IRQCHIP)	+= irq-ti-sci-intr.o
>  obj-$(CONFIG_TI_SCI_INTA_IRQCHIP)	+= irq-ti-sci-inta.o
> +obj-$(CONFIG_TI_PRUSS_INTC)		+= irq-pruss-intc.o
> diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c
> new file mode 100644
> index 000000000000..4a9456544fd0
> --- /dev/null
> +++ b/drivers/irqchip/irq-pruss-intc.c
> @@ -0,0 +1,338 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * PRU-ICSS INTC IRQChip driver for various TI SoCs
> + *
> + * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
> + *	Andrew F. Davis <afd@ti.com>
> + *	Suman Anna <s-anna@ti.com>
> + */
> +
> +#include <linux/irq.h>
> +#include <linux/irqchip/chained_irq.h>
> +#include <linux/irqdomain.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +
> +/*
> + * Number of host interrupts reaching the main MPU sub-system. Note that this
> + * is not the same as the total number of host interrupts supported by the PRUSS
> + * INTC instance
> + */
> +#define MAX_NUM_HOST_IRQS	8
> +
> +/* minimum starting host interrupt number for MPU */
> +#define MIN_PRU_HOST_INT	2
> +
> +/* maximum number of system events */
> +#define MAX_PRU_SYS_EVENTS	64
> +
> +/* PRU_ICSS_INTC registers */
> +#define PRU_INTC_REVID		0x0000
> +#define PRU_INTC_CR		0x0004
> +#define PRU_INTC_GER		0x0010
> +#define PRU_INTC_GNLR		0x001c
> +#define PRU_INTC_SISR		0x0020
> +#define PRU_INTC_SICR		0x0024
> +#define PRU_INTC_EISR		0x0028
> +#define PRU_INTC_EICR		0x002c
> +#define PRU_INTC_HIEISR		0x0034
> +#define PRU_INTC_HIDISR		0x0038
> +#define PRU_INTC_GPIR		0x0080
> +#define PRU_INTC_SRSR0		0x0200
> +#define PRU_INTC_SRSR1		0x0204
> +#define PRU_INTC_SECR0		0x0280
> +#define PRU_INTC_SECR1		0x0284
> +#define PRU_INTC_ESR0		0x0300
> +#define PRU_INTC_ESR1		0x0304
> +#define PRU_INTC_ECR0		0x0380
> +#define PRU_INTC_ECR1		0x0384
> +#define PRU_INTC_CMR(x)		(0x0400 + (x) * 4)
> +#define PRU_INTC_HMR(x)		(0x0800 + (x) * 4)
> +#define PRU_INTC_HIPIR(x)	(0x0900 + (x) * 4)
> +#define PRU_INTC_SIPR0		0x0d00
> +#define PRU_INTC_SIPR1		0x0d04
> +#define PRU_INTC_SITR0		0x0d80
> +#define PRU_INTC_SITR1		0x0d84
> +#define PRU_INTC_HINLR(x)	(0x1100 + (x) * 4)
> +#define PRU_INTC_HIER		0x1500
> +
> +/* HIPIR register bit-fields */
> +#define INTC_HIPIR_NONE_HINT	0x80000000
> +
> +/**
> + * struct pruss_intc - PRUSS interrupt controller structure
> + * @irqs: kernel irq numbers corresponding to PRUSS host interrupts
> + * @base: base virtual address of INTC register space
> + * @irqchip: irq chip for this interrupt controller
> + * @domain: irq domain for this interrupt controller
> + * @lock: mutex to serialize access to INTC
> + */
> +struct pruss_intc {
> +	unsigned int irqs[MAX_NUM_HOST_IRQS];
> +	void __iomem *base;
> +	struct irq_chip *irqchip;
> +	struct irq_domain *domain;
> +	struct mutex lock; /* PRUSS INTC lock */

Nothing seem to use that lock in this patch (other than to initialize it).

> +};
> +
> +static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned int reg)
> +{
> +	return readl_relaxed(intc->base + reg);
> +}
> +
> +static inline void pruss_intc_write_reg(struct pruss_intc *intc,
> +					unsigned int reg, u32 val)
> +{
> +	writel_relaxed(val, intc->base + reg);
> +}
> +
> +static int pruss_intc_check_write(struct pruss_intc *intc, unsigned int reg,
> +				  unsigned int sysevent)
> +{
> +	if (!intc)
> +		return -EINVAL;
> +
> +	if (sysevent >= MAX_PRU_SYS_EVENTS)
> +		return -EINVAL;

How can any of these happen?  That'd be a bug in the driver surely.
Also, nothing ever checks the return value.

> +
> +	pruss_intc_write_reg(intc, reg, sysevent);
> +
> +	return 0;
> +}
> +
> +static void pruss_intc_init(struct pruss_intc *intc)
> +{
> +	int i;
> +
> +	/* configure polarity to active high for all system interrupts */
> +	pruss_intc_write_reg(intc, PRU_INTC_SIPR0, 0xffffffff);
> +	pruss_intc_write_reg(intc, PRU_INTC_SIPR1, 0xffffffff);
> +
> +	/* configure type to pulse interrupt for all system interrupts */
> +	pruss_intc_write_reg(intc, PRU_INTC_SITR0, 0);
> +	pruss_intc_write_reg(intc, PRU_INTC_SITR1, 0);
> +
> +	/* clear all 16 interrupt channel map registers */
> +	for (i = 0; i < 16; i++)
> +		pruss_intc_write_reg(intc, PRU_INTC_CMR(i), 0);
> +
> +	/* clear all 3 host interrupt map registers */
> +	for (i = 0; i < 3; i++)
> +		pruss_intc_write_reg(intc, PRU_INTC_HMR(i), 0);
> +}
> +
> +static void pruss_intc_irq_ack(struct irq_data *data)
> +{
> +	struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
> +	unsigned int hwirq = data->hwirq;
> +
> +	pruss_intc_check_write(intc, PRU_INTC_SICR, hwirq);
> +}
> +
> +static void pruss_intc_irq_mask(struct irq_data *data)
> +{
> +	struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
> +	unsigned int hwirq = data->hwirq;
> +
> +	pruss_intc_check_write(intc, PRU_INTC_EICR, hwirq);
> +}
> +
> +static void pruss_intc_irq_unmask(struct irq_data *data)
> +{
> +	struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
> +	unsigned int hwirq = data->hwirq;
> +
> +	pruss_intc_check_write(intc, PRU_INTC_EISR, hwirq);
> +}
> +
> +static int pruss_intc_irq_reqres(struct irq_data *data)
> +{
> +	if (!try_module_get(THIS_MODULE))
> +		return -ENODEV;
> +
> +	return 0;
> +}
> +
> +static void pruss_intc_irq_relres(struct irq_data *data)
> +{
> +	module_put(THIS_MODULE);
> +}
> +
> +static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int virq,
> +				     irq_hw_number_t hw)
> +{
> +	struct pruss_intc *intc = d->host_data;
> +
> +	irq_set_chip_data(virq, intc);
> +	irq_set_chip_and_handler(virq, intc->irqchip, handle_level_irq);
> +
> +	return 0;
> +}
> +
> +static void pruss_intc_irq_domain_unmap(struct irq_domain *d, unsigned int virq)
> +{
> +	irq_set_chip_and_handler(virq, NULL, NULL);
> +	irq_set_chip_data(virq, NULL);
> +}
> +
> +static const struct irq_domain_ops pruss_intc_irq_domain_ops = {
> +	.xlate	= irq_domain_xlate_onecell,
> +	.map	= pruss_intc_irq_domain_map,
> +	.unmap	= pruss_intc_irq_domain_unmap,
> +};
> +
> +static void pruss_intc_irq_handler(struct irq_desc *desc)
> +{
> +	unsigned int irq = irq_desc_get_irq(desc);
> +	struct irq_chip *chip = irq_desc_get_chip(desc);
> +	struct pruss_intc *intc = irq_get_handler_data(irq);
> +	u32 hipir;
> +	unsigned int virq;
> +	int i, hwirq;
> +
> +	chained_irq_enter(chip, desc);
> +
> +	/* find our host irq number */
> +	for (i = 0; i < MAX_NUM_HOST_IRQS; i++)
> +		if (intc->irqs[i] == irq)
> +			break;
> +	if (i == MAX_NUM_HOST_IRQS)
> +		goto err;
> +
> +	i += MIN_PRU_HOST_INT;
> +
> +	/* get highest priority pending PRUSS system event */
> +	hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i));
> +	while (!(hipir & INTC_HIPIR_NONE_HINT)) {
> +		hwirq = hipir & GENMASK(9, 0);
> +		virq = irq_linear_revmap(intc->domain, hwirq);
> +
> +		/*
> +		 * NOTE: manually ACK any system events that do not have a
> +		 * handler mapped yet
> +		 */
> +		if (unlikely(!virq))
> +			pruss_intc_check_write(intc, PRU_INTC_SICR, hwirq);

How were they configured the first place?

> +		else
> +			generic_handle_irq(virq);
> +
> +		/* get next system event */
> +		hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i));
> +	}
> +err:
> +	chained_irq_exit(chip, desc);
> +}
> +
> +static int pruss_intc_probe(struct platform_device *pdev)
> +{
> +	static const char * const irq_names[] = {

Should this be sized with MAX_NUM_HOST_IRQS, given that this is how you
parse it?

> +		"host_intr0", "host_intr1", "host_intr2", "host_intr3",
> +		"host_intr4", "host_intr5", "host_intr6", "host_intr7", };
> +	struct device *dev = &pdev->dev;
> +	struct pruss_intc *intc;
> +	struct resource *res;
> +	struct irq_chip *irqchip;
> +	int i, irq;
> +
> +	intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL);
> +	if (!intc)
> +		return -ENOMEM;
> +	platform_set_drvdata(pdev, intc);
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	intc->base = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(intc->base)) {
> +		dev_err(dev, "failed to parse and map intc memory resource\n");
> +		return PTR_ERR(intc->base);
> +	}
> +
> +	dev_dbg(dev, "intc memory: pa %pa size 0x%zx va %pK\n", &res->start,
> +		(size_t)resource_size(res), intc->base);
> +
> +	mutex_init(&intc->lock);
> +
> +	pruss_intc_init(intc);
> +
> +	irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL);
> +	if (!irqchip)
> +		return -ENOMEM;
> +
> +	irqchip->irq_ack = pruss_intc_irq_ack;
> +	irqchip->irq_mask = pruss_intc_irq_mask;
> +	irqchip->irq_unmask = pruss_intc_irq_unmask;
> +	irqchip->irq_request_resources = pruss_intc_irq_reqres;
> +	irqchip->irq_release_resources = pruss_intc_irq_relres;
> +	irqchip->name = dev_name(dev);
> +	intc->irqchip = irqchip;

Given that each and every pruss_intc ends up with a pointer to its own
irqchip, why is it a separate allocation instead of directly embedding
the structure?

Alternatively, have a single 'static const struct irq_chip' and lose the
slightly pointless dev_name as the irqchip name.

> +
> +	/* always 64 events */
> +	intc->domain = irq_domain_add_linear(dev->of_node, MAX_PRU_SYS_EVENTS,
> +					     &pruss_intc_irq_domain_ops, intc);
> +	if (!intc->domain)
> +		return -ENOMEM;
> +
> +	for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
> +		irq = platform_get_irq_byname(pdev, irq_names[i]);
> +		if (irq < 0) {

irq == 0 is also an error.

> +			dev_err(dev, "platform_get_irq_byname failed for %s : %d\n",
> +				irq_names[i], irq);
> +			goto fail_irq;
> +		}
> +
> +		intc->irqs[i] = irq;
> +		irq_set_handler_data(irq, intc);
> +		irq_set_chained_handler(irq, pruss_intc_irq_handler);
> +	}
> +
> +	return 0;
> +
> +fail_irq:
> +	while (--i >= 0) {
> +		if (intc->irqs[i])

This 'if' seems supperfluous.

> +			irq_set_chained_handler_and_data(intc->irqs[i], NULL,
> +							 NULL);
> +	}
> +	irq_domain_remove(intc->domain);
> +	return irq;
> +}
> +
> +static int pruss_intc_remove(struct platform_device *pdev)
> +{
> +	struct pruss_intc *intc = platform_get_drvdata(pdev);
> +	unsigned int hwirq;
> +	int i;
> +
> +	for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
> +		if (intc->irqs[i])

Same here.

> +			irq_set_chained_handler_and_data(intc->irqs[i], NULL,
> +							 NULL);
> +	}
> +
> +	for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++)
> +		irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq));
> +	irq_domain_remove(intc->domain);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id pruss_intc_of_match[] = {
> +	{ .compatible = "ti,pruss-intc", },
> +	{ /* sentinel */ },
> +};
> +MODULE_DEVICE_TABLE(of, pruss_intc_of_match);
> +
> +static struct platform_driver pruss_intc_driver = {
> +	.driver = {
> +		.name = "pruss-intc",
> +		.of_match_table = pruss_intc_of_match,
> +	},
> +	.probe  = pruss_intc_probe,
> +	.remove = pruss_intc_remove,
> +};
> +module_platform_driver(pruss_intc_driver);
> +
> +MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
> +MODULE_AUTHOR("Suman Anna <s-anna@ti.com>");
> +MODULE_DESCRIPTION("TI PRU-ICSS INTC Driver");
> +MODULE_LICENSE("GPL v2");
> 

Thanks,
	
	M.
-- 
Jazz is not dead, it just smells funny...

Re: [PATCH v2 2/6] irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS interrupts

[Suman Anna]

Hi Marc,

On 8/1/19 4:42 AM, Marc Zyngier wrote:
> On 31/07/2019 23:41, Suman Anna wrote:
>> From: "Andrew F. Davis" <afd@ti.com>
>>
>> The Programmable Real-Time Unit Subsystem (PRUSS) contains a local
>> interrupt controller (INTC) that can handle various system input events
>> and post interrupts back to the device-level initiators. The INTC can
>> support upto 64 input events with individual control configuration and
>> hardware prioritization. These events are mapped onto 10 output interrupt
>> lines through two levels of many-to-one mapping support. Different
>> interrupt lines are routed to the individual PRU cores or to the host
>> CPU, or to other devices on the SoC. Some of these events are sourced
>> from peripherals or other sub-modules within that PRUSS, while a few
>> others are sourced from SoC-level peripherals/devices.
>>
>> The PRUSS INTC platform driver manages this PRUSS interrupt controller
>> and implements an irqchip driver to provide a Linux standard way for
>> the PRU client users to enable/disable/ack/re-trigger a PRUSS system
>> event. The system events to interrupt channels and output interrupts
>> relies on the mapping configuration provided either through the PRU
>> firmware blob or via the PRU application's device tree node. The
>> mappings will be programmed during the boot/shutdown of a PRU core.
>>
>> The PRUSS INTC module is reference counted during the interrupt
>> setup phase through the irqchip's irq_request_resources() and
>> irq_release_resources() ops. This restricts the module from being
>> removed as long as there are active interrupt users.
>>
>> The driver currently supports and can be built for OMAP architecture
>> based AM335x, AM437x and AM57xx SoCs; Keystone2 architecture based
>> 66AK2G SoCs and Davinci architecture based OMAP-L13x/AM18x/DA850 SoCs.
>> All of these SoCs support 64 system events, 10 interrupt channels and
>> 10 output interrupt lines per PRUSS INTC with a few SoC integration
>> differences.
>>
>> NOTE:
>> Each PRU-ICSS's INTC on AM57xx SoCs is preceded by a Crossbar that
>> enables multiple external events to be routed to a specific number
>> of input interrupt events. Any non-default external interrupt event
>> directed towards PRUSS needs this crossbar to be setup properly.
>>
>> Signed-off-by: Andrew F. Davis <afd@ti.com>
>> Signed-off-by: Suman Anna <s-anna@ti.com>
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>> ---
>> v2: 
>>  - Addressed all of David Lechner's comments
>>  - Dropped irq_retrigger callback
>>  - Updated interrupt names from "hostX" to "host_intrX"
>>  - Moved host_mask variable to patch 4
>> v1: https://patchwork.kernel.org/patch/11034545/
>> v0: https://patchwork.kernel.org/patch/10795761/
>>
>>  drivers/irqchip/Kconfig          |  10 +
>>  drivers/irqchip/Makefile         |   1 +
>>  drivers/irqchip/irq-pruss-intc.c | 338 +++++++++++++++++++++++++++++++
>>  3 files changed, 349 insertions(+)
>>  create mode 100644 drivers/irqchip/irq-pruss-intc.c
>>
>> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
>> index 80e10f4e213a..dc6b5aa77a5d 100644
>> --- a/drivers/irqchip/Kconfig
>> +++ b/drivers/irqchip/Kconfig
>> @@ -471,6 +471,16 @@ config TI_SCI_INTA_IRQCHIP
>>  	  If you wish to use interrupt aggregator irq resources managed by the
>>  	  TI System Controller, say Y here. Otherwise, say N.
>>  
>> +config TI_PRUSS_INTC
>> +	tristate "TI PRU-ICSS Interrupt Controller"
>> +	depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM437X || SOC_DRA7XX || ARCH_KEYSTONE
>> +	select IRQ_DOMAIN
>> +	help
>> +	   This enables support for the PRU-ICSS Local Interrupt Controller
>> +	   present within a PRU-ICSS subsystem present on various TI SoCs.
>> +	   The PRUSS INTC enables various interrupts to be routed to multiple
>> +	   different processors within the SoC.
>> +
>>  endmenu
>>  
>>  config SIFIVE_PLIC
>> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
>> index 8d0fcec6ab23..a02e652ca805 100644
>> --- a/drivers/irqchip/Makefile
>> +++ b/drivers/irqchip/Makefile
>> @@ -102,3 +102,4 @@ obj-$(CONFIG_MADERA_IRQ)		+= irq-madera.o
>>  obj-$(CONFIG_LS1X_IRQ)			+= irq-ls1x.o
>>  obj-$(CONFIG_TI_SCI_INTR_IRQCHIP)	+= irq-ti-sci-intr.o
>>  obj-$(CONFIG_TI_SCI_INTA_IRQCHIP)	+= irq-ti-sci-inta.o
>> +obj-$(CONFIG_TI_PRUSS_INTC)		+= irq-pruss-intc.o
>> diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c
>> new file mode 100644
>> index 000000000000..4a9456544fd0
>> --- /dev/null
>> +++ b/drivers/irqchip/irq-pruss-intc.c
>> @@ -0,0 +1,338 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * PRU-ICSS INTC IRQChip driver for various TI SoCs
>> + *
>> + * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
>> + *	Andrew F. Davis <afd@ti.com>
>> + *	Suman Anna <s-anna@ti.com>
>> + */
>> +
>> +#include <linux/irq.h>
>> +#include <linux/irqchip/chained_irq.h>
>> +#include <linux/irqdomain.h>
>> +#include <linux/module.h>
>> +#include <linux/of_device.h>
>> +#include <linux/platform_device.h>
>> +
>> +/*
>> + * Number of host interrupts reaching the main MPU sub-system. Note that this
>> + * is not the same as the total number of host interrupts supported by the PRUSS
>> + * INTC instance
>> + */
>> +#define MAX_NUM_HOST_IRQS	8
>> +
>> +/* minimum starting host interrupt number for MPU */
>> +#define MIN_PRU_HOST_INT	2
>> +
>> +/* maximum number of system events */
>> +#define MAX_PRU_SYS_EVENTS	64
>> +
>> +/* PRU_ICSS_INTC registers */
>> +#define PRU_INTC_REVID		0x0000
>> +#define PRU_INTC_CR		0x0004
>> +#define PRU_INTC_GER		0x0010
>> +#define PRU_INTC_GNLR		0x001c
>> +#define PRU_INTC_SISR		0x0020
>> +#define PRU_INTC_SICR		0x0024
>> +#define PRU_INTC_EISR		0x0028
>> +#define PRU_INTC_EICR		0x002c
>> +#define PRU_INTC_HIEISR		0x0034
>> +#define PRU_INTC_HIDISR		0x0038
>> +#define PRU_INTC_GPIR		0x0080
>> +#define PRU_INTC_SRSR0		0x0200
>> +#define PRU_INTC_SRSR1		0x0204
>> +#define PRU_INTC_SECR0		0x0280
>> +#define PRU_INTC_SECR1		0x0284
>> +#define PRU_INTC_ESR0		0x0300
>> +#define PRU_INTC_ESR1		0x0304
>> +#define PRU_INTC_ECR0		0x0380
>> +#define PRU_INTC_ECR1		0x0384
>> +#define PRU_INTC_CMR(x)		(0x0400 + (x) * 4)
>> +#define PRU_INTC_HMR(x)		(0x0800 + (x) * 4)
>> +#define PRU_INTC_HIPIR(x)	(0x0900 + (x) * 4)
>> +#define PRU_INTC_SIPR0		0x0d00
>> +#define PRU_INTC_SIPR1		0x0d04
>> +#define PRU_INTC_SITR0		0x0d80
>> +#define PRU_INTC_SITR1		0x0d84
>> +#define PRU_INTC_HINLR(x)	(0x1100 + (x) * 4)
>> +#define PRU_INTC_HIER		0x1500
>> +
>> +/* HIPIR register bit-fields */
>> +#define INTC_HIPIR_NONE_HINT	0x80000000
>> +
>> +/**
>> + * struct pruss_intc - PRUSS interrupt controller structure
>> + * @irqs: kernel irq numbers corresponding to PRUSS host interrupts
>> + * @base: base virtual address of INTC register space
>> + * @irqchip: irq chip for this interrupt controller
>> + * @domain: irq domain for this interrupt controller
>> + * @lock: mutex to serialize access to INTC
>> + */
>> +struct pruss_intc {
>> +	unsigned int irqs[MAX_NUM_HOST_IRQS];
>> +	void __iomem *base;
>> +	struct irq_chip *irqchip;
>> +	struct irq_domain *domain;
>> +	struct mutex lock; /* PRUSS INTC lock */
> 
> Nothing seem to use that lock in this patch (other than to initialize it).

Correct, will move this to patch 4 where the actual usage is similar to
the host_mask move done in this version.

> 
>> +};
>> +
>> +static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned int reg)
>> +{
>> +	return readl_relaxed(intc->base + reg);
>> +}
>> +
>> +static inline void pruss_intc_write_reg(struct pruss_intc *intc,
>> +					unsigned int reg, u32 val)
>> +{
>> +	writel_relaxed(val, intc->base + reg);
>> +}
>> +
>> +static int pruss_intc_check_write(struct pruss_intc *intc, unsigned int reg,
>> +				  unsigned int sysevent)
>> +{
>> +	if (!intc)
>> +		return -EINVAL;
>> +
>> +	if (sysevent >= MAX_PRU_SYS_EVENTS)
>> +		return -EINVAL;
> 
> How can any of these happen?  That'd be a bug in the driver surely.
> Also, nothing ever checks the return value.

Yeah, I think I can drop this. The ack/mask/unmask callbacks are all
void returning functions, but we do return the value in
irq_set_irqchip_state() callback added in patch 5 (will reorder that
patch for the next version). This is similar to the check in
gic_irq_set_irqchip_state().

> 
>> +
>> +	pruss_intc_write_reg(intc, reg, sysevent);
>> +
>> +	return 0;
>> +}
>> +
>> +static void pruss_intc_init(struct pruss_intc *intc)
>> +{
>> +	int i;
>> +
>> +	/* configure polarity to active high for all system interrupts */
>> +	pruss_intc_write_reg(intc, PRU_INTC_SIPR0, 0xffffffff);
>> +	pruss_intc_write_reg(intc, PRU_INTC_SIPR1, 0xffffffff);
>> +
>> +	/* configure type to pulse interrupt for all system interrupts */
>> +	pruss_intc_write_reg(intc, PRU_INTC_SITR0, 0);
>> +	pruss_intc_write_reg(intc, PRU_INTC_SITR1, 0);
>> +
>> +	/* clear all 16 interrupt channel map registers */
>> +	for (i = 0; i < 16; i++)
>> +		pruss_intc_write_reg(intc, PRU_INTC_CMR(i), 0);
>> +
>> +	/* clear all 3 host interrupt map registers */
>> +	for (i = 0; i < 3; i++)
>> +		pruss_intc_write_reg(intc, PRU_INTC_HMR(i), 0);
>> +}
>> +
>> +static void pruss_intc_irq_ack(struct irq_data *data)
>> +{
>> +	struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
>> +	unsigned int hwirq = data->hwirq;
>> +
>> +	pruss_intc_check_write(intc, PRU_INTC_SICR, hwirq);
>> +}
>> +
>> +static void pruss_intc_irq_mask(struct irq_data *data)
>> +{
>> +	struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
>> +	unsigned int hwirq = data->hwirq;
>> +
>> +	pruss_intc_check_write(intc, PRU_INTC_EICR, hwirq);
>> +}
>> +
>> +static void pruss_intc_irq_unmask(struct irq_data *data)
>> +{
>> +	struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
>> +	unsigned int hwirq = data->hwirq;
>> +
>> +	pruss_intc_check_write(intc, PRU_INTC_EISR, hwirq);
>> +}
>> +
>> +static int pruss_intc_irq_reqres(struct irq_data *data)
>> +{
>> +	if (!try_module_get(THIS_MODULE))
>> +		return -ENODEV;
>> +
>> +	return 0;
>> +}
>> +
>> +static void pruss_intc_irq_relres(struct irq_data *data)
>> +{
>> +	module_put(THIS_MODULE);
>> +}
>> +
>> +static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int virq,
>> +				     irq_hw_number_t hw)
>> +{
>> +	struct pruss_intc *intc = d->host_data;
>> +
>> +	irq_set_chip_data(virq, intc);
>> +	irq_set_chip_and_handler(virq, intc->irqchip, handle_level_irq);
>> +
>> +	return 0;
>> +}
>> +
>> +static void pruss_intc_irq_domain_unmap(struct irq_domain *d, unsigned int virq)
>> +{
>> +	irq_set_chip_and_handler(virq, NULL, NULL);
>> +	irq_set_chip_data(virq, NULL);
>> +}
>> +
>> +static const struct irq_domain_ops pruss_intc_irq_domain_ops = {
>> +	.xlate	= irq_domain_xlate_onecell,
>> +	.map	= pruss_intc_irq_domain_map,
>> +	.unmap	= pruss_intc_irq_domain_unmap,
>> +};
>> +
>> +static void pruss_intc_irq_handler(struct irq_desc *desc)
>> +{
>> +	unsigned int irq = irq_desc_get_irq(desc);
>> +	struct irq_chip *chip = irq_desc_get_chip(desc);
>> +	struct pruss_intc *intc = irq_get_handler_data(irq);
>> +	u32 hipir;
>> +	unsigned int virq;
>> +	int i, hwirq;
>> +
>> +	chained_irq_enter(chip, desc);
>> +
>> +	/* find our host irq number */
>> +	for (i = 0; i < MAX_NUM_HOST_IRQS; i++)
>> +		if (intc->irqs[i] == irq)
>> +			break;
>> +	if (i == MAX_NUM_HOST_IRQS)
>> +		goto err;
>> +
>> +	i += MIN_PRU_HOST_INT;
>> +
>> +	/* get highest priority pending PRUSS system event */
>> +	hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i));
>> +	while (!(hipir & INTC_HIPIR_NONE_HINT)) {
>> +		hwirq = hipir & GENMASK(9, 0);
>> +		virq = irq_linear_revmap(intc->domain, hwirq);
>> +
>> +		/*
>> +		 * NOTE: manually ACK any system events that do not have a
>> +		 * handler mapped yet
>> +		 */
>> +		if (unlikely(!virq))
>> +			pruss_intc_check_write(intc, PRU_INTC_SICR, hwirq);
> 
> How were they configured the first place?

Ideally, this should not occur, I probably should add a WARN_ON here
catching any misuse. The PRUSS INTC is touched by multiple processors,
and each of them have to use some of the same registers to ack the
internal event. The current design is limited to only acking and
triggering the interrupts from PRU firmwares while the mappings are all
done by Linux. We are forced to do this to save some instruction space
in the tiny Instruction RAM that the PRUs (smallest is 4K and largest is
12K) have.

> 
>> +		else
>> +			generic_handle_irq(virq);
>> +
>> +		/* get next system event */
>> +		hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i));
>> +	}
>> +err:
>> +	chained_irq_exit(chip, desc);
>> +}
>> +
>> +static int pruss_intc_probe(struct platform_device *pdev)
>> +{
>> +	static const char * const irq_names[] = {
> 
> Should this be sized with MAX_NUM_HOST_IRQS, given that this is how you
> parse it?

Yes, will update in the next version.

> 
>> +		"host_intr0", "host_intr1", "host_intr2", "host_intr3",
>> +		"host_intr4", "host_intr5", "host_intr6", "host_intr7", };
>> +	struct device *dev = &pdev->dev;
>> +	struct pruss_intc *intc;
>> +	struct resource *res;
>> +	struct irq_chip *irqchip;
>> +	int i, irq;
>> +
>> +	intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL);
>> +	if (!intc)
>> +		return -ENOMEM;
>> +	platform_set_drvdata(pdev, intc);
>> +
>> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +	intc->base = devm_ioremap_resource(dev, res);
>> +	if (IS_ERR(intc->base)) {
>> +		dev_err(dev, "failed to parse and map intc memory resource\n");
>> +		return PTR_ERR(intc->base);
>> +	}
>> +
>> +	dev_dbg(dev, "intc memory: pa %pa size 0x%zx va %pK\n", &res->start,
>> +		(size_t)resource_size(res), intc->base);
>> +
>> +	mutex_init(&intc->lock);
>> +
>> +	pruss_intc_init(intc);
>> +
>> +	irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL);
>> +	if (!irqchip)
>> +		return -ENOMEM;
>> +
>> +	irqchip->irq_ack = pruss_intc_irq_ack;
>> +	irqchip->irq_mask = pruss_intc_irq_mask;
>> +	irqchip->irq_unmask = pruss_intc_irq_unmask;
>> +	irqchip->irq_request_resources = pruss_intc_irq_reqres;
>> +	irqchip->irq_release_resources = pruss_intc_irq_relres;
>> +	irqchip->name = dev_name(dev);
>> +	intc->irqchip = irqchip;
> 
> Given that each and every pruss_intc ends up with a pointer to its own
> irqchip, why is it a separate allocation instead of directly embedding
> the structure?
> 
> Alternatively, have a single 'static const struct irq_chip' and lose the
> slightly pointless dev_name as the irqchip name.

Agreed, this can be optimized.

> 
>> +
>> +	/* always 64 events */
>> +	intc->domain = irq_domain_add_linear(dev->of_node, MAX_PRU_SYS_EVENTS,
>> +					     &pruss_intc_irq_domain_ops, intc);
>> +	if (!intc->domain)
>> +		return -ENOMEM;
>> +
>> +	for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
>> +		irq = platform_get_irq_byname(pdev, irq_names[i]);
>> +		if (irq < 0) {
> 
> irq == 0 is also an error.

OK, will fix.

> 
>> +			dev_err(dev, "platform_get_irq_byname failed for %s : %d\n",
>> +				irq_names[i], irq);
>> +			goto fail_irq;
>> +		}
>> +
>> +		intc->irqs[i] = irq;
>> +		irq_set_handler_data(irq, intc);
>> +		irq_set_chained_handler(irq, pruss_intc_irq_handler);
>> +	}
>> +
>> +	return 0;
>> +
>> +fail_irq:
>> +	while (--i >= 0) {
>> +		if (intc->irqs[i])
> 
> This 'if' seems supperfluous.

So, some interrupts among the MAX_NUM_HOST_IRQS are not connected to the
Arm processor on some SoCs. I will move this check to the next patch
which introduces the skipping of interrupts.

> 
>> +			irq_set_chained_handler_and_data(intc->irqs[i], NULL,
>> +							 NULL);
>> +	}
>> +	irq_domain_remove(intc->domain);
>> +	return irq;
>> +}
>> +
>> +static int pruss_intc_remove(struct platform_device *pdev)
>> +{
>> +	struct pruss_intc *intc = platform_get_drvdata(pdev);
>> +	unsigned int hwirq;
>> +	int i;
>> +
>> +	for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
>> +		if (intc->irqs[i])
> 
> Same here.

Will move this as well.

> 
>> +			irq_set_chained_handler_and_data(intc->irqs[i], NULL,
>> +							 NULL);
>> +	}
>> +
>> +	for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++)
>> +		irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq));
>> +	irq_domain_remove(intc->domain);
>> +
>> +	return 0;
>> +}
>> +
>> +static const struct of_device_id pruss_intc_of_match[] = {
>> +	{ .compatible = "ti,pruss-intc", },
>> +	{ /* sentinel */ },
>> +};
>> +MODULE_DEVICE_TABLE(of, pruss_intc_of_match);
>> +
>> +static struct platform_driver pruss_intc_driver = {
>> +	.driver = {
>> +		.name = "pruss-intc",
>> +		.of_match_table = pruss_intc_of_match,
>> +	},
>> +	.probe  = pruss_intc_probe,
>> +	.remove = pruss_intc_remove,
>> +};
>> +module_platform_driver(pruss_intc_driver);
>> +
>> +MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
>> +MODULE_AUTHOR("Suman Anna <s-anna@ti.com>");
>> +MODULE_DESCRIPTION("TI PRU-ICSS INTC Driver");
>> +MODULE_LICENSE("GPL v2");
>>
> 
> Thanks,
> 	

Thank you for all the review comments.

regards
Suman

[PATCH v2 3/6] irqchip/irq-pruss-intc: Add support for shared and invalid interrupts

[Suman Anna]

The PRUSS INTC has a fixed number of output interrupt lines that are
connected to a number of processors or other PRUSS instances or other
devices (like DMA) on the SoC. The output interrupt lines 2 through 9
are usually connected to the main Arm host processor and are referred
to as host interrupts 0 through 7 from ARM/MPU perspective.

All of these 8 host interrupts are not always exclusively connected
to the Arm interrupt controller. Some SoCs have some interrupt lines
not connected to the Arm interrupt controller at all, while a few others
have the interrupt lines connected to multiple processors in which they
need to be partitioned as per SoC integration needs. For example, AM437x
and 66AK2G SoCs have 2 PRUSS instances each and have the host interrupt 5
connected to the other PRUSS, while AM335x has host interrupt 0 shared
between MPU and TSC_ADC and host interrupts 6 & 7 shared between MPU and
a DMA controller.

Add support to the PRUSS INTC driver to allow both these shared and
invalid interrupts by not returning a failure if any of these interrupts
are skipped from the corresponding INTC DT node.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2:
 - Fixed a typo in error message trace for ti,irqs-shared
 - Updated patch description to use generic "interrupt controller" instead
   of GIC
 - Revised the kerneldoc comment for invalid_intr
v1: https://patchwork.kernel.org/patch/11034559/

 drivers/irqchip/irq-pruss-intc.c | 44 +++++++++++++++++++++++++++++++-
 1 file changed, 43 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c
index 4a9456544fd0..3a1b8a93cfad 100644
--- a/drivers/irqchip/irq-pruss-intc.c
+++ b/drivers/irqchip/irq-pruss-intc.c
@@ -67,6 +67,8 @@
  * @irqchip: irq chip for this interrupt controller
  * @domain: irq domain for this interrupt controller
  * @lock: mutex to serialize access to INTC
+ * @shared_intr: bit-map denoting if the MPU host interrupt is shared
+ * @invalid_intr: bit-map denoting if host interrupt is not connected to MPU
  */
 struct pruss_intc {
 	unsigned int irqs[MAX_NUM_HOST_IRQS];
@@ -74,6 +76,8 @@ struct pruss_intc {
 	struct irq_chip *irqchip;
 	struct irq_domain *domain;
 	struct mutex lock; /* PRUSS INTC lock */
+	u16 shared_intr;
+	u16 invalid_intr;
 };
 
 static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned int reg)
@@ -233,7 +237,8 @@ static int pruss_intc_probe(struct platform_device *pdev)
 	struct pruss_intc *intc;
 	struct resource *res;
 	struct irq_chip *irqchip;
-	int i, irq;
+	int i, irq, count;
+	u8 temp_intr[MAX_NUM_HOST_IRQS] = { 0 };
 
 	intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL);
 	if (!intc)
@@ -250,6 +255,39 @@ static int pruss_intc_probe(struct platform_device *pdev)
 	dev_dbg(dev, "intc memory: pa %pa size 0x%zx va %pK\n", &res->start,
 		(size_t)resource_size(res), intc->base);
 
+	count = of_property_read_variable_u8_array(dev->of_node,
+						   "ti,irqs-reserved",
+						   temp_intr, 0,
+						   MAX_NUM_HOST_IRQS);
+	if (count < 0 && count != -EINVAL)
+		return count;
+	count = (count == -EINVAL ? 0 : count);
+	for (i = 0; i < count; i++) {
+		if (temp_intr[i] < MAX_NUM_HOST_IRQS) {
+			intc->invalid_intr |= BIT(temp_intr[i]);
+		} else {
+			dev_warn(dev, "ignoring invalid reserved irq %d\n",
+				 temp_intr[i]);
+		}
+		temp_intr[i] = 0;
+	}
+
+	count = of_property_read_variable_u8_array(dev->of_node,
+						   "ti,irqs-shared",
+						   temp_intr, 0,
+						   MAX_NUM_HOST_IRQS);
+	if (count < 0 && count != -EINVAL)
+		return count;
+	count = (count == -EINVAL ? 0 : count);
+	for (i = 0; i < count; i++) {
+		if (temp_intr[i] < MAX_NUM_HOST_IRQS) {
+			intc->shared_intr |= BIT(temp_intr[i]);
+		} else {
+			dev_warn(dev, "ignoring invalid shared irq %d\n",
+				 temp_intr[i]);
+		}
+	}
+
 	mutex_init(&intc->lock);
 
 	pruss_intc_init(intc);
@@ -275,6 +313,10 @@ static int pruss_intc_probe(struct platform_device *pdev)
 	for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
 		irq = platform_get_irq_byname(pdev, irq_names[i]);
 		if (irq < 0) {
+			if (intc->shared_intr & BIT(i) ||
+			    intc->invalid_intr & BIT(i))
+				continue;
+
 			dev_err(dev, "platform_get_irq_byname failed for %s : %d\n",
 				irq_names[i], irq);
 			goto fail_irq;
-- 
2.22.0

[PATCH v2 4/6] irqchip/irq-pruss-intc: Add helper functions to configure internal mapping

[Suman Anna]

The PRUSS INTC receives a number of system input interrupt source events
and supports individual control configuration and hardware prioritization.
These input events can be mapped to some output interrupt lines through 2
levels of many-to-one mapping i.e. events to channel mapping and channels
to output interrupts.

This mapping information is provided through the PRU firmware that is
loaded onto a PRU core/s or through the device tree node of the PRU
application. The mapping is configured by the PRU remoteproc driver, and
is setup before the PRU core is started and cleaned up after the PRU core
is stopped. This event mapping configuration logic programs the Channel
Map Registers (CMRx) and Host-Interrupt Map Registers (HMRx) only when a
new program is being loaded/started and the same events and interrupt
channels are reset to zero when stopping a PRU.

Add two helper functions: pruss_intc_configure() & pruss_intc_unconfigure()
that the PRU remoteproc driver can use to configure the PRUSS INTC.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
v2:
 - Added new internal helper functions pruss_intc_update_cmr/hmr for
   programming CMR and HMR registers
 - Added unroll logic on failures in pruss_intc_configure() using the
   refactored functions
 - Updated unconfigure logic to reset the map registers and updated
   patch description accordingly
 - Renamed the FREE macro to PRU_INTC_FREE and moved it to header file 
v1: https://patchwork.kernel.org/patch/11034563/

 drivers/irqchip/irq-pruss-intc.c       | 286 ++++++++++++++++++++++++-
 include/linux/irqchip/irq-pruss-intc.h |  36 ++++
 2 files changed, 320 insertions(+), 2 deletions(-)
 create mode 100644 include/linux/irqchip/irq-pruss-intc.h

diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c
index 3a1b8a93cfad..63cfc665be1e 100644
--- a/drivers/irqchip/irq-pruss-intc.c
+++ b/drivers/irqchip/irq-pruss-intc.c
@@ -9,6 +9,7 @@
 
 #include <linux/irq.h>
 #include <linux/irqchip/chained_irq.h>
+#include <linux/irqchip/irq-pruss-intc.h>
 #include <linux/irqdomain.h>
 #include <linux/module.h>
 #include <linux/of_device.h>
@@ -24,8 +25,8 @@
 /* minimum starting host interrupt number for MPU */
 #define MIN_PRU_HOST_INT	2
 
-/* maximum number of system events */
-#define MAX_PRU_SYS_EVENTS	64
+/* maximum number of host interrupts */
+#define MAX_PRU_HOST_INT	10
 
 /* PRU_ICSS_INTC registers */
 #define PRU_INTC_REVID		0x0000
@@ -57,6 +58,16 @@
 #define PRU_INTC_HINLR(x)	(0x1100 + (x) * 4)
 #define PRU_INTC_HIER		0x1500
 
+/* CMR register bit-field macros */
+#define CMR_EVT_MAP_MASK	0xf
+#define CMR_EVT_MAP_BITS	8
+#define CMR_EVT_PER_REG		4
+
+/* HMR register bit-field macros */
+#define HMR_CH_MAP_MASK		0xf
+#define HMR_CH_MAP_BITS		8
+#define HMR_CH_PER_REG		4
+
 /* HIPIR register bit-fields */
 #define INTC_HIPIR_NONE_HINT	0x80000000
 
@@ -66,7 +77,9 @@
  * @base: base virtual address of INTC register space
  * @irqchip: irq chip for this interrupt controller
  * @domain: irq domain for this interrupt controller
+ * @config_map: stored INTC configuration mapping data
  * @lock: mutex to serialize access to INTC
+ * @host_mask: indicate which HOST IRQs are enabled
  * @shared_intr: bit-map denoting if the MPU host interrupt is shared
  * @invalid_intr: bit-map denoting if host interrupt is not connected to MPU
  */
@@ -75,7 +88,9 @@ struct pruss_intc {
 	void __iomem *base;
 	struct irq_chip *irqchip;
 	struct irq_domain *domain;
+	struct pruss_intc_config config_map;
 	struct mutex lock; /* PRUSS INTC lock */
+	u32 host_mask;
 	u16 shared_intr;
 	u16 invalid_intr;
 };
@@ -105,6 +120,267 @@ static int pruss_intc_check_write(struct pruss_intc *intc, unsigned int reg,
 	return 0;
 }
 
+static void pruss_intc_update_cmr(struct pruss_intc *intc, int evt, s8 ch)
+{
+	u32 idx, val;
+
+	idx = evt / CMR_EVT_PER_REG;
+	val = pruss_intc_read_reg(intc, PRU_INTC_CMR(idx));
+	val &= ~(CMR_EVT_MAP_MASK <<
+		 ((evt % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS));
+	val |= ch << ((evt % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS);
+	pruss_intc_write_reg(intc, PRU_INTC_CMR(idx), val);
+}
+
+static void pruss_intc_update_hmr(struct pruss_intc *intc, int ch, s8 host)
+{
+	u32 idx, val;
+
+	idx = ch / HMR_CH_PER_REG;
+	val = pruss_intc_read_reg(intc, PRU_INTC_HMR(idx));
+	val &= ~(HMR_CH_MAP_MASK <<
+		 ((ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS));
+	val |= host << ((ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS);
+	pruss_intc_write_reg(intc, PRU_INTC_HMR(idx), val);
+}
+
+static struct pruss_intc *to_pruss_intc(struct device *pru_dev)
+{
+	struct device_node *np;
+	struct platform_device *pdev;
+	struct device *pruss_dev = pru_dev->parent;
+	struct pruss_intc *intc = ERR_PTR(-ENODEV);
+
+	np = of_get_child_by_name(pruss_dev->of_node, "interrupt-controller");
+	if (!np) {
+		dev_err(pruss_dev, "pruss does not have an interrupt-controller node\n");
+		return intc;
+	}
+
+	pdev = of_find_device_by_node(np);
+	if (!pdev) {
+		dev_err(pruss_dev, "no associated platform device\n");
+		goto out;
+	}
+
+	intc = platform_get_drvdata(pdev);
+	if (!intc) {
+		dev_err(pruss_dev, "pruss intc device probe failed?\n");
+		intc = ERR_PTR(-EINVAL);
+	}
+
+out:
+	of_node_put(np);
+	return intc;
+}
+
+/**
+ * pruss_intc_configure() - configure the PRUSS INTC
+ * @dev: pru device pointer
+ * @intc_config: PRU core-specific INTC configuration
+ *
+ * Configures the PRUSS INTC with the provided configuration from
+ * a PRU core. Any existing event to channel mappings or channel to
+ * host interrupt mappings are checked to make sure there are no
+ * conflicting configuration between both the PRU cores. The function
+ * is intended to be used only by the PRU remoteproc driver.
+ *
+ * Returns 0 on success, or a suitable error code otherwise
+ */
+int pruss_intc_configure(struct device *dev,
+			 struct pruss_intc_config *intc_config)
+{
+	struct pruss_intc *intc;
+	int i, idx, ret;
+	s8 ch, host;
+	u64 sysevt_mask = 0;
+	u32 ch_mask = 0;
+	u32 host_mask = 0;
+
+	intc = to_pruss_intc(dev);
+	if (IS_ERR(intc))
+		return PTR_ERR(intc);
+
+	mutex_lock(&intc->lock);
+
+	/*
+	 * configure channel map registers - each register holds map info
+	 * for 4 events, with each event occupying the lower nibble in
+	 * a register byte address in little-endian fashion
+	 */
+	for (i = 0; i < ARRAY_SIZE(intc_config->sysev_to_ch); i++) {
+		ch = intc_config->sysev_to_ch[i];
+		if (ch < 0)
+			continue;
+
+		/* check if sysevent already assigned */
+		if (intc->config_map.sysev_to_ch[i] != PRU_INTC_FREE) {
+			dev_err(dev, "event %d (req. channel %d) already assigned to channel %d\n",
+				i, ch, intc->config_map.sysev_to_ch[i]);
+			ret = -EEXIST;
+			goto fail_evt;
+		}
+
+		intc->config_map.sysev_to_ch[i] = ch;
+		pruss_intc_update_cmr(intc, i, ch);
+		sysevt_mask |= BIT_ULL(i);
+		ch_mask |= BIT(ch);
+		idx = i / CMR_EVT_PER_REG;
+
+		dev_dbg(dev, "SYSEVT%d -> CH%d (CMR%d 0x%08x)\n", i, ch, idx,
+			pruss_intc_read_reg(intc, PRU_INTC_CMR(idx)));
+	}
+
+	/*
+	 * set host map registers - each register holds map info for
+	 * 4 channels, with each channel occupying the lower nibble in
+	 * a register byte address in little-endian fashion
+	 */
+	for (i = 0; i < ARRAY_SIZE(intc_config->ch_to_host); i++) {
+		host = intc_config->ch_to_host[i];
+		if (host < 0)
+			continue;
+
+		/* check if channel already assigned */
+		if (intc->config_map.ch_to_host[i] != PRU_INTC_FREE) {
+			dev_err(dev, "channel %d (req. intr_no %d) already assigned to intr_no %d\n",
+				i, host, intc->config_map.ch_to_host[i]);
+			ret = -EEXIST;
+			goto fail_ch;
+		}
+
+		/* check if host intr is already in use by other PRU */
+		if (intc->host_mask & (1U << host)) {
+			dev_err(dev, "%s: host intr %d already in use\n",
+				__func__, host);
+			ret = -EEXIST;
+			goto fail_ch;
+		}
+
+		intc->config_map.ch_to_host[i] = host;
+		pruss_intc_update_hmr(intc, i, host);
+		ch_mask |= BIT(i);
+		host_mask |= BIT(host);
+		idx = i / HMR_CH_PER_REG;
+
+		dev_dbg(dev, "CH%d -> HOST%d (HMR%d 0x%08x)\n", i, host, idx,
+			pruss_intc_read_reg(intc, PRU_INTC_HMR(idx)));
+	}
+
+	dev_info(dev, "configured system_events = 0x%016llx intr_channels = 0x%08x host_intr = 0x%08x\n",
+		 sysevt_mask, ch_mask, host_mask);
+
+	/* enable system events, writing 0 has no-effect */
+	pruss_intc_write_reg(intc, PRU_INTC_ESR0, lower_32_bits(sysevt_mask));
+	pruss_intc_write_reg(intc, PRU_INTC_SECR0, lower_32_bits(sysevt_mask));
+	pruss_intc_write_reg(intc, PRU_INTC_ESR1, upper_32_bits(sysevt_mask));
+	pruss_intc_write_reg(intc, PRU_INTC_SECR1, upper_32_bits(sysevt_mask));
+
+	/* enable host interrupts */
+	for (i = 0; i < MAX_PRU_HOST_INT; i++) {
+		if (host_mask & BIT(i))
+			pruss_intc_write_reg(intc, PRU_INTC_HIEISR, i);
+	}
+
+	/* global interrupt enable */
+	pruss_intc_write_reg(intc, PRU_INTC_GER, 1);
+
+	intc->host_mask |= host_mask;
+
+	mutex_unlock(&intc->lock);
+	return 0;
+
+fail_ch:
+	while (--i >= 0) {
+		if (intc_config->ch_to_host[i] >= 0) {
+			intc->config_map.ch_to_host[i] = PRU_INTC_FREE;
+			pruss_intc_update_hmr(intc, i, 0);
+		}
+	}
+	i = ARRAY_SIZE(intc_config->sysev_to_ch);
+fail_evt:
+	while (--i >= 0) {
+		if (intc_config->sysev_to_ch[i] >= 0) {
+			intc->config_map.sysev_to_ch[i] = PRU_INTC_FREE;
+			pruss_intc_update_cmr(intc, i, 0);
+		}
+	}
+	mutex_unlock(&intc->lock);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(pruss_intc_configure);
+
+/**
+ * pruss_intc_unconfigure() - unconfigure the PRUSS INTC
+ * @dev: pru device pointer
+ * @intc_config: PRU core specific INTC configuration
+ *
+ * Undo whatever was done in pruss_intc_configure() for a PRU core.
+ * It should be sufficient to just mark the resources free in the
+ * global map and disable the host interrupts and sysevents.
+ */
+int pruss_intc_unconfigure(struct device *dev,
+			   struct pruss_intc_config *intc_config)
+{
+	struct pruss_intc *intc;
+	int i;
+	s8 ch, host;
+	u64 sysevt_mask = 0;
+	u32 host_mask = 0;
+
+	intc = to_pruss_intc(dev);
+	if (IS_ERR(intc))
+		return PTR_ERR(intc);
+
+	mutex_lock(&intc->lock);
+
+	for (i = 0; i < ARRAY_SIZE(intc_config->sysev_to_ch); i++) {
+		ch = intc_config->sysev_to_ch[i];
+		if (ch < 0)
+			continue;
+
+		/* mark sysevent free in global map */
+		intc->config_map.sysev_to_ch[i] = PRU_INTC_FREE;
+		sysevt_mask |= BIT_ULL(i);
+		/* clear the map using reset value 0 */
+		pruss_intc_update_cmr(intc, i, 0);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(intc_config->ch_to_host); i++) {
+		host = intc_config->ch_to_host[i];
+		if (host < 0)
+			continue;
+
+		/* mark channel free in global map */
+		intc->config_map.ch_to_host[i] = PRU_INTC_FREE;
+		host_mask |= BIT(host);
+		/* clear the map using reset value 0 */
+		pruss_intc_update_hmr(intc, i, 0);
+	}
+
+	dev_info(dev, "unconfigured system_events = 0x%016llx host_intr = 0x%08x\n",
+		 sysevt_mask, host_mask);
+
+	/* disable system events, writing 0 has no-effect */
+	pruss_intc_write_reg(intc, PRU_INTC_ECR0, lower_32_bits(sysevt_mask));
+	pruss_intc_write_reg(intc, PRU_INTC_ECR1, upper_32_bits(sysevt_mask));
+	/* clear any pending status */
+	pruss_intc_write_reg(intc, PRU_INTC_SECR0, lower_32_bits(sysevt_mask));
+	pruss_intc_write_reg(intc, PRU_INTC_SECR1, upper_32_bits(sysevt_mask));
+
+	/* disable host interrupts */
+	for (i = 0; i < MAX_PRU_HOST_INT; i++) {
+		if (host_mask & BIT(i))
+			pruss_intc_write_reg(intc, PRU_INTC_HIDISR, i);
+	}
+
+	intc->host_mask &= ~host_mask;
+	mutex_unlock(&intc->lock);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(pruss_intc_unconfigure);
+
 static void pruss_intc_init(struct pruss_intc *intc)
 {
 	int i;
@@ -290,6 +566,12 @@ static int pruss_intc_probe(struct platform_device *pdev)
 
 	mutex_init(&intc->lock);
 
+	for (i = 0; i < ARRAY_SIZE(intc->config_map.sysev_to_ch); i++)
+		intc->config_map.sysev_to_ch[i] = PRU_INTC_FREE;
+
+	for (i = 0; i < ARRAY_SIZE(intc->config_map.ch_to_host); i++)
+		intc->config_map.ch_to_host[i] = PRU_INTC_FREE;
+
 	pruss_intc_init(intc);
 
 	irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL);
diff --git a/include/linux/irqchip/irq-pruss-intc.h b/include/linux/irqchip/irq-pruss-intc.h
new file mode 100644
index 000000000000..daffc048b303
--- /dev/null
+++ b/include/linux/irqchip/irq-pruss-intc.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * PRU-ICSS sub-system private interfaces
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ *	Suman Anna <s-anna@ti.com>
+ */
+
+#ifndef __LINUX_IRQ_PRUSS_INTC_H
+#define __LINUX_IRQ_PRUSS_INTC_H
+
+/* maximum number of system events */
+#define MAX_PRU_SYS_EVENTS	64
+
+/* maximum number of interrupt channels */
+#define MAX_PRU_CHANNELS	10
+
+/* use -1 to mark unassigned events and channels */
+#define PRU_INTC_FREE		-1
+
+/**
+ * struct pruss_intc_config - INTC configuration info
+ * @sysev_to_ch: system events to channel mapping information
+ * @ch_to_host: interrupt channel to host interrupt information
+ */
+struct pruss_intc_config {
+	s8 sysev_to_ch[MAX_PRU_SYS_EVENTS];
+	s8 ch_to_host[MAX_PRU_CHANNELS];
+};
+
+int pruss_intc_configure(struct device *dev,
+			 struct pruss_intc_config *intc_config);
+int pruss_intc_unconfigure(struct device *dev,
+			   struct pruss_intc_config *intc_config);
+
+#endif	/* __LINUX_IRQ_PRUSS_INTC_H */
-- 
2.22.0

Re: [PATCH v2 4/6] irqchip/irq-pruss-intc: Add helper functions to configure internal mapping

[Marc Zyngier]

On 31/07/2019 23:41, Suman Anna wrote:
> The PRUSS INTC receives a number of system input interrupt source events
> and supports individual control configuration and hardware prioritization.
> These input events can be mapped to some output interrupt lines through 2
> levels of many-to-one mapping i.e. events to channel mapping and channels
> to output interrupts.
> 
> This mapping information is provided through the PRU firmware that is
> loaded onto a PRU core/s or through the device tree node of the PRU
> application. The mapping is configured by the PRU remoteproc driver, and
> is setup before the PRU core is started and cleaned up after the PRU core
> is stopped. This event mapping configuration logic programs the Channel
> Map Registers (CMRx) and Host-Interrupt Map Registers (HMRx) only when a
> new program is being loaded/started and the same events and interrupt
> channels are reset to zero when stopping a PRU.
> 
> Add two helper functions: pruss_intc_configure() & pruss_intc_unconfigure()
> that the PRU remoteproc driver can use to configure the PRUSS INTC.

So let me see if I correctly understand this: this adds yet another
firmware description parser, with a private interface to another
(undisclosed?) driver, bypassing the standard irqchip configuration
mechanism. It sounds great, doesn't it?

What I cannot really infer from this message (-ETOOMUCHJARGON) is what
interrupts this affects:

- Interrupts from random devices to the PRUSS?
- Interrupts from the PRUSS to the host?
- Something else?

When does this happen? Under control of what? It isn't even clear why
this is part of this irqchip driver.

Depending what this does, there may be ways to fit it into the standard
interrupt configuration framework. After all, we already have standard
interfaces to route interrupts to virtual CPUs, effectively passing full
control of an interrupt to another entity. If you squint hard enough,
your PRUSS can fit that description.

If that doesn't work, then we need to make the IRQ framework grok that
kind of requirement (hence my request for clarification). But I'm
strongly opposed to inventing a SoC-private way of configuring
interrupts behind the kernel's back.

Thanks,

	M.
-- 
Jazz is not dead, it just smells funny...

Re: [PATCH v2 4/6] irqchip/irq-pruss-intc: Add helper functions to configure internal mapping

[Suman Anna]

Hi Marc,

On 8/1/19 3:45 AM, Marc Zyngier wrote:
> On 31/07/2019 23:41, Suman Anna wrote:
>> The PRUSS INTC receives a number of system input interrupt source events
>> and supports individual control configuration and hardware prioritization.
>> These input events can be mapped to some output interrupt lines through 2
>> levels of many-to-one mapping i.e. events to channel mapping and channels
>> to output interrupts.
>>
>> This mapping information is provided through the PRU firmware that is
>> loaded onto a PRU core/s or through the device tree node of the PRU
>> application. The mapping is configured by the PRU remoteproc driver, and
>> is setup before the PRU core is started and cleaned up after the PRU core
>> is stopped. This event mapping configuration logic programs the Channel
>> Map Registers (CMRx) and Host-Interrupt Map Registers (HMRx) only when a
>> new program is being loaded/started and the same events and interrupt
>> channels are reset to zero when stopping a PRU.
>>
>> Add two helper functions: pruss_intc_configure() & pruss_intc_unconfigure()
>> that the PRU remoteproc driver can use to configure the PRUSS INTC.
> 
> So let me see if I correctly understand this: this adds yet another
> firmware description parser, with a private interface to another
> (undisclosed?) driver, bypassing the standard irqchip configuration
> mechanism. It sounds great, doesn't it?
> 
> What I cannot really infer from this message (-ETOOMUCHJARGON) is what
> interrupts this affects:
> 
> - Interrupts from random devices to the PRUSS?
> - Interrupts from the PRUSS to the host?
> - Something else?

The interrupt sources (called system events) can be from internal PRUSS
peripherals, SoC-level peripherals or just software triggering (limited
to some events).

So, the PRUSS INTC behaves as a funnel and is both an interrupt router
and multiplexer. The INTC itself is part of the PRUSS, and all PRU
application related interrupts/events that need to trigger an interrupt
to either the PRU cores or other host processors (like DSP, ARM) have to
go through this INTC, and routed out to a limited number of output
interrupts that are then connected to different processors.

The split of interrupt handling between a PRU and its peer host
processor will be a application design choice (We can implement soft IPs
like UARTs, ADCs, I2Cs etc using PRUs). Some of the input events
themselves are multiplexed and controlled by a single MMR (outside of
INTC) that feeds different sets of events into the INTC. The MMR
configuration is outside of scope of this driver and will depend on the
application/client driver being run.

> 
> When does this happen? Under control of what? It isn't even clear why
> this is part of this irqchip driver.

The mapping configuration is per PRU application and firmware, and is
done in line with acquiring and release a PRU which is treated as an
exclusive resource. We establish the mapping for all events through this
driver including the events that are to be routed to PRUs. This is done
to save the tiny/limited Instruction RAM space that PRUs have.

We have designed this as an irqchip driver (instead of some custom SoC
driver exporting custom functions) to use standard Linux semantics/irq
API and better integrate with Linux DT, but we need some semantics for
establishing the routing at runtime depending on the PRU client driver
we are running. The exported functions will be called only by the PRU
remoteproc driver during a pru_rproc_get()/pru_rproc_put(), and are
transparent to PRU client drivers.

Please also see the discussion from v1 [1] on why we can't use an
extended number of interrupt-cells infrastructure for achieving this.

[1] https://patchwork.kernel.org/patch/11034563/


> Depending what this does, there may be ways to fit it into the standard
> interrupt configuration framework. After all, we already have standard
> interfaces to route interrupts to virtual CPUs, effectively passing full
> control of an interrupt to another entity. If you squint hard enough,
> your PRUSS can fit that description.

Yeah, I am open to suggestions if there is a better way of doing this.

regards
Suman

> 
> If that doesn't work, then we need to make the IRQ framework grok that
> kind of requirement (hence my request for clarification). But I'm
> strongly opposed to inventing a SoC-private way of configuring
> interrupts behind the kernel's back.
> 
> Thanks,
> 
> 	M.
> 

Re: [PATCH v2 4/6] irqchip/irq-pruss-intc: Add helper functions to configure internal mapping

[David Lechner]

On 8/1/19 12:10 PM, Suman Anna wrote:
> Hi Marc,
> 
> On 8/1/19 3:45 AM, Marc Zyngier wrote:
>> On 31/07/2019 23:41, Suman Anna wrote:
>>> The PRUSS INTC receives a number of system input interrupt source events
>>> and supports individual control configuration and hardware prioritization.
>>> These input events can be mapped to some output interrupt lines through 2
>>> levels of many-to-one mapping i.e. events to channel mapping and channels
>>> to output interrupts.
>>>
>>> This mapping information is provided through the PRU firmware that is
>>> loaded onto a PRU core/s or through the device tree node of the PRU
>>> application. The mapping is configured by the PRU remoteproc driver, and
>>> is setup before the PRU core is started and cleaned up after the PRU core
>>> is stopped. This event mapping configuration logic programs the Channel
>>> Map Registers (CMRx) and Host-Interrupt Map Registers (HMRx) only when a
>>> new program is being loaded/started and the same events and interrupt
>>> channels are reset to zero when stopping a PRU.
>>>
>>> Add two helper functions: pruss_intc_configure() & pruss_intc_unconfigure()
>>> that the PRU remoteproc driver can use to configure the PRUSS INTC.
>>
>> So let me see if I correctly understand this: this adds yet another
>> firmware description parser, with a private interface to another
>> (undisclosed?) driver, bypassing the standard irqchip configuration
>> mechanism. It sounds great, doesn't it?
>>
>> What I cannot really infer from this message (-ETOOMUCHJARGON) is what
>> interrupts this affects:
>>
>> - Interrupts from random devices to the PRUSS?
>> - Interrupts from the PRUSS to the host?
>> - Something else?
> 
> The interrupt sources (called system events) can be from internal PRUSS
> peripherals, SoC-level peripherals or just software triggering (limited
> to some events).
> 
> So, the PRUSS INTC behaves as a funnel and is both an interrupt router
> and multiplexer. The INTC itself is part of the PRUSS, and all PRU
> application related interrupts/events that need to trigger an interrupt
> to either the PRU cores or other host processors (like DSP, ARM) have to
> go through this INTC, and routed out to a limited number of output
> interrupts that are then connected to different processors.
> 
> The split of interrupt handling between a PRU and its peer host
> processor will be a application design choice (We can implement soft IPs
> like UARTs, ADCs, I2Cs etc using PRUs). Some of the input events
> themselves are multiplexed and controlled by a single MMR (outside of
> INTC) that feeds different sets of events into the INTC. The MMR
> configuration is outside of scope of this driver and will depend on the
> application/client driver being run.
> 
>>
>> When does this happen? Under control of what? It isn't even clear why
>> this is part of this irqchip driver.
> 
> The mapping configuration is per PRU application and firmware, and is
> done in line with acquiring and release a PRU which is treated as an
> exclusive resource. We establish the mapping for all events through this
> driver including the events that are to be routed to PRUs. This is done
> to save the tiny/limited Instruction RAM space that PRUs have.
> 
> We have designed this as an irqchip driver (instead of some custom SoC
> driver exporting custom functions) to use standard Linux semantics/irq
> API and better integrate with Linux DT, but we need some semantics for
> establishing the routing at runtime depending on the PRU client driver
> we are running. The exported functions will be called only by the PRU
> remoteproc driver during a pru_rproc_get()/pru_rproc_put(), and are
> transparent to PRU client drivers.
> 
> Please also see the discussion from v1 [1] on why we can't use an
> extended number of interrupt-cells infrastructure for achieving this.
> 
> [1] https://patchwork.kernel.org/patch/11034563/
> 
> 
>> Depending what this does, there may be ways to fit it into the standard
>> interrupt configuration framework. After all, we already have standard
>> interfaces to route interrupts to virtual CPUs, effectively passing full
>> control of an interrupt to another entity. If you squint hard enough,
>> your PRUSS can fit that description.
> 
> Yeah, I am open to suggestions if there is a better way of doing this.

Hi Suman,

Can you explain more about the use case where one PRU system event is
mapped to multiple host events?

I have an idea that we can use multiple struct irq_domains to make this
work in the existing IRQ framework, but it would be helpful to know more
about the bigger picture first.

> 
> regards
> Suman
> 
>>
>> If that doesn't work, then we need to make the IRQ framework grok that
>> kind of requirement (hence my request for clarification). But I'm
>> strongly opposed to inventing a SoC-private way of configuring
>> interrupts behind the kernel's back.
>>
>> Thanks,
>>
>> 	M.
>>
> 

Re: [PATCH v2 4/6] irqchip/irq-pruss-intc: Add helper functions to configure internal mapping

[Suman Anna]

Hi David,

On 8/1/19 1:31 PM, David Lechner wrote:
> On 8/1/19 12:10 PM, Suman Anna wrote:
>> Hi Marc,
>> 
>> On 8/1/19 3:45 AM, Marc Zyngier wrote:
>>> On 31/07/2019 23:41, Suman Anna wrote:
>>>> The PRUSS INTC receives a number of system input interrupt
>>>> source events and supports individual control configuration and
>>>> hardware prioritization. These input events can be mapped to
>>>> some output interrupt lines through 2 levels of many-to-one
>>>> mapping i.e. events to channel mapping and channels to output
>>>> interrupts.
>>>> 
>>>> This mapping information is provided through the PRU firmware
>>>> that is loaded onto a PRU core/s or through the device tree
>>>> node of the PRU application. The mapping is configured by the
>>>> PRU remoteproc driver, and is setup before the PRU core is
>>>> started and cleaned up after the PRU core is stopped. This
>>>> event mapping configuration logic programs the Channel Map
>>>> Registers (CMRx) and Host-Interrupt Map Registers (HMRx) only 
>>>> when a new program is being loaded/started and the same events
>>>> and interrupt channels are reset to zero when stopping a PRU.
>>>> 
>>>> Add two helper functions: pruss_intc_configure() & 
>>>> pruss_intc_unconfigure() that the PRU remoteproc driver can use
>>>> to configure the PRUSS INTC.
>>> 
>>> So let me see if I correctly understand this: this adds yet
>>> another firmware description parser, with a private interface to
>>> another (undisclosed?) driver, bypassing the standard irqchip
>>> configuration mechanism. It sounds great, doesn't it?
>>> 
>>> What I cannot really infer from this message (-ETOOMUCHJARGON) is
>>> what interrupts this affects:
>>> 
>>> - Interrupts from random devices to the PRUSS? - Interrupts from
>>> the PRUSS to the host? - Something else?
>> 
>> The interrupt sources (called system events) can be from internal
>> PRUSS peripherals, SoC-level peripherals or just software
>> triggering (limited to some events).
>> 
>> So, the PRUSS INTC behaves as a funnel and is both an interrupt
>> router and multiplexer. The INTC itself is part of the PRUSS, and
>> all PRU application related interrupts/events that need to trigger
>> an interrupt to either the PRU cores or other host processors (like
>> DSP, ARM) have to go through this INTC, and routed out to a limited
>> number of output interrupts that are then connected to different
>> processors.
>> 
>> The split of interrupt handling between a PRU and its peer host 
>> processor will be a application design choice (We can implement
>> soft IPs like UARTs, ADCs, I2Cs etc using PRUs). Some of the input
>> events themselves are multiplexed and controlled by a single MMR
>> (outside of INTC) that feeds different sets of events into the
>> INTC. The MMR configuration is outside of scope of this driver and
>> will depend on the application/client driver being run.
>> 
>>> 
>>> When does this happen? Under control of what? It isn't even clear
>>> why this is part of this irqchip driver.
>> 
>> The mapping configuration is per PRU application and firmware, and
>> is done in line with acquiring and release a PRU which is treated
>> as an exclusive resource. We establish the mapping for all events
>> through this driver including the events that are to be routed to
>> PRUs. This is done to save the tiny/limited Instruction RAM space
>> that PRUs have.
>> 
>> We have designed this as an irqchip driver (instead of some custom
>> SoC driver exporting custom functions) to use standard Linux
>> semantics/irq API and better integrate with Linux DT, but we need
>> some semantics for establishing the routing at runtime depending on
>> the PRU client driver we are running. The exported functions will
>> be called only by the PRU remoteproc driver during a
>> pru_rproc_get()/pru_rproc_put(), and are transparent to PRU client
>> drivers.
>> 
>> Please also see the discussion from v1 [1] on why we can't use an 
>> extended number of interrupt-cells infrastructure for achieving
>> this.
>> 
>> [1] https://patchwork.kernel.org/patch/11034563/
>> 
>> 
>>> Depending what this does, there may be ways to fit it into the
>>> standard interrupt configuration framework. After all, we already
>>> have standard interfaces to route interrupts to virtual CPUs,
>>> effectively passing full control of an interrupt to another
>>> entity. If you squint hard enough, your PRUSS can fit that
>>> description.
>> 
>> Yeah, I am open to suggestions if there is a better way of doing
>> this.
> 

> Hi Suman,
> 
> Can you explain more about the use case where one PRU system event
> is mapped to multiple host events?

On AM335x, for example, we have 64 events out of which events 16 to 31
are not sourced by any peripherals and are used for general purpose
signaling between a PRU0/PRU1 core and any external host processor (like
an ARM). So, different applications/drivers implementing a different
soft IP like a Soft UART, Soft I2C, ADC etc will need to be using among
these generic set to achieve their various interrupts / signaling logic
between the corresponding ARM driver and the PRU firmware implementing
the soft IP.

Following are some existing usage examples on AM335x within TI SDKs
(tuples of <system_event intr_channel output_interrupt>
1. A Soft UART implementing 3 ports per PRU:
PRU0: <21, 2, 2>, <22, 3, 3>, <23, 4, 4>
PRU1: <24, 5, 5>, <25, 6, 6>, <26, 7, 7>;

2. A Dual-EMAC PRU Ethernet usecase using one PRU per ethernet port
utilizing the MDIO, MII_TI sub-modules within PRUSS:
PRU0: {42, 0, 0}, {20, 2, 2}, {22, 4, 4}, {26, 6, 6}, {41, 7, 8},
PRU1: {54, 1, 1}, {21, 3, 3}, {23, 5, 5}, {53, 8, 9}, {27, 9, 7},

Some of the above PRU Ethernet ones are generic events while the others
are tied to specific MII_RT interrupt events. A different mapping is
used when both the ethernet ports and PRUs are being used to achieve a
Switch functionality.

Point is different applications might use mapping differently as per
their firmware and driver/application design and their split across one
or more PRUs (design by contract). And we need to set this up at runtime
when the application driver is getting run. We will have either the Soft
UART or the Ethernet running at a time depending on the end goal desired

> I have an idea that we can use multiple struct irq_domains to make
> this work in the existing IRQ framework, but it would be helpful to
> know more about the bigger picture first.

Yeah, would be great if there is a way this can be solved without having
to introduce additional API.

regards
Suman

> 
>> 
>> regards Suman
>> 
>>> 
>>> If that doesn't work, then we need to make the IRQ framework grok
>>> that kind of requirement (hence my request for clarification).
>>> But I'm strongly opposed to inventing a SoC-private way of
>>> configuring interrupts behind the kernel's back.
>>> 
>>> Thanks,
>>> 
>>> M.
>>> 
>> 
> 

Re: [PATCH v2 4/6] irqchip/irq-pruss-intc: Add helper functions to configure internal mapping

[David Lechner]

On 8/2/19 4:26 PM, Suman Anna wrote:
> Point is different applications might use mapping differently as per
> their firmware and driver/application design and their split across one
> or more PRUs (design by contract). And we need to set this up at runtime
> when the application driver is getting run. We will have either the Soft
> UART or the Ethernet running at a time depending on the end goal desired
> 
>> I have an idea that we can use multiple struct irq_domains to make
>> this work in the existing IRQ framework, but it would be helpful to
>> know more about the bigger picture first.
> 
> Yeah, would be great if there is a way this can be solved without having
> to introduce additional API.
> 


Here is what I came up with to use existing IRQ APIs to implement event mapping.
Basically it is the same as my previous suggestion [1], with the addition of
multiple IRQ domains.

The idea is that each external interrupt controller (or DMA controller, etc.)
that is connected to the PRUSS interrupt controller is considered an interrupt
domain. One of the objections to my previous patch was that we could only have
one IRQ descriptor per event. Now we can have one descriptor per event per
domain.

I am still proposing that we use the interrupt-cells and identical vendor
resource data structures in the PRU firmware be used to provide the mapping
information. (As a side note, I still think it is important to include EVTSEL
on AM18xx in order to fully describe the event.)

The bindings will have N = 4 cells (or N = 5 when EVTSEL is required to fully
describe the event):

	Cell 0: The PRUSS event number, e.g. 0 to 64 for most PRUSSs
	Cell 1: The EVTSEL value (omitted when N == 4), e.g. 0, 1 or
		TI_PRUSS_INTC_EVTSEL_ANY if the event is the same for all EVTSEL
		values. On AM18xx, external events will all require 0 or 1 while
		system events will always be TI_PRUSS_INTC_EVTSEL_ANY.
	Cell N-3: The channel that the event gets mapped to, e.g. 0 to 9
	Cell N-2: The host that the channel gets mapped to, e.g. 0 to 9
	Cell N-1: The interrupt domain, e.g. TI_PRUSS_INTC_DOMAIN_PRU or
		TI_PRUSS_INTC_DOMAIN_MCU

The TI_PRUSS_INTC_DOMAIN_* values are just arbitrary numbers assigned to the
possible domains. For example, on AM18xx and AM33xx, there are just two domains,
the PRU domain for host 0 and host 1 and the MCU domain for host 2 thru 9.
Looking at the AM65xx manual, it looks like it would have 4 domains, the PRU
domain, the RTU PRU domain, the MCU domain and a task manager domain. (And I
suppose that domains could even be more granular if needed, e.g. we could drop
the arbitrary domain number and treat each host interrupt/event as an interrupt
domain, then there would be an IRQ descriptor per PRU INTC event per host.)

The AM18xx example I have been using will look like this in the device tree:

	interrupts = <63 TI_PRUSS_INTC_EVTSEL_ANY 0 0 TI_PRUSS_INTC_DOMAIN_PRU>,
		     <62 TI_PRUSS_INTC_EVTSEL_ANY 2 2 TI_PRUSS_INTC_DOMAIN_MCU>;

To keep parsing simple, the PRU firmware can include vendor resources that have
essentially the same format as the device tree bindings. For example:

enum {
	/* IRQ descriptor without EVTSEL */
	TI_PRU_VENDOR_RESOURCE_IRQ = RSC_VENDOR_START,
	/* IRQ descriptor with EVTSEL */
	TI_PRU_VENDOR_RESOURCE_IRQ2,
};

struct ti_pru_vendor_resource_irq {
	__le32 event;
	__le32 channel;
	__le32 host;
	__le32 domain;
};

struct ti_pru_vendor_resource_irq2 {
	__le32 event;
	__le32 evt_sel;
	__le32 channel;
	__le32 host;
	__le32 domain;
};

Then we can provide a vendor resource hook in the remoteproc driver to handle
these resources:

static int ti_pru_rproc_handle_rsc(struct rproc *rproc, u32 rsc_type, void *rsc,
				   int offset, int avail)
{
	struct ti_pru_data *pru = rproc->priv;
	struct irq_fwspec fwspec;
	unsigned int virq;

	switch (rsc_type) {
	case TI_PRU_VENDOR_RESOURCE_IRQ:
	{
		struct ti_pru_vendor_resource_irq *rsc_irq = rsc;

		fwspec.fwnode = pru->intc_fwnode;
		fwspec.param[0] = le32_to_cpu(rsc_irq->event);
		fwspec.param[1] = le32_to_cpu(rsc_irq->channel);
		fwspec.param[2] = le32_to_cpu(rsc_irq->host);
		fwspec.param[3] = le32_to_cpu(rsc_irq->domain);
		fwspec.param_count = 4;
	}
		break;
	case TI_PRU_VENDOR_RESOURCE_IRQ2:
	{
		struct ti_pru_vendor_resource_irq2 *rsc_irq2 = rsc;

		fwspec.fwnode = pru->intc_fwnode;
		fwspec.param[0] = le32_to_cpu(rsc_irq2->event);
		fwspec.param[1] = le32_to_cpu(rsc_irq2->evt_sel);
		fwspec.param[2] = le32_to_cpu(rsc_irq2->channel);
		fwspec.param[3] = le32_to_cpu(rsc_irq2->host);
		fwspec.param[4] = le32_to_cpu(rsc_irq2->domain);
		fwspec.param_count = 5;
		break;
	}
	default:
		return RSC_IGNORED;
	}

	virq = irq_create_fwspec_mapping(&fwspec);
	if (!virq)
		return -EINVAL;

	/* TODO: save virq (and other metadata) for later use */

	return RSC_HANDLED;
}

static const struct rproc_ops ti_pru_rproc_ops = {
	.start = ti_pru_rproc_start,
	.stop = ti_pru_rproc_stop,
	.kick = ti_pru_rproc_kick,
	.da_to_va = ti_pru_rproc_da_to_va,
	.handle_rsc = ti_pru_rproc_handle_rsc,
};

The handle_rsc callback is called for each resource when the PRU is booted.
The function irq_create_fwspec_mapping() causes the IRQ to be mapped in
hardware. From what I understand from the previous discussions, this is exactly
when we want this to happen.

This patch applies on top of "irqchip/irq-pruss-intc: Add a PRUSS irqchip driver
for PRUSS interrupts", "irqchip/irq-pruss-intc: Add support for shared and
invalid interrupts" and "irqchip/irq-pruss-intc: Implement irq_{get,set}
_irqchip_state ops" from [PATCH v2 0/6] "Add TI PRUSS Local Interrupt Controller
IRQChip driver" [2].

A working copy along with some remoteproc and rpmsg hacks can be found on my
GitHub [3].

[1]: https://lore.kernel.org/lkml/fb2bdb7b-4d4d-508f-722a-554888280145@lechnology.com/
[2]: https://lore.kernel.org/lkml/20190731224149.11153-1-s-anna@ti.com/
[3]: https://github.com/dlech/linux/commits/pruss-2019-08-08

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: David Lechner <david@lechnology.com>
---
  drivers/irqchip/irq-pruss-intc.c              | 387 +++++++++++++++++-
  .../interrupt-controller/ti-pruss.h           |  27 ++
  2 files changed, 396 insertions(+), 18 deletions(-)
  create mode 100644 include/dt-bindings/interrupt-controller/ti-pruss.h

diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c
index c1fd6c09f2f2..da4349df08c3 100644
--- a/drivers/irqchip/irq-pruss-intc.c
+++ b/drivers/irqchip/irq-pruss-intc.c
@@ -5,6 +5,8 @@
   * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
   *	Andrew F. Davis <afd@ti.com>
   *	Suman Anna <s-anna@ti.com>
+ *
+ * Copyright (C) 2019 David Lechner <david@lechnology.com>
   */
  
  #include <linux/interrupt.h>
@@ -14,6 +16,14 @@
  #include <linux/module.h>
  #include <linux/of_device.h>
  #include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include <dt-bindings/interrupt-controller/ti-pruss.h>
+
+/* The number of possible interrupt domains, see TI_PRUSS_INTC_DOMAIN_* in
+ * dt-bindings/interrupt-controller/ti-pruss.h
+ */
+#define NUM_TI_PRUSS_INTC_DOMAIN 5
  
  /*
   * Number of host interrupts reaching the main MPU sub-system. Note that this
@@ -25,6 +35,12 @@
  /* minimum starting host interrupt number for MPU */
  #define MIN_PRU_HOST_INT	2
  
+/* maximum number of host interrupts */
+#define MAX_PRU_HOST_INT	10
+
+/* maximum number of interrupt channels */
+#define MAX_PRU_CHANNELS	10
+
  /* maximum number of system events */
  #define MAX_PRU_SYS_EVENTS	64
  
@@ -57,27 +73,83 @@
  #define PRU_INTC_HINLR(x)	(0x1100 + (x) * 4)
  #define PRU_INTC_HIER		0x1500
  
+/* CMR register bit-field macros */
+#define CMR_EVT_MAP_MASK	0xf
+#define CMR_EVT_MAP_BITS	8
+#define CMR_EVT_PER_REG		4
+
+/* HMR register bit-field macros */
+#define HMR_CH_MAP_MASK		0xf
+#define HMR_CH_MAP_BITS		8
+#define HMR_CH_PER_REG		4
+
  /* HIPIR register bit-fields */
  #define INTC_HIPIR_NONE_HINT	0x80000000
  
+/**
+ * struct pruss_intc_hwirq_data - additional metadata associated with a PRU
+ * system event
+ * @evtsel: The event select index (AM18xx only)
+ * @channel: The PRU INTC channel that the system event should be mapped to
+ * @host: The PRU INTC host that the channel should be mapped to
+ */
+struct pruss_intc_hwirq_data {
+	u8 evtsel;
+	u8 channel;
+	u8 host;
+};
+
+/**
+ * struct pruss_intc_map_record - keeps track of actual mapping state
+ * @value: The currently mapped value (evtsel, channel or host)
+ * @ref_count: Keeps track of number of current users of this resource
+ */
+struct pruss_intc_map_record {
+	u8 value;
+	u8 ref_count;
+};
+
+/**
+ * struct pruss_intc_domain - information specific to an external IRQ domain
+ * @hwirq_data: Table of additional mapping data received from device tree
+ *	or PRU firmware
+ * @domain: irq domain
+ * @intc: the interrupt controller
+ * @id: Unique domain identifier (from device tree bindings)
+ */
+struct pruss_intc_domain {
+	struct pruss_intc_hwirq_data hwirq_data[MAX_PRU_SYS_EVENTS];
+	struct irq_domain *domain;
+	struct pruss_intc *intc;
+	u32 id;
+};
+
  /**
   * struct pruss_intc - PRUSS interrupt controller structure
+ * @domain: External interrupt domains
+ * @evtsel: Tracks the current state of CFGCHIP3[3].PRUSSEVTSEL (AM18xx only)
+ * @event_channel: Tracks the current state of system event to channel mappings
+ * @channel_host: Tracks the current state of channel to host mappings
   * @irqs: kernel irq numbers corresponding to PRUSS host interrupts
   * @base: base virtual address of INTC register space
   * @irqchip: irq chip for this interrupt controller
- * @domain: irq domain for this interrupt controller
   * @lock: mutex to serialize access to INTC
   * @shared_intr: bit-map denoting if the MPU host interrupt is shared
   * @invalid_intr: bit-map denoting if host interrupt is not connected to MPU
+ * @has_evtsel: indicates that the chip has an event select mux
   */
  struct pruss_intc {
+	struct pruss_intc_domain domain[NUM_ISA_INTERRUPTS];
+	struct pruss_intc_map_record evtsel;
+	struct pruss_intc_map_record event_channel[MAX_PRU_SYS_EVENTS];
+	struct pruss_intc_map_record channel_host[MAX_PRU_CHANNELS];
  	unsigned int irqs[MAX_NUM_HOST_IRQS];
  	void __iomem *base;
  	struct irq_chip *irqchip;
-	struct irq_domain *domain;
  	struct mutex lock; /* PRUSS INTC lock */
  	u16 shared_intr;
  	u16 invalid_intr;
+	bool has_evtsel;
  };
  
  static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned int reg)
@@ -105,6 +177,172 @@ static int pruss_intc_check_write(struct pruss_intc *intc, unsigned int reg,
  	return 0;
  }
  
+/**
+ * pruss_intc_map() - configure the PRUSS INTC
+ * @domain: pru intc domain pointer
+ * @hwirq: the system event number
+ *
+ * Configures the PRUSS INTC with the provided configuration from the one
+ * parsed in the xlate function. Any existing event to channel mappings or
+ * channel to host interrupt mappings are checked to make sure there are no
+ * conflicting configuration between both the PRU cores.
+ *
+ * Returns 0 on success, or a suitable error code otherwise
+ */
+static int pruss_intc_map(struct pruss_intc_domain *domain, unsigned long hwirq)
+{
+	struct pruss_intc *intc = domain->intc;
+	struct device* dev = intc->irqchip->parent_device;
+	u32 val;
+	int idx, ret;
+	u8 evtsel, ch, host;
+
+	if (hwirq >= MAX_PRU_SYS_EVENTS)
+		return -EINVAL;
+
+	mutex_lock(&intc->lock);
+
+	evtsel = domain->hwirq_data[hwirq].evtsel;
+	ch = domain->hwirq_data[hwirq].channel;
+	host = domain->hwirq_data[hwirq].host;
+
+	if (intc->has_evtsel && intc->evtsel.ref_count > 0 &&
+	    intc->evtsel.value != evtsel) {
+		dev_err(dev, "event %lu (req. evtsel %d) already assigned to evtsel %d\n",
+			hwirq, evtsel, intc->evtsel.value);
+		ret = -EBUSY;
+		goto unlock;
+	}
+
+	/* check if sysevent already assigned */
+	if (intc->event_channel[hwirq].ref_count > 0 &&
+	    intc->event_channel[hwirq].value != ch) {
+		dev_err(dev, "event %lu (req. channel %d) already assigned to channel %d\n",
+			hwirq, ch, intc->event_channel[hwirq].value);
+		ret = -EBUSY;
+		goto unlock;
+	}
+
+	/* check if channel already assigned */
+	if (intc->channel_host[ch].ref_count > 0 &&
+	    intc->channel_host[ch].value != host) {
+		dev_err(dev, "channel %d (req. host %d) already assigned to host %d\n",
+			ch, host, intc->channel_host[ch].value);
+		ret = -EBUSY;
+		goto unlock;
+	}
+
+	if (++intc->evtsel.ref_count == 1) {
+		intc->evtsel.value = evtsel;
+
+		/* TODO: need to implement CFGCHIP3[3].PRUSSEVTSEL */
+	}
+
+	if (++intc->event_channel[hwirq].ref_count == 1) {
+		intc->event_channel[hwirq].value = ch;
+
+		/*
+		 * configure channel map registers - each register holds map
+		 * info for 4 events, with each event occupying the lower nibble
+		 * in a register byte address in little-endian fashion
+		 */
+		idx = hwirq / CMR_EVT_PER_REG;
+
+		val = pruss_intc_read_reg(intc, PRU_INTC_CMR(idx));
+		val &= ~(CMR_EVT_MAP_MASK <<
+				((hwirq % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS));
+		val |= ch << ((hwirq % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS);
+		pruss_intc_write_reg(intc, PRU_INTC_CMR(idx), val);
+
+		dev_dbg(dev, "SYSEV%lu -> CH%d (CMR%d 0x%08x)\n", hwirq, ch,
+			idx, pruss_intc_read_reg(intc, PRU_INTC_CMR(idx)));
+
+		/* clear and enable system event */
+		pruss_intc_write_reg(intc, PRU_INTC_SICR, hwirq);
+		pruss_intc_write_reg(intc, PRU_INTC_EISR, hwirq);
+	}
+
+	if (++intc->channel_host[ch].ref_count == 1) {
+		intc->channel_host[ch].value = host;
+
+		/*
+		 * set host map registers - each register holds map info for
+		 * 4 channels, with each channel occupying the lower nibble in
+		 * a register byte address in little-endian fashion
+		 */
+		idx = ch / HMR_CH_PER_REG;
+
+		val = pruss_intc_read_reg(intc, PRU_INTC_HMR(idx));
+		val &= ~(HMR_CH_MAP_MASK <<
+				((ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS));
+		val |= host << ((ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS);
+		pruss_intc_write_reg(intc, PRU_INTC_HMR(idx), val);
+
+		dev_dbg(dev, "CH%d -> HOST%d (HMR%d 0x%08x)\n", ch, host, idx,
+			pruss_intc_read_reg(intc, PRU_INTC_HMR(idx)));
+
+		/* enable host interrupts */
+		pruss_intc_write_reg(intc, PRU_INTC_HIEISR, host);
+	}
+
+	dev_info(dev, "mapped system_event = %lu channel = %d host = %d domain = %u\n",
+		 hwirq, ch, host, domain->id);
+
+	/* global interrupt enable */
+	pruss_intc_write_reg(intc, PRU_INTC_GER, 1);
+
+	mutex_unlock(&intc->lock);
+	return 0;
+
+unlock:
+	mutex_unlock(&intc->lock);
+	return ret;
+}
+
+/**
+ * pruss_intc_unmap() - unconfigure the PRUSS INTC
+ * @domain: pru intc domain pointer
+ * @hwirq: the system event number
+ *
+ * Undo whatever was done in pruss_intc_map() for a PRU core.
+ * Mappings are reference counted, so resources are only disabled when there
+ * are no longer any users.
+ */
+static void pruss_intc_unmap(struct pruss_intc_domain *domain, unsigned long hwirq)
+{
+	struct pruss_intc *intc = domain->intc;
+	struct device* dev = intc->irqchip->parent_device;
+	u8 ch, host;
+
+	if (hwirq >= MAX_PRU_SYS_EVENTS)
+		return;
+
+	mutex_lock(&intc->lock);
+
+	ch = intc->event_channel[hwirq].value;
+	host = intc->channel_host[ch].value;
+
+	if (--intc->channel_host[ch].ref_count == 0) {
+		/* disable host interrupts */
+		pruss_intc_write_reg(intc, PRU_INTC_HIDISR, host);
+	}
+
+	if (--intc->event_channel[hwirq].ref_count == 0) {
+		/* disable system events */
+		pruss_intc_write_reg(intc, PRU_INTC_EICR, hwirq);
+		/* clear any pending status */
+		pruss_intc_write_reg(intc, PRU_INTC_SICR, hwirq);
+	}
+
+	if (intc->has_evtsel)
+		intc->evtsel.ref_count--;
+
+	dev_info(dev, "unmapped system_event = %lu channel = %d host = %d\n",
+		 hwirq, ch, host);
+
+	mutex_unlock(&intc->lock);
+}
+
  static void pruss_intc_init(struct pruss_intc *intc)
  {
  	int i;
@@ -198,10 +436,83 @@ static int pruss_intc_irq_set_irqchip_state(struct irq_data *data,
  	return pruss_intc_check_write(intc, PRU_INTC_SICR, data->hwirq);
  }
  
+static int pruss_intc_irq_domain_select(struct irq_domain *d,
+					struct irq_fwspec *fwspec,
+					enum irq_domain_bus_token bus_token)
+{
+	struct pruss_intc_domain *domain = d->host_data;
+	int num_cells = domain->intc->has_evtsel ? 5 : 4;
+	u32 domain_id;
+
+	if (!fwspec || fwspec->fwnode != domain->domain->fwnode)
+		return 0;
+
+	if (bus_token != DOMAIN_BUS_ANY && bus_token != domain->domain->bus_token)
+		return 0;
+
+	if (WARN_ON_ONCE(fwspec->param_count != num_cells))
+		return 0;
+
+	domain_id = fwspec->param[fwspec->param_count - 1];
+	if (domain_id != domain->id)
+		return 0;
+
+	return 1;
+}
+
+static int
+pruss_intc_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
+			    const u32 *intspec, unsigned int intsize,
+			    unsigned long *out_hwirq, unsigned int *out_type)
+{
+	struct pruss_intc_domain *domain = d->host_data;
+	struct pruss_intc *intc = domain->intc;
+	int num_cells = intc->has_evtsel ? 5 : 4;
+	u32 sys_event, channel, host, domain_id;
+	u32 evtsel = 0;
+
+	if (WARN_ON_ONCE(intsize != num_cells))
+		return -EINVAL;
+
+	sys_event = intspec[0];
+	if (sys_event >= MAX_PRU_SYS_EVENTS)
+		return -EINVAL;
+
+	if (intc->has_evtsel)
+		evtsel = intspec[1];
+
+	channel = intspec[intsize - 3];
+	if (channel >= MAX_PRU_CHANNELS)
+		return -EINVAL;
+
+	host = intspec[intsize - 2];
+	if (host >= MAX_PRU_HOST_INT)
+		return -EINVAL;
+
+	domain_id = intspec[intsize - 1];
+	if (domain_id != domain->id)
+		return -EINVAL;
+
+	domain->hwirq_data[sys_event].evtsel = evtsel;
+	domain->hwirq_data[sys_event].channel = channel;
+	domain->hwirq_data[sys_event].host = host;
+
+	*out_hwirq = sys_event;
+	*out_type = IRQ_TYPE_NONE;
+
+	return 0;
+}
+
  static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int virq,
  				     irq_hw_number_t hw)
  {
-	struct pruss_intc *intc = d->host_data;
+	struct pruss_intc_domain *domain = d->host_data;
+	struct pruss_intc *intc = domain->intc;
+	int err;
+
+	err = pruss_intc_map(domain, hw);
+	if (err < 0)
+		return err;
  
  	irq_set_chip_data(virq, intc);
  	irq_set_chip_and_handler(virq, intc->irqchip, handle_level_irq);
@@ -211,12 +522,17 @@ static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int virq,
  
  static void pruss_intc_irq_domain_unmap(struct irq_domain *d, unsigned int virq)
  {
+	struct pruss_intc_domain *domain = d->host_data;
+	unsigned long hwirq = irqd_to_hwirq(irq_get_irq_data(virq));
+
  	irq_set_chip_and_handler(virq, NULL, NULL);
  	irq_set_chip_data(virq, NULL);
+	pruss_intc_unmap(domain, hwirq);
  }
  
  static const struct irq_domain_ops pruss_intc_irq_domain_ops = {
-	.xlate	= irq_domain_xlate_onecell,
+	.select	= pruss_intc_irq_domain_select,
+	.xlate	= pruss_intc_irq_domain_xlate,
  	.map	= pruss_intc_irq_domain_map,
  	.unmap	= pruss_intc_irq_domain_unmap,
  };
@@ -245,7 +561,8 @@ static void pruss_intc_irq_handler(struct irq_desc *desc)
  	hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i));
  	while (!(hipir & INTC_HIPIR_NONE_HINT)) {
  		hwirq = hipir & GENMASK(9, 0);
-		virq = irq_linear_revmap(intc->domain, hwirq);
+		virq = irq_linear_revmap(
+			intc->domain[TI_PRUSS_INTC_DOMAIN_MCU].domain, hwirq);
  
  		/*
  		 * NOTE: manually ACK any system events that do not have a
@@ -272,7 +589,8 @@ static int pruss_intc_probe(struct platform_device *pdev)
  	struct pruss_intc *intc;
  	struct resource *res;
  	struct irq_chip *irqchip;
-	int i, irq, count;
+	int i, err, irq, count;
+	u32 num_cells;
  	u8 temp_intr[MAX_NUM_HOST_IRQS] = { 0 };
  
  	intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL);
@@ -323,13 +641,22 @@ static int pruss_intc_probe(struct platform_device *pdev)
  		}
  	}
  
+	err = of_property_read_u32(dev->of_node, "#interrupt-cells", &num_cells);
+	if (!err && num_cells == 5)
+		intc->has_evtsel = true;
+
  	mutex_init(&intc->lock);
  
+	pm_runtime_enable(dev);
+	pm_runtime_get_sync(dev);
+
  	pruss_intc_init(intc);
  
  	irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL);
-	if (!irqchip)
-		return -ENOMEM;
+	if (!irqchip) {
+		err = -ENOMEM;
+		goto fail_alloc;
+	}
  
  	irqchip->irq_ack = pruss_intc_irq_ack;
  	irqchip->irq_mask = pruss_intc_irq_mask;
@@ -338,14 +665,24 @@ static int pruss_intc_probe(struct platform_device *pdev)
  	irqchip->irq_release_resources = pruss_intc_irq_relres;
  	irqchip->irq_get_irqchip_state = pruss_intc_irq_get_irqchip_state;
  	irqchip->irq_set_irqchip_state = pruss_intc_irq_set_irqchip_state;
+	irqchip->parent_device = dev;
  	irqchip->name = dev_name(dev);
  	intc->irqchip = irqchip;
  
-	/* always 64 events */
-	intc->domain = irq_domain_add_linear(dev->of_node, MAX_PRU_SYS_EVENTS,
-					     &pruss_intc_irq_domain_ops, intc);
-	if (!intc->domain)
-		return -ENOMEM;
+	for (i = 0; i < NUM_TI_PRUSS_INTC_DOMAIN; i++) {
+		intc->domain[i].intc = intc;
+		intc->domain[i].id = i;
+		/* always 64 events */
+		intc->domain[i].domain = irq_domain_add_linear(dev->of_node,
+				MAX_PRU_SYS_EVENTS, &pruss_intc_irq_domain_ops,
+				&intc->domain[i]);
+		if (!intc->domain[i].domain) {
+			while (--i >= 0)
+				irq_domain_remove(intc->domain[i].domain);
+			err = -ENOMEM;
+			goto fail_alloc;
+		}
+	}
  
  	for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
  		irq = platform_get_irq_byname(pdev, irq_names[i]);
@@ -356,6 +693,7 @@ static int pruss_intc_probe(struct platform_device *pdev)
  
  			dev_err(dev, "platform_get_irq_byname failed for %s : %d\n",
  				irq_names[i], irq);
+			err = irq;
  			goto fail_irq;
  		}
  
@@ -372,13 +710,20 @@ static int pruss_intc_probe(struct platform_device *pdev)
  			irq_set_chained_handler_and_data(intc->irqs[i], NULL,
  							 NULL);
  	}
-	irq_domain_remove(intc->domain);
-	return irq;
+	for (i = 0; i < NUM_TI_PRUSS_INTC_DOMAIN; i++)
+		irq_domain_remove(intc->domain[i].domain);
+
+fail_alloc:
+	pm_runtime_put(dev);
+	pm_runtime_disable(dev);
+
+	return err;
  }
  
  static int pruss_intc_remove(struct platform_device *pdev)
  {
  	struct pruss_intc *intc = platform_get_drvdata(pdev);
+	struct device *dev = &pdev->dev;
  	unsigned int hwirq;
  	int i;
  
@@ -388,9 +733,15 @@ static int pruss_intc_remove(struct platform_device *pdev)
  							 NULL);
  	}
  
-	for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++)
-		irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq));
-	irq_domain_remove(intc->domain);
+	for (i = 0; i < NUM_TI_PRUSS_INTC_DOMAIN; i++) {
+		for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++)
+			irq_dispose_mapping(irq_find_mapping(
+					    intc->domain[i].domain, hwirq));
+		irq_domain_remove(intc->domain[i].domain);
+	}
+
+	pm_runtime_put(dev);
+	pm_runtime_disable(dev);
  
  	return 0;
  }
diff --git a/include/dt-bindings/interrupt-controller/ti-pruss.h b/include/dt-bindings/interrupt-controller/ti-pruss.h
new file mode 100644
index 000000000000..326a68c31bce
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/ti-pruss.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * This header provides constants for the Texas Instruments Programmable
+ * Realtime Unit Subsystem (PRUSS) interrupt controller.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_TI_PRUSS_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_TI_PRUSS_H
+
+/* interrupt specifier for optional cell 1 */
+
+#define TI_PRUSS_INTC_EVTSEL_ANY	0xffffffff
+
+/* interrupt specifier for cell #interrupt-cells - 1 */
+
+/* host interrupt is connected to PRU cores, e.g. host events 0 and 1 */
+#define TI_PRUSS_INTC_DOMAIN_PRU	0
+/* host interrupt is connected to MCU's interrupt controller  */
+#define TI_PRUSS_INTC_DOMAIN_MCU	1
+/* host interrupt is connected to DSP's interrupt controller  */
+#define TI_PRUSS_INTC_DOMAIN_DSP	2
+/* host interrupt is connected to the auxillary PRU cores  */
+#define TI_PRUSS_INTC_DOMAIN_RTU_PRU	3
+/* host interrupt is connected to the task managers  */
+#define TI_PRUSS_INTC_DOMAIN_TASK	4
+
+#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_TI_PRUSS_H */
-- 
2.17.1

Re: [PATCH v2 4/6] irqchip/irq-pruss-intc: Add helper functions to configure internal mapping

[David Lechner]

On 8/8/19 12:09 PM, David Lechner wrote:
> 
> Then we can provide a vendor resource hook in the remoteproc driver to handle
> these resources:
> 
> static int ti_pru_rproc_handle_rsc(struct rproc *rproc, u32 rsc_type, void *rsc,
>                     int offset, int avail)
> {
>      struct ti_pru_data *pru = rproc->priv;
>      struct irq_fwspec fwspec;
>      unsigned int virq;
> 
>      switch (rsc_type) {
>      case TI_PRU_VENDOR_RESOURCE_IRQ:
>      {
>          struct ti_pru_vendor_resource_irq *rsc_irq = rsc;
> 
>          fwspec.fwnode = pru->intc_fwnode;
>          fwspec.param[0] = le32_to_cpu(rsc_irq->event);
>          fwspec.param[1] = le32_to_cpu(rsc_irq->channel);
>          fwspec.param[2] = le32_to_cpu(rsc_irq->host);
>          fwspec.param[3] = le32_to_cpu(rsc_irq->domain);
>          fwspec.param_count = 4;
>      }
>          break;
>      case TI_PRU_VENDOR_RESOURCE_IRQ2:
>      {
>          struct ti_pru_vendor_resource_irq2 *rsc_irq2 = rsc;
> 
>          fwspec.fwnode = pru->intc_fwnode;
>          fwspec.param[0] = le32_to_cpu(rsc_irq2->event);
>          fwspec.param[1] = le32_to_cpu(rsc_irq2->evt_sel);
>          fwspec.param[2] = le32_to_cpu(rsc_irq2->channel);
>          fwspec.param[3] = le32_to_cpu(rsc_irq2->host);
>          fwspec.param[4] = le32_to_cpu(rsc_irq2->domain);
>          fwspec.param_count = 5;
>          break;
>      }
>      default:
>          return RSC_IGNORED;
>      }
> 
>      virq = irq_create_fwspec_mapping(&fwspec);
>      if (!virq)
>          return -EINVAL;
> 
>      /* TODO: save virq (and other metadata) for later use */
> 
>      return RSC_HANDLED;
> }
> 
> static const struct rproc_ops ti_pru_rproc_ops = {
>      .start = ti_pru_rproc_start,
>      .stop = ti_pru_rproc_stop,
>      .kick = ti_pru_rproc_kick,
>      .da_to_va = ti_pru_rproc_da_to_va,
>      .handle_rsc = ti_pru_rproc_handle_rsc,
> };
> 

After re-reading some of the previous discussions, it sounds like
we wouldn't want to always map every IRQ in the firmware resource
table.

In that case, we could implement the rproc_ops parse_fw callback
instead. All firmware nodes could be collected (from both the
firmware resource table and device tree) and the remoteproc driver
could decide which ones need to be mapped and which ones don't.
Then it could call irq_create_fwspec_mapping() only the nodes
that need to be mapped based on the current application.

Re: [PATCH v2 4/6] irqchip/irq-pruss-intc: Add helper functions to configure internal mapping

[Suman Anna]

Hi David,

On 8/8/19 12:09 PM, David Lechner wrote:
> On 8/2/19 4:26 PM, Suman Anna wrote:
>> Point is different applications might use mapping differently as per
>> their firmware and driver/application design and their split across one
>> or more PRUs (design by contract). And we need to set this up at runtime
>> when the application driver is getting run. We will have either the Soft
>> UART or the Ethernet running at a time depending on the end goal desired
>>
>>> I have an idea that we can use multiple struct irq_domains to make
>>> this work in the existing IRQ framework, but it would be helpful to
>>> know more about the bigger picture first.
>>
>> Yeah, would be great if there is a way this can be solved without having
>> to introduce additional API.
>>
> 
> 
> Here is what I came up with to use existing IRQ APIs to implement event
> mapping.
> Basically it is the same as my previous suggestion [1], with the
> addition of
> multiple IRQ domains.

First of all, many thanks for looking into the problem and providing
patches for the alternate solutions. If we were to not use any exported
functions, this approach does seem to be a viable solution. I am going
to play around with both [1] and this patch with all our existing
usecases and see if I run into any issues.

So, w.r.t this patch compared to [1], is the multiple IRQ domain solving
anything specifically? Our main issue is the re-purposing of a event
(and its mapping depending on the application), and the same issue will
remain whether we have multiple domains or not. Also, now we would
expect an event to migrate between different domains based on its usage.

> 
> The idea is that each external interrupt controller (or DMA controller,
> etc.)
> that is connected to the PRUSS interrupt controller is considered an
> interrupt
> domain. One of the objections to my previous patch was that we could
> only have
> one IRQ descriptor per event. Now we can have one descriptor per event per
> domain.
> 
> I am still proposing that we use the interrupt-cells and identical vendor
> resource data structures in the PRU firmware be used to provide the mapping
> information. (As a side note, I still think it is important to include
> EVTSEL
> on AM18xx in order to fully describe the event.)

W.r.t EVTSEL, it is a global value and applies to a range of events. I
have another equivalent register/functionality on most of the other SoCs
as well (a register in PRUSS_CFG space) that muxes standard events vs
MII_RT events. Again, that is limited to only a subset of all the system
events. So, should this continue to be a per event specifier, it will be
yet another mapping configuration data item (my idea was to manage this
once per application within the PRU remoteproc driver along with the
fwspec mapping).

regards
Suman

> 
> The bindings will have N = 4 cells (or N = 5 when EVTSEL is required to
> fully
> describe the event):
> 
>     Cell 0: The PRUSS event number, e.g. 0 to 64 for most PRUSSs
>     Cell 1: The EVTSEL value (omitted when N == 4), e.g. 0, 1 or
>         TI_PRUSS_INTC_EVTSEL_ANY if the event is the same for all EVTSEL
>         values. On AM18xx, external events will all require 0 or 1 while
>         system events will always be TI_PRUSS_INTC_EVTSEL_ANY.
>     Cell N-3: The channel that the event gets mapped to, e.g. 0 to 9
>     Cell N-2: The host that the channel gets mapped to, e.g. 0 to 9
>     Cell N-1: The interrupt domain, e.g. TI_PRUSS_INTC_DOMAIN_PRU or
>         TI_PRUSS_INTC_DOMAIN_MCU
> 
> The TI_PRUSS_INTC_DOMAIN_* values are just arbitrary numbers assigned to
> the
> possible domains. For example, on AM18xx and AM33xx, there are just two
> domains,
> the PRU domain for host 0 and host 1 and the MCU domain for host 2 thru 9.
> Looking at the AM65xx manual, it looks like it would have 4 domains, the
> PRU
> domain, the RTU PRU domain, the MCU domain and a task manager domain.
> (And I
> suppose that domains could even be more granular if needed, e.g. we
> could drop
> the arbitrary domain number and treat each host interrupt/event as an
> interrupt
> domain, then there would be an IRQ descriptor per PRU INTC event per host.)
> 
> The AM18xx example I have been using will look like this in the device
> tree:
> 
>     interrupts = <63 TI_PRUSS_INTC_EVTSEL_ANY 0 0
> TI_PRUSS_INTC_DOMAIN_PRU>,
>              <62 TI_PRUSS_INTC_EVTSEL_ANY 2 2 TI_PRUSS_INTC_DOMAIN_MCU>;
> 
> To keep parsing simple, the PRU firmware can include vendor resources
> that have
> essentially the same format as the device tree bindings. For example:
> 
> enum {
>     /* IRQ descriptor without EVTSEL */
>     TI_PRU_VENDOR_RESOURCE_IRQ = RSC_VENDOR_START,
>     /* IRQ descriptor with EVTSEL */
>     TI_PRU_VENDOR_RESOURCE_IRQ2,
> };
> 
> struct ti_pru_vendor_resource_irq {
>     __le32 event;
>     __le32 channel;
>     __le32 host;
>     __le32 domain;
> };
> 
> struct ti_pru_vendor_resource_irq2 {
>     __le32 event;
>     __le32 evt_sel;
>     __le32 channel;
>     __le32 host;
>     __le32 domain;
> };
> 
> Then we can provide a vendor resource hook in the remoteproc driver to
> handle
> these resources:
> 
> static int ti_pru_rproc_handle_rsc(struct rproc *rproc, u32 rsc_type,
> void *rsc,
>                    int offset, int avail)
> {
>     struct ti_pru_data *pru = rproc->priv;
>     struct irq_fwspec fwspec;
>     unsigned int virq;
> 
>     switch (rsc_type) {
>     case TI_PRU_VENDOR_RESOURCE_IRQ:
>     {
>         struct ti_pru_vendor_resource_irq *rsc_irq = rsc;
> 
>         fwspec.fwnode = pru->intc_fwnode;
>         fwspec.param[0] = le32_to_cpu(rsc_irq->event);
>         fwspec.param[1] = le32_to_cpu(rsc_irq->channel);
>         fwspec.param[2] = le32_to_cpu(rsc_irq->host);
>         fwspec.param[3] = le32_to_cpu(rsc_irq->domain);
>         fwspec.param_count = 4;
>     }
>         break;
>     case TI_PRU_VENDOR_RESOURCE_IRQ2:
>     {
>         struct ti_pru_vendor_resource_irq2 *rsc_irq2 = rsc;
> 
>         fwspec.fwnode = pru->intc_fwnode;
>         fwspec.param[0] = le32_to_cpu(rsc_irq2->event);
>         fwspec.param[1] = le32_to_cpu(rsc_irq2->evt_sel);
>         fwspec.param[2] = le32_to_cpu(rsc_irq2->channel);
>         fwspec.param[3] = le32_to_cpu(rsc_irq2->host);
>         fwspec.param[4] = le32_to_cpu(rsc_irq2->domain);
>         fwspec.param_count = 5;
>         break;
>     }
>     default:
>         return RSC_IGNORED;
>     }
> 
>     virq = irq_create_fwspec_mapping(&fwspec);
>     if (!virq)
>         return -EINVAL;
> 
>     /* TODO: save virq (and other metadata) for later use */
> 
>     return RSC_HANDLED;
> }
> 
> static const struct rproc_ops ti_pru_rproc_ops = {
>     .start = ti_pru_rproc_start,
>     .stop = ti_pru_rproc_stop,
>     .kick = ti_pru_rproc_kick,
>     .da_to_va = ti_pru_rproc_da_to_va,
>     .handle_rsc = ti_pru_rproc_handle_rsc,
> };
> 
> The handle_rsc callback is called for each resource when the PRU is booted.
> The function irq_create_fwspec_mapping() causes the IRQ to be mapped in
> hardware. From what I understand from the previous discussions, this is
> exactly
> when we want this to happen.
> 
> This patch applies on top of "irqchip/irq-pruss-intc: Add a PRUSS
> irqchip driver
> for PRUSS interrupts", "irqchip/irq-pruss-intc: Add support for shared and
> invalid interrupts" and "irqchip/irq-pruss-intc: Implement irq_{get,set}
> _irqchip_state ops" from [PATCH v2 0/6] "Add TI PRUSS Local Interrupt
> Controller
> IRQChip driver" [2].
> 
> A working copy along with some remoteproc and rpmsg hacks can be found
> on my
> GitHub [3].
> 
> [1]:
> https://lore.kernel.org/lkml/fb2bdb7b-4d4d-508f-722a-554888280145@lechnology.com/
> 
> [2]: https://lore.kernel.org/lkml/20190731224149.11153-1-s-anna@ti.com/
> [3]: https://github.com/dlech/linux/commits/pruss-2019-08-08
> 
> Signed-off-by: Suman Anna <s-anna@ti.com>
> Signed-off-by: Andrew F. Davis <afd@ti.com>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> Signed-off-by: David Lechner <david@lechnology.com>
> ---
>  drivers/irqchip/irq-pruss-intc.c              | 387 +++++++++++++++++-
>  .../interrupt-controller/ti-pruss.h           |  27 ++
>  2 files changed, 396 insertions(+), 18 deletions(-)
>  create mode 100644 include/dt-bindings/interrupt-controller/ti-pruss.h
> 
> diff --git a/drivers/irqchip/irq-pruss-intc.c
> b/drivers/irqchip/irq-pruss-intc.c
> index c1fd6c09f2f2..da4349df08c3 100644
> --- a/drivers/irqchip/irq-pruss-intc.c
> +++ b/drivers/irqchip/irq-pruss-intc.c
> @@ -5,6 +5,8 @@
>   * Copyright (C) 2016-2019 Texas Instruments Incorporated -
> http://www.ti.com/
>   *    Andrew F. Davis <afd@ti.com>
>   *    Suman Anna <s-anna@ti.com>
> + *
> + * Copyright (C) 2019 David Lechner <david@lechnology.com>
>   */
>  
>  #include <linux/interrupt.h>
> @@ -14,6 +16,14 @@
>  #include <linux/module.h>
>  #include <linux/of_device.h>
>  #include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +
> +#include <dt-bindings/interrupt-controller/ti-pruss.h>
> +
> +/* The number of possible interrupt domains, see TI_PRUSS_INTC_DOMAIN_* in
> + * dt-bindings/interrupt-controller/ti-pruss.h
> + */
> +#define NUM_TI_PRUSS_INTC_DOMAIN 5
>  
>  /*
>   * Number of host interrupts reaching the main MPU sub-system. Note
> that this
> @@ -25,6 +35,12 @@
>  /* minimum starting host interrupt number for MPU */
>  #define MIN_PRU_HOST_INT    2
>  
> +/* maximum number of host interrupts */
> +#define MAX_PRU_HOST_INT    10
> +
> +/* maximum number of interrupt channels */
> +#define MAX_PRU_CHANNELS    10
> +
>  /* maximum number of system events */
>  #define MAX_PRU_SYS_EVENTS    64
>  
> @@ -57,27 +73,83 @@
>  #define PRU_INTC_HINLR(x)    (0x1100 + (x) * 4)
>  #define PRU_INTC_HIER        0x1500
>  
> +/* CMR register bit-field macros */
> +#define CMR_EVT_MAP_MASK    0xf
> +#define CMR_EVT_MAP_BITS    8
> +#define CMR_EVT_PER_REG        4
> +
> +/* HMR register bit-field macros */
> +#define HMR_CH_MAP_MASK        0xf
> +#define HMR_CH_MAP_BITS        8
> +#define HMR_CH_PER_REG        4
> +
>  /* HIPIR register bit-fields */
>  #define INTC_HIPIR_NONE_HINT    0x80000000
>  
> +/**
> + * struct pruss_intc_hwirq_data - additional metadata associated with a
> PRU
> + * system event
> + * @evtsel: The event select index (AM18xx only)
> + * @channel: The PRU INTC channel that the system event should be
> mapped to
> + * @host: The PRU INTC host that the channel should be mapped to
> + */
> +struct pruss_intc_hwirq_data {
> +    u8 evtsel;
> +    u8 channel;
> +    u8 host;
> +};
> +
> +/**
> + * struct pruss_intc_map_record - keeps track of actual mapping state
> + * @value: The currently mapped value (evtsel, channel or host)
> + * @ref_count: Keeps track of number of current users of this resource
> + */
> +struct pruss_intc_map_record {
> +    u8 value;
> +    u8 ref_count;
> +};
> +
> +/**
> + * struct pruss_intc_domain - information specific to an external IRQ
> domain
> + * @hwirq_data: Table of additional mapping data received from device tree
> + *    or PRU firmware
> + * @domain: irq domain
> + * @intc: the interrupt controller
> + * @id: Unique domain identifier (from device tree bindings)
> + */
> +struct pruss_intc_domain {
> +    struct pruss_intc_hwirq_data hwirq_data[MAX_PRU_SYS_EVENTS];
> +    struct irq_domain *domain;
> +    struct pruss_intc *intc;
> +    u32 id;
> +};
> +
>  /**
>   * struct pruss_intc - PRUSS interrupt controller structure
> + * @domain: External interrupt domains
> + * @evtsel: Tracks the current state of CFGCHIP3[3].PRUSSEVTSEL (AM18xx
> only)
> + * @event_channel: Tracks the current state of system event to channel
> mappings
> + * @channel_host: Tracks the current state of channel to host mappings
>   * @irqs: kernel irq numbers corresponding to PRUSS host interrupts
>   * @base: base virtual address of INTC register space
>   * @irqchip: irq chip for this interrupt controller
> - * @domain: irq domain for this interrupt controller
>   * @lock: mutex to serialize access to INTC
>   * @shared_intr: bit-map denoting if the MPU host interrupt is shared
>   * @invalid_intr: bit-map denoting if host interrupt is not connected
> to MPU
> + * @has_evtsel: indicates that the chip has an event select mux
>   */
>  struct pruss_intc {
> +    struct pruss_intc_domain domain[NUM_ISA_INTERRUPTS];
> +    struct pruss_intc_map_record evtsel;
> +    struct pruss_intc_map_record event_channel[MAX_PRU_SYS_EVENTS];
> +    struct pruss_intc_map_record channel_host[MAX_PRU_CHANNELS];
>      unsigned int irqs[MAX_NUM_HOST_IRQS];
>      void __iomem *base;
>      struct irq_chip *irqchip;
> -    struct irq_domain *domain;
>      struct mutex lock; /* PRUSS INTC lock */
>      u16 shared_intr;
>      u16 invalid_intr;
> +    bool has_evtsel;
>  };
>  
>  static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned
> int reg)
> @@ -105,6 +177,172 @@ static int pruss_intc_check_write(struct
> pruss_intc *intc, unsigned int reg,
>      return 0;
>  }
>  
> +/**
> + * pruss_intc_map() - configure the PRUSS INTC
> + * @domain: pru intc domain pointer
> + * @hwirq: the system event number
> + *
> + * Configures the PRUSS INTC with the provided configuration from the one
> + * parsed in the xlate function. Any existing event to channel mappings or
> + * channel to host interrupt mappings are checked to make sure there
> are no
> + * conflicting configuration between both the PRU cores.
> + *
> + * Returns 0 on success, or a suitable error code otherwise
> + */
> +static int pruss_intc_map(struct pruss_intc_domain *domain, unsigned
> long hwirq)
> +{
> +    struct pruss_intc *intc = domain->intc;
> +    struct device* dev = intc->irqchip->parent_device;
> +    u32 val;
> +    int idx, ret;
> +    u8 evtsel, ch, host;
> +
> +    if (hwirq >= MAX_PRU_SYS_EVENTS)
> +        return -EINVAL;
> +
> +    mutex_lock(&intc->lock);
> +
> +    evtsel = domain->hwirq_data[hwirq].evtsel;
> +    ch = domain->hwirq_data[hwirq].channel;
> +    host = domain->hwirq_data[hwirq].host;
> +
> +    if (intc->has_evtsel && intc->evtsel.ref_count > 0 &&
> +        intc->evtsel.value != evtsel) {
> +        dev_err(dev, "event %lu (req. evtsel %d) already assigned to
> evtsel %d\n",
> +            hwirq, evtsel, intc->evtsel.value);
> +        ret = -EBUSY;
> +        goto unlock;
> +    }
> +
> +    /* check if sysevent already assigned */
> +    if (intc->event_channel[hwirq].ref_count > 0 &&
> +        intc->event_channel[hwirq].value != ch) {
> +        dev_err(dev, "event %lu (req. channel %d) already assigned to
> channel %d\n",
> +            hwirq, ch, intc->event_channel[hwirq].value);
> +        ret = -EBUSY;
> +        goto unlock;
> +    }
> +
> +    /* check if channel already assigned */
> +    if (intc->channel_host[ch].ref_count > 0 &&
> +        intc->channel_host[ch].value != host) {
> +        dev_err(dev, "channel %d (req. host %d) already assigned to
> host %d\n",
> +            ch, host, intc->channel_host[ch].value);
> +        ret = -EBUSY;
> +        goto unlock;
> +    }
> +
> +    if (++intc->evtsel.ref_count == 1) {
> +        intc->evtsel.value = evtsel;
> +
> +        /* TODO: need to implement CFGCHIP3[3].PRUSSEVTSEL */
> +    }
> +
> +    if (++intc->event_channel[hwirq].ref_count == 1) {
> +        intc->event_channel[hwirq].value = ch;
> +
> +        /*
> +         * configure channel map registers - each register holds map
> +         * info for 4 events, with each event occupying the lower nibble
> +         * in a register byte address in little-endian fashion
> +         */
> +        idx = hwirq / CMR_EVT_PER_REG;
> +
> +        val = pruss_intc_read_reg(intc, PRU_INTC_CMR(idx));
> +        val &= ~(CMR_EVT_MAP_MASK <<
> +                ((hwirq % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS));
> +        val |= ch << ((hwirq % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS);
> +        pruss_intc_write_reg(intc, PRU_INTC_CMR(idx), val);
> +
> +        dev_dbg(dev, "SYSEV%lu -> CH%d (CMR%d 0x%08x)\n", hwirq, ch,
> +            idx, pruss_intc_read_reg(intc, PRU_INTC_CMR(idx)));
> +
> +        /* clear and enable system event */
> +        pruss_intc_write_reg(intc, PRU_INTC_SICR, hwirq);
> +        pruss_intc_write_reg(intc, PRU_INTC_EISR, hwirq);
> +    }
> +
> +    if (++intc->channel_host[ch].ref_count == 1) {
> +        intc->channel_host[ch].value = host;
> +
> +        /*
> +         * set host map registers - each register holds map info for
> +         * 4 channels, with each channel occupying the lower nibble in
> +         * a register byte address in little-endian fashion
> +         */
> +        idx = ch / HMR_CH_PER_REG;
> +
> +        val = pruss_intc_read_reg(intc, PRU_INTC_HMR(idx));
> +        val &= ~(HMR_CH_MAP_MASK <<
> +                ((ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS));
> +        val |= host << ((ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS);
> +        pruss_intc_write_reg(intc, PRU_INTC_HMR(idx), val);
> +
> +        dev_dbg(dev, "CH%d -> HOST%d (HMR%d 0x%08x)\n", ch, host, idx,
> +            pruss_intc_read_reg(intc, PRU_INTC_HMR(idx)));
> +
> +        /* enable host interrupts */
> +        pruss_intc_write_reg(intc, PRU_INTC_HIEISR, host);
> +    }
> +
> +    dev_info(dev, "mapped system_event = %lu channel = %d host = %d
> domain = %u\n",
> +         hwirq, ch, host, domain->id);
> +
> +    /* global interrupt enable */
> +    pruss_intc_write_reg(intc, PRU_INTC_GER, 1);
> +
> +    mutex_unlock(&intc->lock);
> +    return 0;
> +
> +unlock:
> +    mutex_unlock(&intc->lock);
> +    return ret;
> +}
> +
> +/**
> + * pruss_intc_unmap() - unconfigure the PRUSS INTC
> + * @domain: pru intc domain pointer
> + * @hwirq: the system event number
> + *
> + * Undo whatever was done in pruss_intc_map() for a PRU core.
> + * Mappings are reference counted, so resources are only disabled when
> there
> + * are no longer any users.
> + */
> +static void pruss_intc_unmap(struct pruss_intc_domain *domain, unsigned
> long hwirq)
> +{
> +    struct pruss_intc *intc = domain->intc;
> +    struct device* dev = intc->irqchip->parent_device;
> +    u8 ch, host;
> +
> +    if (hwirq >= MAX_PRU_SYS_EVENTS)
> +        return;
> +
> +    mutex_lock(&intc->lock);
> +
> +    ch = intc->event_channel[hwirq].value;
> +    host = intc->channel_host[ch].value;
> +
> +    if (--intc->channel_host[ch].ref_count == 0) {
> +        /* disable host interrupts */
> +        pruss_intc_write_reg(intc, PRU_INTC_HIDISR, host);
> +    }
> +
> +    if (--intc->event_channel[hwirq].ref_count == 0) {
> +        /* disable system events */
> +        pruss_intc_write_reg(intc, PRU_INTC_EICR, hwirq);
> +        /* clear any pending status */
> +        pruss_intc_write_reg(intc, PRU_INTC_SICR, hwirq);
> +    }
> +
> +    if (intc->has_evtsel)
> +        intc->evtsel.ref_count--;
> +
> +    dev_info(dev, "unmapped system_event = %lu channel = %d host = %d\n",
> +         hwirq, ch, host);
> +
> +    mutex_unlock(&intc->lock);
> +}
> +
>  static void pruss_intc_init(struct pruss_intc *intc)
>  {
>      int i;
> @@ -198,10 +436,83 @@ static int pruss_intc_irq_set_irqchip_state(struct
> irq_data *data,
>      return pruss_intc_check_write(intc, PRU_INTC_SICR, data->hwirq);
>  }
>  
> +static int pruss_intc_irq_domain_select(struct irq_domain *d,
> +                    struct irq_fwspec *fwspec,
> +                    enum irq_domain_bus_token bus_token)
> +{
> +    struct pruss_intc_domain *domain = d->host_data;
> +    int num_cells = domain->intc->has_evtsel ? 5 : 4;
> +    u32 domain_id;
> +
> +    if (!fwspec || fwspec->fwnode != domain->domain->fwnode)
> +        return 0;
> +
> +    if (bus_token != DOMAIN_BUS_ANY && bus_token !=
> domain->domain->bus_token)
> +        return 0;
> +
> +    if (WARN_ON_ONCE(fwspec->param_count != num_cells))
> +        return 0;
> +
> +    domain_id = fwspec->param[fwspec->param_count - 1];
> +    if (domain_id != domain->id)
> +        return 0;
> +
> +    return 1;
> +}
> +
> +static int
> +pruss_intc_irq_domain_xlate(struct irq_domain *d, struct device_node
> *node,
> +                const u32 *intspec, unsigned int intsize,
> +                unsigned long *out_hwirq, unsigned int *out_type)
> +{
> +    struct pruss_intc_domain *domain = d->host_data;
> +    struct pruss_intc *intc = domain->intc;
> +    int num_cells = intc->has_evtsel ? 5 : 4;
> +    u32 sys_event, channel, host, domain_id;
> +    u32 evtsel = 0;
> +
> +    if (WARN_ON_ONCE(intsize != num_cells))
> +        return -EINVAL;
> +
> +    sys_event = intspec[0];
> +    if (sys_event >= MAX_PRU_SYS_EVENTS)
> +        return -EINVAL;
> +
> +    if (intc->has_evtsel)
> +        evtsel = intspec[1];
> +
> +    channel = intspec[intsize - 3];
> +    if (channel >= MAX_PRU_CHANNELS)
> +        return -EINVAL;
> +
> +    host = intspec[intsize - 2];
> +    if (host >= MAX_PRU_HOST_INT)
> +        return -EINVAL;
> +
> +    domain_id = intspec[intsize - 1];
> +    if (domain_id != domain->id)
> +        return -EINVAL;
> +
> +    domain->hwirq_data[sys_event].evtsel = evtsel;
> +    domain->hwirq_data[sys_event].channel = channel;
> +    domain->hwirq_data[sys_event].host = host;
> +
> +    *out_hwirq = sys_event;
> +    *out_type = IRQ_TYPE_NONE;
> +
> +    return 0;
> +}
> +
>  static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int
> virq,
>                       irq_hw_number_t hw)
>  {
> -    struct pruss_intc *intc = d->host_data;
> +    struct pruss_intc_domain *domain = d->host_data;
> +    struct pruss_intc *intc = domain->intc;
> +    int err;
> +
> +    err = pruss_intc_map(domain, hw);
> +    if (err < 0)
> +        return err;
>  
>      irq_set_chip_data(virq, intc);
>      irq_set_chip_and_handler(virq, intc->irqchip, handle_level_irq);
> @@ -211,12 +522,17 @@ static int pruss_intc_irq_domain_map(struct
> irq_domain *d, unsigned int virq,
>  
>  static void pruss_intc_irq_domain_unmap(struct irq_domain *d, unsigned
> int virq)
>  {
> +    struct pruss_intc_domain *domain = d->host_data;
> +    unsigned long hwirq = irqd_to_hwirq(irq_get_irq_data(virq));
> +
>      irq_set_chip_and_handler(virq, NULL, NULL);
>      irq_set_chip_data(virq, NULL);
> +    pruss_intc_unmap(domain, hwirq);
>  }
>  
>  static const struct irq_domain_ops pruss_intc_irq_domain_ops = {
> -    .xlate    = irq_domain_xlate_onecell,
> +    .select    = pruss_intc_irq_domain_select,
> +    .xlate    = pruss_intc_irq_domain_xlate,
>      .map    = pruss_intc_irq_domain_map,
>      .unmap    = pruss_intc_irq_domain_unmap,
>  };
> @@ -245,7 +561,8 @@ static void pruss_intc_irq_handler(struct irq_desc
> *desc)
>      hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i));
>      while (!(hipir & INTC_HIPIR_NONE_HINT)) {
>          hwirq = hipir & GENMASK(9, 0);
> -        virq = irq_linear_revmap(intc->domain, hwirq);
> +        virq = irq_linear_revmap(
> +            intc->domain[TI_PRUSS_INTC_DOMAIN_MCU].domain, hwirq);
>  
>          /*
>           * NOTE: manually ACK any system events that do not have a
> @@ -272,7 +589,8 @@ static int pruss_intc_probe(struct platform_device
> *pdev)
>      struct pruss_intc *intc;
>      struct resource *res;
>      struct irq_chip *irqchip;
> -    int i, irq, count;
> +    int i, err, irq, count;
> +    u32 num_cells;
>      u8 temp_intr[MAX_NUM_HOST_IRQS] = { 0 };
>  
>      intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL);
> @@ -323,13 +641,22 @@ static int pruss_intc_probe(struct platform_device
> *pdev)
>          }
>      }
>  
> +    err = of_property_read_u32(dev->of_node, "#interrupt-cells",
> &num_cells);
> +    if (!err && num_cells == 5)
> +        intc->has_evtsel = true;
> +
>      mutex_init(&intc->lock);
>  
> +    pm_runtime_enable(dev);
> +    pm_runtime_get_sync(dev);
> +
>      pruss_intc_init(intc);
>  
>      irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL);
> -    if (!irqchip)
> -        return -ENOMEM;
> +    if (!irqchip) {
> +        err = -ENOMEM;
> +        goto fail_alloc;
> +    }
>  
>      irqchip->irq_ack = pruss_intc_irq_ack;
>      irqchip->irq_mask = pruss_intc_irq_mask;
> @@ -338,14 +665,24 @@ static int pruss_intc_probe(struct platform_device
> *pdev)
>      irqchip->irq_release_resources = pruss_intc_irq_relres;
>      irqchip->irq_get_irqchip_state = pruss_intc_irq_get_irqchip_state;
>      irqchip->irq_set_irqchip_state = pruss_intc_irq_set_irqchip_state;
> +    irqchip->parent_device = dev;
>      irqchip->name = dev_name(dev);
>      intc->irqchip = irqchip;
>  
> -    /* always 64 events */
> -    intc->domain = irq_domain_add_linear(dev->of_node, MAX_PRU_SYS_EVENTS,
> -                         &pruss_intc_irq_domain_ops, intc);
> -    if (!intc->domain)
> -        return -ENOMEM;
> +    for (i = 0; i < NUM_TI_PRUSS_INTC_DOMAIN; i++) {
> +        intc->domain[i].intc = intc;
> +        intc->domain[i].id = i;
> +        /* always 64 events */
> +        intc->domain[i].domain = irq_domain_add_linear(dev->of_node,
> +                MAX_PRU_SYS_EVENTS, &pruss_intc_irq_domain_ops,
> +                &intc->domain[i]);
> +        if (!intc->domain[i].domain) {
> +            while (--i >= 0)
> +                irq_domain_remove(intc->domain[i].domain);
> +            err = -ENOMEM;
> +            goto fail_alloc;
> +        }
> +    }
>  
>      for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
>          irq = platform_get_irq_byname(pdev, irq_names[i]);
> @@ -356,6 +693,7 @@ static int pruss_intc_probe(struct platform_device
> *pdev)
>  
>              dev_err(dev, "platform_get_irq_byname failed for %s : %d\n",
>                  irq_names[i], irq);
> +            err = irq;
>              goto fail_irq;
>          }
>  
> @@ -372,13 +710,20 @@ static int pruss_intc_probe(struct platform_device
> *pdev)
>              irq_set_chained_handler_and_data(intc->irqs[i], NULL,
>                               NULL);
>      }
> -    irq_domain_remove(intc->domain);
> -    return irq;
> +    for (i = 0; i < NUM_TI_PRUSS_INTC_DOMAIN; i++)
> +        irq_domain_remove(intc->domain[i].domain);
> +
> +fail_alloc:
> +    pm_runtime_put(dev);
> +    pm_runtime_disable(dev);
> +
> +    return err;
>  }
>  
>  static int pruss_intc_remove(struct platform_device *pdev)
>  {
>      struct pruss_intc *intc = platform_get_drvdata(pdev);
> +    struct device *dev = &pdev->dev;
>      unsigned int hwirq;
>      int i;
>  
> @@ -388,9 +733,15 @@ static int pruss_intc_remove(struct platform_device
> *pdev)
>                               NULL);
>      }
>  
> -    for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++)
> -        irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq));
> -    irq_domain_remove(intc->domain);
> +    for (i = 0; i < NUM_TI_PRUSS_INTC_DOMAIN; i++) {
> +        for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++)
> +            irq_dispose_mapping(irq_find_mapping(
> +                        intc->domain[i].domain, hwirq));
> +        irq_domain_remove(intc->domain[i].domain);
> +    }
> +
> +    pm_runtime_put(dev);
> +    pm_runtime_disable(dev);
>  
>      return 0;
>  }
> diff --git a/include/dt-bindings/interrupt-controller/ti-pruss.h
> b/include/dt-bindings/interrupt-controller/ti-pruss.h
> new file mode 100644
> index 000000000000..326a68c31bce
> --- /dev/null
> +++ b/include/dt-bindings/interrupt-controller/ti-pruss.h
> @@ -0,0 +1,27 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
> +/*
> + * This header provides constants for the Texas Instruments Programmable
> + * Realtime Unit Subsystem (PRUSS) interrupt controller.
> + */
> +
> +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_TI_PRUSS_H
> +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_TI_PRUSS_H
> +
> +/* interrupt specifier for optional cell 1 */
> +
> +#define TI_PRUSS_INTC_EVTSEL_ANY    0xffffffff
> +
> +/* interrupt specifier for cell #interrupt-cells - 1 */
> +
> +/* host interrupt is connected to PRU cores, e.g. host events 0 and 1 */
> +#define TI_PRUSS_INTC_DOMAIN_PRU    0
> +/* host interrupt is connected to MCU's interrupt controller  */
> +#define TI_PRUSS_INTC_DOMAIN_MCU    1
> +/* host interrupt is connected to DSP's interrupt controller  */
> +#define TI_PRUSS_INTC_DOMAIN_DSP    2
> +/* host interrupt is connected to the auxillary PRU cores  */
> +#define TI_PRUSS_INTC_DOMAIN_RTU_PRU    3
> +/* host interrupt is connected to the task managers  */
> +#define TI_PRUSS_INTC_DOMAIN_TASK    4
> +
> +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_TI_PRUSS_H */

Re: [PATCH v2 4/6] irqchip/irq-pruss-intc: Add helper functions to configure internal mapping

[David Lechner]

On 8/12/19 2:39 PM, Suman Anna wrote:
> Hi David,
> 
> On 8/8/19 12:09 PM, David Lechner wrote:
>> On 8/2/19 4:26 PM, Suman Anna wrote:
>>> Point is different applications might use mapping differently as per
>>> their firmware and driver/application design and their split across one
>>> or more PRUs (design by contract). And we need to set this up at runtime
>>> when the application driver is getting run. We will have either the Soft
>>> UART or the Ethernet running at a time depending on the end goal desired
>>>
>>>> I have an idea that we can use multiple struct irq_domains to make
>>>> this work in the existing IRQ framework, but it would be helpful to
>>>> know more about the bigger picture first.
>>>
>>> Yeah, would be great if there is a way this can be solved without having
>>> to introduce additional API.
>>>
>>
>>
>> Here is what I came up with to use existing IRQ APIs to implement event
>> mapping.
>> Basically it is the same as my previous suggestion [1], with the
>> addition of
>> multiple IRQ domains.
> 
> First of all, many thanks for looking into the problem and providing
> patches for the alternate solutions. If we were to not use any exported
> functions, this approach does seem to be a viable solution. I am going
> to play around with both [1] and this patch with all our existing
> usecases and see if I run into any issues.
> 
> So, w.r.t this patch compared to [1], is the multiple IRQ domain solving
> anything specifically? Our main issue is the re-purposing of a event
> (and its mapping depending on the application), and the same issue will
> remain whether we have multiple domains or not. Also, now we would
> expect an event to migrate between different domains based on its usage.

The only thing using multiple IRQ domains gets us is that it allows us to
have multiple IRQ descriptors (virq) for a single PRU event. In other
words, if we needed to map a single system event to both a PRU core and
the MCU interrupt controller at the same time, then we would need separate
IRQ domains to do this. I we would never need to do something like this,
then we don't the IRQ domains.

Previously, you said "We can have two different applications use the same
event with different mappings." So I took this to mean that the events
would actually be mapped in hardware at the same time, but now I
understand it to just mean that a single firmware blob could contain
multiple mappings that contain the same events, but won't actually be used
at the same time. So if this is the case, then we probably don't need to
mess with IRQ domains.


> 
>>
>> The idea is that each external interrupt controller (or DMA controller,
>> etc.)
>> that is connected to the PRUSS interrupt controller is considered an
>> interrupt
>> domain. One of the objections to my previous patch was that we could
>> only have
>> one IRQ descriptor per event. Now we can have one descriptor per event per
>> domain.
>>
>> I am still proposing that we use the interrupt-cells and identical vendor
>> resource data structures in the PRU firmware be used to provide the mapping
>> information. (As a side note, I still think it is important to include
>> EVTSEL
>> on AM18xx in order to fully describe the event.)
> 
> W.r.t EVTSEL, it is a global value and applies to a range of events. I
> have another equivalent register/functionality on most of the other SoCs
> as well (a register in PRUSS_CFG space) that muxes standard events vs
> MII_RT events. Again, that is limited to only a subset of all the system
> events. So, should this continue to be a per event specifier, it will be
> yet another mapping configuration data item (my idea was to manage this
> once per application within the PRU remoteproc driver along with the
> fwspec mapping).

I guess it just seems a bit fragile to me to specify EVTSEL elsewhere. My
thinking is that the first event registered that requires a specific EVTSEL
value "wins" and if any other events are registered with a different EVTSEL
value, then we will get an error. Likewise, if all users of a specific
EVTSEL value are unmapped, then it is up for grabs for any value again.

On the other hand, with a global value as you have proposed, we can just
leave comments in the device tree and the firmware about which EVTSEL value
is required for a specific event number. We won't be able to catch mistakes
at runtime, but at least there will be something to remind us what we did
wrong. So, I suppose that is good enough.

Re: [PATCH v2 4/6] irqchip/irq-pruss-intc: Add helper functions to configure internal mapping

[Suman Anna]

Hi David,

On 8/13/19 9:26 AM, David Lechner wrote:
> On 8/12/19 2:39 PM, Suman Anna wrote:
>> Hi David,
>>
>> On 8/8/19 12:09 PM, David Lechner wrote:
>>> On 8/2/19 4:26 PM, Suman Anna wrote:
>>>> Point is different applications might use mapping differently as per
>>>> their firmware and driver/application design and their split across one
>>>> or more PRUs (design by contract). And we need to set this up at
>>>> runtime
>>>> when the application driver is getting run. We will have either the
>>>> Soft
>>>> UART or the Ethernet running at a time depending on the end goal
>>>> desired
>>>>
>>>>> I have an idea that we can use multiple struct irq_domains to make
>>>>> this work in the existing IRQ framework, but it would be helpful to
>>>>> know more about the bigger picture first.
>>>>
>>>> Yeah, would be great if there is a way this can be solved without
>>>> having
>>>> to introduce additional API.
>>>>
>>>
>>>
>>> Here is what I came up with to use existing IRQ APIs to implement event
>>> mapping.
>>> Basically it is the same as my previous suggestion [1], with the
>>> addition of
>>> multiple IRQ domains.
>>
>> First of all, many thanks for looking into the problem and providing
>> patches for the alternate solutions. If we were to not use any exported
>> functions, this approach does seem to be a viable solution. I am going
>> to play around with both [1] and this patch with all our existing
>> usecases and see if I run into any issues.
>>
>> So, w.r.t this patch compared to [1], is the multiple IRQ domain solving
>> anything specifically? Our main issue is the re-purposing of a event
>> (and its mapping depending on the application), and the same issue will
>> remain whether we have multiple domains or not. Also, now we would
>> expect an event to migrate between different domains based on its usage.
> 
> The only thing using multiple IRQ domains gets us is that it allows us to
> have multiple IRQ descriptors (virq) for a single PRU event. In other
> words, if we needed to map a single system event to both a PRU core and
> the MCU interrupt controller at the same time, then we would need separate
> IRQ domains to do this. I we would never need to do something like this,
> then we don't the IRQ domains.

Yeah, this is not a realistic usecase. A event can only be mapped to a
single channel which in turn can be mapped to only a single output
interrupt and we expect this to be processed by only a single entity
even if it may be connected to multiple processors. That is going to be
a system integration partitioning design choice. This is where the
irqs-shared and irqs-reserved logic comes in, so that MPU doesn't deal
with that interrupt line if it is expected to be handled by a different
processor.

> 
> Previously, you said "We can have two different applications use the same
> event with different mappings." So I took this to mean that the events
> would actually be mapped in hardware at the same time, but now I
> understand it to just mean that a single firmware blob could contain
> multiple mappings that contain the same events, but won't actually be used
> at the same time. So if this is the case, then we probably don't need to
> mess with IRQ domains.

The different applications (like PRU Dual-EMAC or PRU Soft UART I
mentioned earlier) will indeed be running at separate times, PRU cores
are a very limited resource, so it is treated as an exclusive resource.
The INTC is expected to be programmed as per the application running at
a given time. We also expect the firmware blob to change as per the
application.

> 
> 
>>
>>>
>>> The idea is that each external interrupt controller (or DMA controller,
>>> etc.)
>>> that is connected to the PRUSS interrupt controller is considered an
>>> interrupt
>>> domain. One of the objections to my previous patch was that we could
>>> only have
>>> one IRQ descriptor per event. Now we can have one descriptor per
>>> event per
>>> domain.
>>>
>>> I am still proposing that we use the interrupt-cells and identical
>>> vendor
>>> resource data structures in the PRU firmware be used to provide the
>>> mapping
>>> information. (As a side note, I still think it is important to include
>>> EVTSEL
>>> on AM18xx in order to fully describe the event.)
>>
>> W.r.t EVTSEL, it is a global value and applies to a range of events. I
>> have another equivalent register/functionality on most of the other SoCs
>> as well (a register in PRUSS_CFG space) that muxes standard events vs
>> MII_RT events. Again, that is limited to only a subset of all the system
>> events. So, should this continue to be a per event specifier, it will be
>> yet another mapping configuration data item (my idea was to manage this
>> once per application within the PRU remoteproc driver along with the
>> fwspec mapping).
> 
> I guess it just seems a bit fragile to me to specify EVTSEL elsewhere. My
> thinking is that the first event registered that requires a specific EVTSEL
> value "wins" and if any other events are registered with a different EVTSEL
> value, then we will get an error. Likewise, if all users of a specific
> EVTSEL value are unmapped, then it is up for grabs for any value again.

We usually expect an application to have possibly multiple events, and
so all of them are expected to match if it is using multiple events
within the range controlled by EVTSEL or the CFG register. It only needs
to be programmed once if the application needs it. The first one to win
introduces ordering issues in general. Anyway, for this solution to work
in general, I am expecting the irq_create_fwspec_mapping()s to be per
application, and they should be overwriting any previous configured values.

> 
> On the other hand, with a global value as you have proposed, we can just
> leave comments in the device tree and the firmware about which EVTSEL value
> is required for a specific event number. We won't be able to catch mistakes
> at runtime, but at least there will be something to remind us what we did
> wrong. So, I suppose that is good enough.

With the global value, I expect it to be a property of the client node
alongside interrupts. The management and selection of this will be left
to the PRU remoteproc driver. Encoding this on the firmware-side per
event also seems a waste of memory. End of the day, it is going to be
design contract with the application and firmware.

regards
Suman

[PATCH v2 5/6] irqchip/irq-pruss-intc: Implement irq_{get,set}_irqchip_state ops

[Suman Anna]

From: David Lechner <david@lechnology.com>

This implements the irq_get_irqchip_state and irq_set_irqchip_state
callbacks for the TI PRUSS INTC driver. The set callback can be used
by drivers to "kick" a PRU by enabling a PRU system event.

Example:
     irq_set_irqchip_state(irq, IRQCHIP_STATE_PENDING, true);

Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2: New patch from David replacing an exported API from v1,
    https://patchwork.kernel.org/patch/11034565/

 drivers/irqchip/irq-pruss-intc.c | 41 ++++++++++++++++++++++++++++++--
 1 file changed, 39 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c
index 63cfc665be1e..59e26dfbb179 100644
--- a/drivers/irqchip/irq-pruss-intc.c
+++ b/drivers/irqchip/irq-pruss-intc.c
@@ -7,6 +7,7 @@
  *	Suman Anna <s-anna@ti.com>
  */
 
+#include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/irqchip/chained_irq.h>
 #include <linux/irqchip/irq-pruss-intc.h>
@@ -40,8 +41,7 @@
 #define PRU_INTC_HIEISR		0x0034
 #define PRU_INTC_HIDISR		0x0038
 #define PRU_INTC_GPIR		0x0080
-#define PRU_INTC_SRSR0		0x0200
-#define PRU_INTC_SRSR1		0x0204
+#define PRU_INTC_SRSR(x)	(0x0200 + (x) * 4)
 #define PRU_INTC_SECR0		0x0280
 #define PRU_INTC_SECR1		0x0284
 #define PRU_INTC_ESR0		0x0300
@@ -439,6 +439,41 @@ static void pruss_intc_irq_relres(struct irq_data *data)
 	module_put(THIS_MODULE);
 }
 
+static int pruss_intc_irq_get_irqchip_state(struct irq_data *data,
+					    enum irqchip_irq_state which,
+					    bool *state)
+{
+	struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
+	u32 reg, mask, srsr;
+
+	if (which != IRQCHIP_STATE_PENDING)
+		return -EINVAL;
+
+	reg = PRU_INTC_SRSR(data->hwirq / 32);
+	mask = BIT(data->hwirq % 32);
+
+	srsr = pruss_intc_read_reg(intc, reg);
+
+	*state = !!(srsr & mask);
+
+	return 0;
+}
+
+static int pruss_intc_irq_set_irqchip_state(struct irq_data *data,
+					    enum irqchip_irq_state which,
+					    bool state)
+{
+	struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
+
+	if (which != IRQCHIP_STATE_PENDING)
+		return -EINVAL;
+
+	if (state)
+		return pruss_intc_check_write(intc, PRU_INTC_SISR, data->hwirq);
+
+	return pruss_intc_check_write(intc, PRU_INTC_SICR, data->hwirq);
+}
+
 static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int virq,
 				     irq_hw_number_t hw)
 {
@@ -583,6 +618,8 @@ static int pruss_intc_probe(struct platform_device *pdev)
 	irqchip->irq_unmask = pruss_intc_irq_unmask;
 	irqchip->irq_request_resources = pruss_intc_irq_reqres;
 	irqchip->irq_release_resources = pruss_intc_irq_relres;
+	irqchip->irq_get_irqchip_state = pruss_intc_irq_get_irqchip_state;
+	irqchip->irq_set_irqchip_state = pruss_intc_irq_set_irqchip_state;
 	irqchip->name = dev_name(dev);
 	intc->irqchip = irqchip;
 
-- 
2.22.0

[PATCH v2 6/6] irqchip/irq-pruss-intc: Add support for ICSSG INTC on K3 SoCs

[Suman Anna]

The K3 AM65x and J721E SoCs have the next generation of the PRU-ICSS IP,
commonly called ICSSG. The PRUSS INTC present within the ICSSG supports
more System Events (160 vs 64), more Interrupt Channels and Host Interrupts
(20 vs 10) compared to the previous generation PRUSS INTC instances. The
first 2 and the last 10 of these host interrupt lines are used by the
PRU and other auxiliary cores and sub-modules within the ICSSG, with 8
host interrupts connected to MPU. The host interrupts 5, 6, 7 are also
connected to the other ICSSG instances within the SoC and can be
partitioned as per system integration through the board dts files.

Enhance the PRUSS INTC driver to add support for this ICSSG INTC
instance. This support is added using specific compatible and match
data and updating the code to use this data instead of the current
hard-coded macros. The INTC config structure is updated to use the
higher events and channels on all SoCs, while limiting the actual
processing to only the relevant number of events/channels/interrupts.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2:
 - Rebased patch with indexed macros like ESRx, ECRx where x = 0,1 dropped
v1: https://patchwork.kernel.org/patch/11034543/

 drivers/irqchip/Kconfig                |   2 +-
 drivers/irqchip/irq-pruss-intc.c       | 181 +++++++++++++++++--------
 include/linux/irqchip/irq-pruss-intc.h |   4 +-
 3 files changed, 126 insertions(+), 61 deletions(-)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index dc6b5aa77a5d..a98bfec6b364 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -473,7 +473,7 @@ config TI_SCI_INTA_IRQCHIP
 
 config TI_PRUSS_INTC
 	tristate "TI PRU-ICSS Interrupt Controller"
-	depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM437X || SOC_DRA7XX || ARCH_KEYSTONE
+	depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM437X || SOC_DRA7XX || ARCH_KEYSTONE || ARCH_K3
 	select IRQ_DOMAIN
 	help
 	   This enables support for the PRU-ICSS Local Interrupt Controller
diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c
index 59e26dfbb179..891a14b6c399 100644
--- a/drivers/irqchip/irq-pruss-intc.c
+++ b/drivers/irqchip/irq-pruss-intc.c
@@ -7,6 +7,7 @@
  *	Suman Anna <s-anna@ti.com>
  */
 
+#include <linux/bitmap.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/irqchip/chained_irq.h>
@@ -26,9 +27,6 @@
 /* minimum starting host interrupt number for MPU */
 #define MIN_PRU_HOST_INT	2
 
-/* maximum number of host interrupts */
-#define MAX_PRU_HOST_INT	10
-
 /* PRU_ICSS_INTC registers */
 #define PRU_INTC_REVID		0x0000
 #define PRU_INTC_CR		0x0004
@@ -42,19 +40,14 @@
 #define PRU_INTC_HIDISR		0x0038
 #define PRU_INTC_GPIR		0x0080
 #define PRU_INTC_SRSR(x)	(0x0200 + (x) * 4)
-#define PRU_INTC_SECR0		0x0280
-#define PRU_INTC_SECR1		0x0284
-#define PRU_INTC_ESR0		0x0300
-#define PRU_INTC_ESR1		0x0304
-#define PRU_INTC_ECR0		0x0380
-#define PRU_INTC_ECR1		0x0384
+#define PRU_INTC_SECR(x)	(0x0280 + (x) * 4)
+#define PRU_INTC_ESR(x)		(0x0300 + (x) * 4)
+#define PRU_INTC_ECR(x)		(0x0380 + (x) * 4)
 #define PRU_INTC_CMR(x)		(0x0400 + (x) * 4)
 #define PRU_INTC_HMR(x)		(0x0800 + (x) * 4)
 #define PRU_INTC_HIPIR(x)	(0x0900 + (x) * 4)
-#define PRU_INTC_SIPR0		0x0d00
-#define PRU_INTC_SIPR1		0x0d04
-#define PRU_INTC_SITR0		0x0d80
-#define PRU_INTC_SITR1		0x0d84
+#define PRU_INTC_SIPR(x)	(0x0d00 + (x) * 4)
+#define PRU_INTC_SITR(x)	(0x0d80 + (x) * 4)
 #define PRU_INTC_HINLR(x)	(0x1100 + (x) * 4)
 #define PRU_INTC_HIER		0x1500
 
@@ -71,12 +64,23 @@
 /* HIPIR register bit-fields */
 #define INTC_HIPIR_NONE_HINT	0x80000000
 
+/**
+ * struct pruss_intc_match_data - match data to handle SoC variations
+ * @num_system_events: number of input system events handled by the PRUSS INTC
+ * @num_host_intrs: number of host interrupts supported by the PRUSS INTC
+ */
+struct pruss_intc_match_data {
+	u8 num_system_events;
+	u8 num_host_intrs;
+};
+
 /**
  * struct pruss_intc - PRUSS interrupt controller structure
  * @irqs: kernel irq numbers corresponding to PRUSS host interrupts
  * @base: base virtual address of INTC register space
  * @irqchip: irq chip for this interrupt controller
  * @domain: irq domain for this interrupt controller
+ * @data: cached PRUSS INTC IP configuration data
  * @config_map: stored INTC configuration mapping data
  * @lock: mutex to serialize access to INTC
  * @host_mask: indicate which HOST IRQs are enabled
@@ -88,6 +92,7 @@ struct pruss_intc {
 	void __iomem *base;
 	struct irq_chip *irqchip;
 	struct irq_domain *domain;
+	const struct pruss_intc_match_data *data;
 	struct pruss_intc_config config_map;
 	struct mutex lock; /* PRUSS INTC lock */
 	u32 host_mask;
@@ -112,7 +117,7 @@ static int pruss_intc_check_write(struct pruss_intc *intc, unsigned int reg,
 	if (!intc)
 		return -EINVAL;
 
-	if (sysevent >= MAX_PRU_SYS_EVENTS)
+	if (sysevent >= intc->data->num_system_events)
 		return -EINVAL;
 
 	pruss_intc_write_reg(intc, reg, sysevent);
@@ -191,16 +196,28 @@ int pruss_intc_configure(struct device *dev,
 			 struct pruss_intc_config *intc_config)
 {
 	struct pruss_intc *intc;
-	int i, idx, ret;
+	int i, idx;
 	s8 ch, host;
-	u64 sysevt_mask = 0;
+	u32 num_events, num_intrs, num_regs;
+	unsigned long *sysevt_bitmap;
+	u32 *sysevts;
 	u32 ch_mask = 0;
 	u32 host_mask = 0;
+	int ret = 0;
 
 	intc = to_pruss_intc(dev);
 	if (IS_ERR(intc))
 		return PTR_ERR(intc);
 
+	num_events = intc->data->num_system_events;
+	num_intrs = intc->data->num_host_intrs;
+	num_regs = DIV_ROUND_UP(num_events, 32);
+
+	sysevt_bitmap = bitmap_zalloc(num_events, GFP_KERNEL);
+	if (!sysevt_bitmap)
+		return -ENOMEM;
+	sysevts = (u32 *)sysevt_bitmap;
+
 	mutex_lock(&intc->lock);
 
 	/*
@@ -208,7 +225,7 @@ int pruss_intc_configure(struct device *dev,
 	 * for 4 events, with each event occupying the lower nibble in
 	 * a register byte address in little-endian fashion
 	 */
-	for (i = 0; i < ARRAY_SIZE(intc_config->sysev_to_ch); i++) {
+	for (i = 0; i < num_events; i++) {
 		ch = intc_config->sysev_to_ch[i];
 		if (ch < 0)
 			continue;
@@ -223,7 +240,7 @@ int pruss_intc_configure(struct device *dev,
 
 		intc->config_map.sysev_to_ch[i] = ch;
 		pruss_intc_update_cmr(intc, i, ch);
-		sysevt_mask |= BIT_ULL(i);
+		bitmap_set(sysevt_bitmap, i, 1);
 		ch_mask |= BIT(ch);
 		idx = i / CMR_EVT_PER_REG;
 
@@ -236,7 +253,7 @@ int pruss_intc_configure(struct device *dev,
 	 * 4 channels, with each channel occupying the lower nibble in
 	 * a register byte address in little-endian fashion
 	 */
-	for (i = 0; i < ARRAY_SIZE(intc_config->ch_to_host); i++) {
+	for (i = 0; i < num_intrs; i++) {
 		host = intc_config->ch_to_host[i];
 		if (host < 0)
 			continue;
@@ -267,17 +284,19 @@ int pruss_intc_configure(struct device *dev,
 			pruss_intc_read_reg(intc, PRU_INTC_HMR(idx)));
 	}
 
-	dev_info(dev, "configured system_events = 0x%016llx intr_channels = 0x%08x host_intr = 0x%08x\n",
-		 sysevt_mask, ch_mask, host_mask);
+	dev_info(dev, "configured system_events[%d-0] = %*pb\n",
+		 num_events - 1, num_events, sysevt_bitmap);
+	dev_info(dev, "configured intr_channels = 0x%08x host_intr = 0x%08x\n",
+		 ch_mask, host_mask);
 
 	/* enable system events, writing 0 has no-effect */
-	pruss_intc_write_reg(intc, PRU_INTC_ESR0, lower_32_bits(sysevt_mask));
-	pruss_intc_write_reg(intc, PRU_INTC_SECR0, lower_32_bits(sysevt_mask));
-	pruss_intc_write_reg(intc, PRU_INTC_ESR1, upper_32_bits(sysevt_mask));
-	pruss_intc_write_reg(intc, PRU_INTC_SECR1, upper_32_bits(sysevt_mask));
+	for (i = 0; i < num_regs; i++) {
+		pruss_intc_write_reg(intc, PRU_INTC_ESR(i), sysevts[i]);
+		pruss_intc_write_reg(intc, PRU_INTC_SECR(i), sysevts[i]);
+	}
 
 	/* enable host interrupts */
-	for (i = 0; i < MAX_PRU_HOST_INT; i++) {
+	for (i = 0; i < num_intrs; i++) {
 		if (host_mask & BIT(i))
 			pruss_intc_write_reg(intc, PRU_INTC_HIEISR, i);
 	}
@@ -286,9 +305,7 @@ int pruss_intc_configure(struct device *dev,
 	pruss_intc_write_reg(intc, PRU_INTC_GER, 1);
 
 	intc->host_mask |= host_mask;
-
-	mutex_unlock(&intc->lock);
-	return 0;
+	goto out;
 
 fail_ch:
 	while (--i >= 0) {
@@ -297,7 +314,7 @@ int pruss_intc_configure(struct device *dev,
 			pruss_intc_update_hmr(intc, i, 0);
 		}
 	}
-	i = ARRAY_SIZE(intc_config->sysev_to_ch);
+	i = num_events;
 fail_evt:
 	while (--i >= 0) {
 		if (intc_config->sysev_to_ch[i] >= 0) {
@@ -305,7 +322,9 @@ int pruss_intc_configure(struct device *dev,
 			pruss_intc_update_cmr(intc, i, 0);
 		}
 	}
+out:
 	mutex_unlock(&intc->lock);
+	bitmap_free(sysevt_bitmap);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(pruss_intc_configure);
@@ -325,28 +344,39 @@ int pruss_intc_unconfigure(struct device *dev,
 	struct pruss_intc *intc;
 	int i;
 	s8 ch, host;
-	u64 sysevt_mask = 0;
+	u32 num_events, num_intrs, num_regs;
+	unsigned long *sysevt_bitmap;
+	u32 *sysevts;
 	u32 host_mask = 0;
 
 	intc = to_pruss_intc(dev);
 	if (IS_ERR(intc))
 		return PTR_ERR(intc);
 
+	num_events = intc->data->num_system_events;
+	num_intrs = intc->data->num_host_intrs;
+	num_regs = DIV_ROUND_UP(num_events, 32);
+
+	sysevt_bitmap = bitmap_zalloc(num_events, GFP_KERNEL);
+	if (!sysevt_bitmap)
+		return -ENOMEM;
+	sysevts = (u32 *)sysevt_bitmap;
+
 	mutex_lock(&intc->lock);
 
-	for (i = 0; i < ARRAY_SIZE(intc_config->sysev_to_ch); i++) {
+	for (i = 0; i < num_events; i++) {
 		ch = intc_config->sysev_to_ch[i];
 		if (ch < 0)
 			continue;
 
 		/* mark sysevent free in global map */
 		intc->config_map.sysev_to_ch[i] = PRU_INTC_FREE;
-		sysevt_mask |= BIT_ULL(i);
+		bitmap_set(sysevt_bitmap, i, 1);
 		/* clear the map using reset value 0 */
 		pruss_intc_update_cmr(intc, i, 0);
 	}
 
-	for (i = 0; i < ARRAY_SIZE(intc_config->ch_to_host); i++) {
+	for (i = 0; i < num_intrs; i++) {
 		host = intc_config->ch_to_host[i];
 		if (host < 0)
 			continue;
@@ -358,24 +388,26 @@ int pruss_intc_unconfigure(struct device *dev,
 		pruss_intc_update_hmr(intc, i, 0);
 	}
 
-	dev_info(dev, "unconfigured system_events = 0x%016llx host_intr = 0x%08x\n",
-		 sysevt_mask, host_mask);
+	dev_info(dev, "unconfigured system_events[%d-0] = %*pb\n",
+		 num_events - 1, num_events, sysevt_bitmap);
+	dev_info(dev, "unconfigured host_intr = 0x%08x\n", host_mask);
 
-	/* disable system events, writing 0 has no-effect */
-	pruss_intc_write_reg(intc, PRU_INTC_ECR0, lower_32_bits(sysevt_mask));
-	pruss_intc_write_reg(intc, PRU_INTC_ECR1, upper_32_bits(sysevt_mask));
-	/* clear any pending status */
-	pruss_intc_write_reg(intc, PRU_INTC_SECR0, lower_32_bits(sysevt_mask));
-	pruss_intc_write_reg(intc, PRU_INTC_SECR1, upper_32_bits(sysevt_mask));
+	for (i = 0; i < num_regs; i++) {
+		/* disable system events, writing 0 has no-effect */
+		pruss_intc_write_reg(intc, PRU_INTC_ECR(i), sysevts[i]);
+		/* clear any pending status */
+		pruss_intc_write_reg(intc, PRU_INTC_SECR(i), sysevts[i]);
+	}
 
 	/* disable host interrupts */
-	for (i = 0; i < MAX_PRU_HOST_INT; i++) {
+	for (i = 0; i < num_intrs; i++) {
 		if (host_mask & BIT(i))
 			pruss_intc_write_reg(intc, PRU_INTC_HIDISR, i);
 	}
 
 	intc->host_mask &= ~host_mask;
 	mutex_unlock(&intc->lock);
+	bitmap_free(sysevt_bitmap);
 
 	return 0;
 }
@@ -384,21 +416,28 @@ EXPORT_SYMBOL_GPL(pruss_intc_unconfigure);
 static void pruss_intc_init(struct pruss_intc *intc)
 {
 	int i;
+	int num_chnl_map_regs = DIV_ROUND_UP(intc->data->num_system_events,
+					     CMR_EVT_PER_REG);
+	int num_host_intr_regs = DIV_ROUND_UP(intc->data->num_host_intrs,
+					      HMR_CH_PER_REG);
+	int num_event_type_regs =
+			DIV_ROUND_UP(intc->data->num_system_events, 32);
 
-	/* configure polarity to active high for all system interrupts */
-	pruss_intc_write_reg(intc, PRU_INTC_SIPR0, 0xffffffff);
-	pruss_intc_write_reg(intc, PRU_INTC_SIPR1, 0xffffffff);
-
-	/* configure type to pulse interrupt for all system interrupts */
-	pruss_intc_write_reg(intc, PRU_INTC_SITR0, 0);
-	pruss_intc_write_reg(intc, PRU_INTC_SITR1, 0);
+	/*
+	 * configure polarity (SIPR register) to active high and
+	 * type (SITR register) to pulse interrupt for all system events
+	 */
+	for (i = 0; i < num_event_type_regs; i++) {
+		pruss_intc_write_reg(intc, PRU_INTC_SIPR(i), 0xffffffff);
+		pruss_intc_write_reg(intc, PRU_INTC_SITR(i), 0);
+	}
 
-	/* clear all 16 interrupt channel map registers */
-	for (i = 0; i < 16; i++)
+	/* clear all interrupt channel map registers, 4 events per register */
+	for (i = 0; i < num_chnl_map_regs; i++)
 		pruss_intc_write_reg(intc, PRU_INTC_CMR(i), 0);
 
-	/* clear all 3 host interrupt map registers */
-	for (i = 0; i < 3; i++)
+	/* clear all host interrupt map registers, 4 channels per register */
+	for (i = 0; i < num_host_intr_regs; i++)
 		pruss_intc_write_reg(intc, PRU_INTC_HMR(i), 0);
 }
 
@@ -549,11 +588,20 @@ static int pruss_intc_probe(struct platform_device *pdev)
 	struct resource *res;
 	struct irq_chip *irqchip;
 	int i, irq, count;
+	const struct pruss_intc_match_data *data;
 	u8 temp_intr[MAX_NUM_HOST_IRQS] = { 0 };
+	u8 max_system_events;
+
+	data = of_device_get_match_data(dev);
+	if (!data)
+		return -ENODEV;
+
+	max_system_events = data->num_system_events;
 
 	intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL);
 	if (!intc)
 		return -ENOMEM;
+	intc->data = data;
 	platform_set_drvdata(pdev, intc);
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -623,8 +671,7 @@ static int pruss_intc_probe(struct platform_device *pdev)
 	irqchip->name = dev_name(dev);
 	intc->irqchip = irqchip;
 
-	/* always 64 events */
-	intc->domain = irq_domain_add_linear(dev->of_node, MAX_PRU_SYS_EVENTS,
+	intc->domain = irq_domain_add_linear(dev->of_node, max_system_events,
 					     &pruss_intc_irq_domain_ops, intc);
 	if (!intc->domain)
 		return -ENOMEM;
@@ -661,6 +708,7 @@ static int pruss_intc_probe(struct platform_device *pdev)
 static int pruss_intc_remove(struct platform_device *pdev)
 {
 	struct pruss_intc *intc = platform_get_drvdata(pdev);
+	u8 max_system_events = intc->data->num_system_events;
 	unsigned int hwirq;
 	int i;
 
@@ -670,15 +718,32 @@ static int pruss_intc_remove(struct platform_device *pdev)
 							 NULL);
 	}
 
-	for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++)
+	for (hwirq = 0; hwirq < max_system_events; hwirq++)
 		irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq));
 	irq_domain_remove(intc->domain);
 
 	return 0;
 }
 
+static const struct pruss_intc_match_data pruss_intc_data = {
+	.num_system_events = 64,
+	.num_host_intrs = 10,
+};
+
+static const struct pruss_intc_match_data icssg_intc_data = {
+	.num_system_events = 160,
+	.num_host_intrs = 20,
+};
+
 static const struct of_device_id pruss_intc_of_match[] = {
-	{ .compatible = "ti,pruss-intc", },
+	{
+		.compatible = "ti,pruss-intc",
+		.data = &pruss_intc_data,
+	},
+	{
+		.compatible = "ti,icssg-intc",
+		.data = &icssg_intc_data,
+	},
 	{ /* sentinel */ },
 };
 MODULE_DEVICE_TABLE(of, pruss_intc_of_match);
diff --git a/include/linux/irqchip/irq-pruss-intc.h b/include/linux/irqchip/irq-pruss-intc.h
index daffc048b303..cc6f9190b04f 100644
--- a/include/linux/irqchip/irq-pruss-intc.h
+++ b/include/linux/irqchip/irq-pruss-intc.h
@@ -10,10 +10,10 @@
 #define __LINUX_IRQ_PRUSS_INTC_H
 
 /* maximum number of system events */
-#define MAX_PRU_SYS_EVENTS	64
+#define MAX_PRU_SYS_EVENTS	160
 
 /* maximum number of interrupt channels */
-#define MAX_PRU_CHANNELS	10
+#define MAX_PRU_CHANNELS	20
 
 /* use -1 to mark unassigned events and channels */
 #define PRU_INTC_FREE		-1
-- 
2.22.0