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Fri, 2 Aug 2019 07:48:37 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K CC: Daniel Lezcano , Thomas Gleixner , Atish Patra , Alistair Francis , Damien Le Moal , Christoph Hellwig , Anup Patel , "kvm@vger.kernel.org" , "linux-riscv@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Anup Patel Subject: [RFC PATCH v2 16/19] RISC-V: KVM: Implement ONE REG interface for FP registers Thread-Topic: [RFC PATCH v2 16/19] RISC-V: KVM: Implement ONE REG interface for FP registers Thread-Index: AQHVSQaxU3hbnoBay0C9NeTjhAbblg== Date: Fri, 2 Aug 2019 07:48:37 +0000 Message-ID: <20190802074620.115029-17-anup.patel@wdc.com> References: <20190802074620.115029-1-anup.patel@wdc.com> In-Reply-To: <20190802074620.115029-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: PN1PR01CA0111.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00::27) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; 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x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: k13uP7ovOs6+WH1iUwAGYBVfmwJ9V5TL53h6ch09JaGjUhMB8bTM9YN4/M/67FdO1m5Kx2JuOlhm9/GQxhbQ9g3ssL1I80BMyGdLC6/Be1Ow8xYCus0p1DscyScVbJ03IT3pMjicErRZtWfjNdFie54ruHH1kwWIB3J184hP5rj0ZaMRdB3H7Fh1Mw+j/TvRj86f6OxXXe9AFKUv0b3uAdX47vALOCNVR6azY3bDR0fLejmvma5CaT0ZELtByXZTJefQV+7Oon66ivKTaLjvr+NwvzxtgN6LCO5z7V27Yji6JTZ49HSsG3ShKfz6IgefVC+BPDmHaqIOy6pY8smCYU/VzIMOx01HiDzb8g43ExolOuSLhi2aETflS+wqFNBvgZJhEzz4OuyLIl8SwmN8J0GqLUCCaL0pE5w/lWhPH1k= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 81529680-71c2-44e2-9160-08d7171dd3a0 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Aug 2019 07:48:37.0629 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Anup.Patel@wdc.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB5566 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Atish Patra Add a KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctl interface for floating point registers such as F0-F31 and FCSR. This support is added for both 'F' and 'D' extensions. Signed-off-by: Atish Patra Signed-off-by: Anup Patel --- arch/riscv/include/uapi/asm/kvm.h | 10 +++ arch/riscv/kvm/vcpu.c | 100 ++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index 024f220eb17e..c9f03363bb28 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -83,6 +83,16 @@ struct kvm_sregs { #define KVM_REG_RISCV_CSR_REG(name) \ (offsetof(struct kvm_sregs, name) / sizeof(unsigned long)) =20 +/* F extension registers are mapped as type4 */ +#define KVM_REG_RISCV_FP_F (0x04 << KVM_REG_RISCV_TYPE_SHIFT) +#define KVM_REG_RISCV_FP_F_REG(name) \ + (offsetof(struct __riscv_f_ext_state, name) / sizeof(u32)) + +/* D extension registers are mapped as type 5 */ +#define KVM_REG_RISCV_FP_D (0x05 << KVM_REG_RISCV_TYPE_SHIFT) +#define KVM_REG_RISCV_FP_D_REG(name) \ + (offsetof(struct __riscv_d_ext_state, name) / sizeof(u64)) + #endif =20 #endif /* __LINUX_KVM_RISCV_H */ diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 995ee27e9b8a..bd79790c5438 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -423,6 +423,94 @@ static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu = *vcpu, return 0; } =20 +static int kvm_riscv_vcpu_get_reg_fp(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype) +{ + struct kvm_cpu_context *cntx =3D &vcpu->arch.guest_context; + unsigned long isa =3D vcpu->arch.isa; + unsigned long __user *uaddr =3D + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num =3D reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + rtype); + void *reg_val; + + if ((rtype =3D=3D KVM_REG_RISCV_FP_F) && (isa & RISCV_ISA_EXT_f)) { + if (KVM_REG_SIZE(reg->id) !=3D sizeof(u32)) + return -EINVAL; + if (reg_num =3D=3D KVM_REG_RISCV_FP_F_REG(fcsr)) + reg_val =3D &cntx->fp.f.fcsr; + else if ((KVM_REG_RISCV_FP_F_REG(f[0]) <=3D reg_num) && + reg_num <=3D KVM_REG_RISCV_FP_F_REG(f[31])) + reg_val =3D &cntx->fp.f.f[reg_num]; + else + return -EINVAL; + } else if ((rtype =3D=3D KVM_REG_RISCV_FP_D) && (isa & RISCV_ISA_EXT_d)) = { + if (reg_num =3D=3D KVM_REG_RISCV_FP_D_REG(fcsr)) { + if (KVM_REG_SIZE(reg->id) !=3D sizeof(u32)) + return -EINVAL; + reg_val =3D &cntx->fp.d.fcsr; + } else if ((KVM_REG_RISCV_FP_D_REG(f[0]) <=3D reg_num) && + reg_num <=3D KVM_REG_RISCV_FP_D_REG(f[31])) { + if (KVM_REG_SIZE(reg->id) !=3D sizeof(u64)) + return -EINVAL; + reg_val =3D &cntx->fp.d.f[reg_num]; + } else + return -EINVAL; + } else + return -EINVAL; + + if (copy_to_user(uaddr, reg_val, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + return 0; +} + +static int kvm_riscv_vcpu_set_reg_fp(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype) +{ + struct kvm_cpu_context *cntx =3D &vcpu->arch.guest_context; + unsigned long isa =3D vcpu->arch.isa; + unsigned long __user *uaddr =3D + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num =3D reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + rtype); + void *reg_val; + + if ((rtype =3D=3D KVM_REG_RISCV_FP_F) && (isa & RISCV_ISA_EXT_f)) { + if (KVM_REG_SIZE(reg->id) !=3D sizeof(u32)) + return -EINVAL; + if (reg_num =3D=3D KVM_REG_RISCV_FP_F_REG(fcsr)) + reg_val =3D &cntx->fp.f.fcsr; + else if ((KVM_REG_RISCV_FP_F_REG(f[0]) <=3D reg_num) && + reg_num <=3D KVM_REG_RISCV_FP_F_REG(f[31])) + reg_val =3D &cntx->fp.f.f[reg_num]; + else + return -EINVAL; + } else if ((rtype =3D=3D KVM_REG_RISCV_FP_D) && (isa & RISCV_ISA_EXT_d)) = { + if (reg_num =3D=3D KVM_REG_RISCV_FP_D_REG(fcsr)) { + if (KVM_REG_SIZE(reg->id) !=3D sizeof(u32)) + return -EINVAL; + reg_val =3D &cntx->fp.d.fcsr; + } else if ((KVM_REG_RISCV_FP_D_REG(f[0]) <=3D reg_num) && + reg_num <=3D KVM_REG_RISCV_FP_D_REG(f[31])) { + if (KVM_REG_SIZE(reg->id) !=3D sizeof(u64)) + return -EINVAL; + reg_val =3D &cntx->fp.d.f[reg_num]; + } else + return -EINVAL; + } else + return -EINVAL; + + if (copy_from_user(reg_val, uaddr, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + return 0; +} + static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) { @@ -432,6 +520,12 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcp= u, return kvm_riscv_vcpu_set_reg_core(vcpu, reg); else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_CSR) return kvm_riscv_vcpu_set_reg_csr(vcpu, reg); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_FP_F) + return kvm_riscv_vcpu_set_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_F); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_FP_D) + return kvm_riscv_vcpu_set_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_D); =20 return -EINVAL; } @@ -445,6 +539,12 @@ static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcp= u, return kvm_riscv_vcpu_get_reg_core(vcpu, reg); else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_CSR) return kvm_riscv_vcpu_get_reg_csr(vcpu, reg); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_FP_F) + return kvm_riscv_vcpu_get_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_F); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_FP_D) + return kvm_riscv_vcpu_get_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_D); =20 return -EINVAL; } --=20 2.17.1