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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: e630e2b5-4145-4c8d-62ab-08d71bfa6667 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Aug 2019 12:17:37.2198 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: phemadri@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB3230 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:5.22.84,1.0.8 definitions=2019-08-08_06:2019-08-07,2019-08-08 signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds support to allocate CNN55XX device AQMQ command queues required for submitting asymmetric crypto requests. Signed-off-by: Phani Kiran Hemadri Reviewed-by: Srikanth Jampala --- drivers/crypto/cavium/nitrox/nitrox_dev.h | 4 ++ drivers/crypto/cavium/nitrox/nitrox_lib.c | 66 ++++++++++++++++++++++- drivers/crypto/cavium/nitrox/nitrox_req.h | 30 +++++++++++ 3 files changed, 99 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/cavium/nitrox/nitrox_dev.h b/drivers/crypto/cav= ium/nitrox/nitrox_dev.h index 5ee98eca728c..2217a2736c8e 100644 --- a/drivers/crypto/cavium/nitrox/nitrox_dev.h +++ b/drivers/crypto/cavium/nitrox/nitrox_dev.h @@ -10,6 +10,8 @@ #define VERSION_LEN 32 /* Maximum queues in PF mode */ #define MAX_PF_QUEUES 64 +/* Maximum device queues */ +#define MAX_DEV_QUEUES (MAX_PF_QUEUES) /* Maximum UCD Blocks */ #define CNN55XX_MAX_UCD_BLOCKS 8 =20 @@ -208,6 +210,7 @@ enum vf_mode { * @mode: Device mode PF/VF * @ctx_pool: DMA pool for crypto context * @pkt_inq: Packet input rings + * @aqmq: AQM command queues * @qvec: MSI-X queue vectors information * @iov: SR-IOV informatin * @num_vecs: number of MSI-X vectors @@ -234,6 +237,7 @@ struct nitrox_device { =20 struct dma_pool *ctx_pool; struct nitrox_cmdq *pkt_inq; + struct nitrox_cmdq *aqmq[MAX_DEV_QUEUES] ____cacheline_aligned_in_smp; =20 struct nitrox_q_vector *qvec; struct nitrox_iov iov; diff --git a/drivers/crypto/cavium/nitrox/nitrox_lib.c b/drivers/crypto/cav= ium/nitrox/nitrox_lib.c index 4ace9bcd603a..5cbc64b851b9 100644 --- a/drivers/crypto/cavium/nitrox/nitrox_lib.c +++ b/drivers/crypto/cavium/nitrox/nitrox_lib.c @@ -19,6 +19,8 @@ =20 /* packet inuput ring alignments */ #define PKTIN_Q_ALIGN_BYTES 16 +/* AQM Queue input alignments */ +#define AQM_Q_ALIGN_BYTES 32 =20 static int nitrox_cmdq_init(struct nitrox_cmdq *cmdq, int align_bytes) { @@ -57,11 +59,15 @@ static void nitrox_cmdq_reset(struct nitrox_cmdq *cmdq) =20 static void nitrox_cmdq_cleanup(struct nitrox_cmdq *cmdq) { - struct nitrox_device *ndev =3D cmdq->ndev; + struct nitrox_device *ndev; + + if (!cmdq) + return; =20 if (!cmdq->unalign_base) return; =20 + ndev =3D cmdq->ndev; cancel_work_sync(&cmdq->backlog_qflush); =20 dma_free_coherent(DEV(ndev), cmdq->qsize, @@ -78,6 +84,57 @@ static void nitrox_cmdq_cleanup(struct nitrox_cmdq *cmdq= ) cmdq->instr_size =3D 0; } =20 +static void nitrox_free_aqm_queues(struct nitrox_device *ndev) +{ + int i; + + for (i =3D 0; i < ndev->nr_queues; i++) { + nitrox_cmdq_cleanup(ndev->aqmq[i]); + kzfree(ndev->aqmq[i]); + ndev->aqmq[i] =3D NULL; + } +} + +static int nitrox_alloc_aqm_queues(struct nitrox_device *ndev) +{ + int i, err; + + for (i =3D 0; i < ndev->nr_queues; i++) { + struct nitrox_cmdq *cmdq; + u64 offset; + + cmdq =3D kzalloc_node(sizeof(*cmdq), GFP_KERNEL, ndev->node); + if (!cmdq) { + err =3D -ENOMEM; + goto aqmq_fail; + } + + cmdq->ndev =3D ndev; + cmdq->qno =3D i; + cmdq->instr_size =3D sizeof(struct aqmq_command_s); + + /* AQM Queue Doorbell Counter Register Address */ + offset =3D AQMQ_DRBLX(i); + cmdq->dbell_csr_addr =3D NITROX_CSR_ADDR(ndev, offset); + /* AQM Queue Commands Completed Count Register Address */ + offset =3D AQMQ_CMD_CNTX(i); + cmdq->compl_cnt_csr_addr =3D NITROX_CSR_ADDR(ndev, offset); + + err =3D nitrox_cmdq_init(cmdq, AQM_Q_ALIGN_BYTES); + if (err) { + kzfree(cmdq); + goto aqmq_fail; + } + ndev->aqmq[i] =3D cmdq; + } + + return 0; + +aqmq_fail: + nitrox_free_aqm_queues(ndev); + return err; +} + static void nitrox_free_pktin_queues(struct nitrox_device *ndev) { int i; @@ -222,6 +279,12 @@ int nitrox_common_sw_init(struct nitrox_device *ndev) if (err) destroy_crypto_dma_pool(ndev); =20 + err =3D nitrox_alloc_aqm_queues(ndev); + if (err) { + nitrox_free_pktin_queues(ndev); + destroy_crypto_dma_pool(ndev); + } + return err; } =20 @@ -231,6 +294,7 @@ int nitrox_common_sw_init(struct nitrox_device *ndev) */ void nitrox_common_sw_cleanup(struct nitrox_device *ndev) { + nitrox_free_aqm_queues(ndev); nitrox_free_pktin_queues(ndev); destroy_crypto_dma_pool(ndev); } diff --git a/drivers/crypto/cavium/nitrox/nitrox_req.h b/drivers/crypto/cav= ium/nitrox/nitrox_req.h index efdbd0fc3e3b..f69ba02c4d25 100644 --- a/drivers/crypto/cavium/nitrox/nitrox_req.h +++ b/drivers/crypto/cavium/nitrox/nitrox_req.h @@ -399,6 +399,36 @@ struct nps_pkt_instr { u64 fdata[2]; }; =20 +/** + * struct aqmq_command_s - The 32 byte command for AE processing. + * @opcode: Request opcode + * @param1: Request control parameter 1 + * @param2: Request control parameter 2 + * @dlen: Input length + * @dptr: Input pointer points to buffer in remote host + * @rptr: Result pointer points to buffer in remote host + * @grp: AQM Group (0..7) + * @cptr: Context pointer + */ +struct aqmq_command_s { + __be16 opcode; + __be16 param1; + __be16 param2; + __be16 dlen; + __be64 dptr; + __be64 rptr; + union { + __be64 word3; +#if defined(__BIG_ENDIAN_BITFIELD) + u64 grp : 3; + u64 cptr : 61; +#else + u64 cptr : 61; + u64 grp : 3; +#endif + }; +}; + /** * struct ctx_hdr - Book keeping data about the crypto context * @pool: Pool used to allocate crypto context --=20 2.17.2