* [PATCH 1/4] arm64: dts: ls1088a: Fix incorrect I2C clock divider
@ 2019-08-06 8:42 Chuanhua Han
2019-08-06 8:42 ` [PATCH 2/4] arm64: dts: ls1012a: " Chuanhua Han
` (4 more replies)
0 siblings, 5 replies; 7+ messages in thread
From: Chuanhua Han @ 2019-08-06 8:42 UTC (permalink / raw)
To: shawnguo, leoyang.li, robh+dt, mark.rutland
Cc: linux-arm-kernel, devicetree, linux-kernel, Chuanhua Han
Ls1088a platform, the i2c input clock is actually platform pll CLK / 8
(this is the hardware connection), other clock divider can not get the
correct i2c clock, resulting in the output of SCL pin clock is not
accurate.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 20f5ebd..30b760e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -324,7 +324,7 @@
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 3>;
+ clocks = <&clockgen 4 7>;
status = "disabled";
};
@@ -334,7 +334,7 @@
#size-cells = <0>;
reg = <0x0 0x2010000 0x0 0x10000>;
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 3>;
+ clocks = <&clockgen 4 7>;
status = "disabled";
};
@@ -344,7 +344,7 @@
#size-cells = <0>;
reg = <0x0 0x2020000 0x0 0x10000>;
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 3>;
+ clocks = <&clockgen 4 7>;
status = "disabled";
};
@@ -354,7 +354,7 @@
#size-cells = <0>;
reg = <0x0 0x2030000 0x0 0x10000>;
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 3>;
+ clocks = <&clockgen 4 7>;
status = "disabled";
};
--
2.9.5
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/4] arm64: dts: ls1012a: Fix incorrect I2C clock divider
2019-08-06 8:42 [PATCH 1/4] arm64: dts: ls1088a: Fix incorrect I2C clock divider Chuanhua Han
@ 2019-08-06 8:42 ` Chuanhua Han
2019-08-06 8:42 ` [PATCH 3/4] arm64: dts: ls1028a: " Chuanhua Han
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Chuanhua Han @ 2019-08-06 8:42 UTC (permalink / raw)
To: shawnguo, leoyang.li, robh+dt, mark.rutland
Cc: linux-arm-kernel, devicetree, linux-kernel, Chuanhua Han
Ls1012a platform, the i2c input clock is actually platform pll CLK / 4
(this is the hardware connection), other clock divider can not get the
correct i2c clock, resulting in the output of SCL pin clock is not
accurate.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index ec6257a..124a7e2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -323,7 +323,7 @@
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 0>;
+ clocks = <&clockgen 4 3>;
status = "disabled";
};
@@ -333,7 +333,7 @@
#size-cells = <0>;
reg = <0x0 0x2190000 0x0 0x10000>;
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 0>;
+ clocks = <&clockgen 4 3>;
status = "disabled";
};
--
2.9.5
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/4] arm64: dts: ls1028a: Fix incorrect I2C clock divider
2019-08-06 8:42 [PATCH 1/4] arm64: dts: ls1088a: Fix incorrect I2C clock divider Chuanhua Han
2019-08-06 8:42 ` [PATCH 2/4] arm64: dts: ls1012a: " Chuanhua Han
@ 2019-08-06 8:42 ` Chuanhua Han
2019-08-06 8:42 ` [PATCH 4/4] arm64: dts: lx2160a: " Chuanhua Han
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Chuanhua Han @ 2019-08-06 8:42 UTC (permalink / raw)
To: shawnguo, leoyang.li, robh+dt, mark.rutland
Cc: linux-arm-kernel, devicetree, linux-kernel, Chuanhua Han
Ls1028a platform, the i2c input clock is actually platform pll CLK / 4
(this is the hardware connection), other clock divider can not get the
correct i2c clock, resulting in the output of SCL pin clock is not
accurate.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index aef5b06..cca7bfdb 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -171,7 +171,7 @@
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>;
+ clocks = <&clockgen 4 3>;
status = "disabled";
};
@@ -181,7 +181,7 @@
#size-cells = <0>;
reg = <0x0 0x2010000 0x0 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>;
+ clocks = <&clockgen 4 3>;
status = "disabled";
};
@@ -191,7 +191,7 @@
#size-cells = <0>;
reg = <0x0 0x2020000 0x0 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>;
+ clocks = <&clockgen 4 3>;
status = "disabled";
};
@@ -201,7 +201,7 @@
#size-cells = <0>;
reg = <0x0 0x2030000 0x0 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>;
+ clocks = <&clockgen 4 3>;
status = "disabled";
};
@@ -211,7 +211,7 @@
#size-cells = <0>;
reg = <0x0 0x2040000 0x0 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>;
+ clocks = <&clockgen 4 3>;
status = "disabled";
};
@@ -221,7 +221,7 @@
#size-cells = <0>;
reg = <0x0 0x2050000 0x0 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>;
+ clocks = <&clockgen 4 3>;
status = "disabled";
};
@@ -231,7 +231,7 @@
#size-cells = <0>;
reg = <0x0 0x2060000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>;
+ clocks = <&clockgen 4 3>;
status = "disabled";
};
@@ -241,7 +241,7 @@
#size-cells = <0>;
reg = <0x0 0x2070000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>;
+ clocks = <&clockgen 4 3>;
status = "disabled";
};
--
2.9.5
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 4/4] arm64: dts: lx2160a: Fix incorrect I2C clock divider
2019-08-06 8:42 [PATCH 1/4] arm64: dts: ls1088a: Fix incorrect I2C clock divider Chuanhua Han
2019-08-06 8:42 ` [PATCH 2/4] arm64: dts: ls1012a: " Chuanhua Han
2019-08-06 8:42 ` [PATCH 3/4] arm64: dts: ls1028a: " Chuanhua Han
@ 2019-08-06 8:42 ` Chuanhua Han
2019-08-12 14:17 ` [PATCH 1/4] arm64: dts: ls1088a: " Shawn Guo
2019-08-19 7:43 ` Shawn Guo
4 siblings, 0 replies; 7+ messages in thread
From: Chuanhua Han @ 2019-08-06 8:42 UTC (permalink / raw)
To: shawnguo, leoyang.li, robh+dt, mark.rutland
Cc: linux-arm-kernel, devicetree, linux-kernel, Chuanhua Han
Lx2160a platform, the i2c input clock is actually platform pll CLK / 16
(this is the hardware connection), other clock divider can not get the
correct i2c clock, resulting in the output of SCL pin clock is not
accurate.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 4720a8e..408e0ec 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -485,7 +485,7 @@
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
- clocks = <&clockgen 4 7>;
+ clocks = <&clockgen 4 15>;
scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
@@ -497,7 +497,7 @@
reg = <0x0 0x2010000 0x0 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
- clocks = <&clockgen 4 7>;
+ clocks = <&clockgen 4 15>;
status = "disabled";
};
@@ -508,7 +508,7 @@
reg = <0x0 0x2020000 0x0 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
- clocks = <&clockgen 4 7>;
+ clocks = <&clockgen 4 15>;
status = "disabled";
};
@@ -519,7 +519,7 @@
reg = <0x0 0x2030000 0x0 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
- clocks = <&clockgen 4 7>;
+ clocks = <&clockgen 4 15>;
status = "disabled";
};
@@ -530,7 +530,7 @@
reg = <0x0 0x2040000 0x0 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
- clocks = <&clockgen 4 7>;
+ clocks = <&clockgen 4 15>;
scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
@@ -542,7 +542,7 @@
reg = <0x0 0x2050000 0x0 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
- clocks = <&clockgen 4 7>;
+ clocks = <&clockgen 4 15>;
status = "disabled";
};
@@ -553,7 +553,7 @@
reg = <0x0 0x2060000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
- clocks = <&clockgen 4 7>;
+ clocks = <&clockgen 4 15>;
status = "disabled";
};
@@ -564,7 +564,7 @@
reg = <0x0 0x2070000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
- clocks = <&clockgen 4 7>;
+ clocks = <&clockgen 4 15>;
status = "disabled";
};
--
2.9.5
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/4] arm64: dts: ls1088a: Fix incorrect I2C clock divider
2019-08-06 8:42 [PATCH 1/4] arm64: dts: ls1088a: Fix incorrect I2C clock divider Chuanhua Han
` (2 preceding siblings ...)
2019-08-06 8:42 ` [PATCH 4/4] arm64: dts: lx2160a: " Chuanhua Han
@ 2019-08-12 14:17 ` Shawn Guo
2019-08-12 20:59 ` Leo Li
2019-08-19 7:43 ` Shawn Guo
4 siblings, 1 reply; 7+ messages in thread
From: Shawn Guo @ 2019-08-12 14:17 UTC (permalink / raw)
To: Chuanhua Han
Cc: leoyang.li, robh+dt, mark.rutland, linux-arm-kernel, devicetree,
linux-kernel
On Tue, Aug 06, 2019 at 04:42:20PM +0800, Chuanhua Han wrote:
> Ls1088a platform, the i2c input clock is actually platform pll CLK / 8
> (this is the hardware connection), other clock divider can not get the
> correct i2c clock, resulting in the output of SCL pin clock is not
> accurate.
>
> Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
@Leo, looks good?
Shawn
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> index 20f5ebd..30b760e 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> @@ -324,7 +324,7 @@
> #size-cells = <0>;
> reg = <0x0 0x2000000 0x0 0x10000>;
> interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 3>;
> + clocks = <&clockgen 4 7>;
> status = "disabled";
> };
>
> @@ -334,7 +334,7 @@
> #size-cells = <0>;
> reg = <0x0 0x2010000 0x0 0x10000>;
> interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 3>;
> + clocks = <&clockgen 4 7>;
> status = "disabled";
> };
>
> @@ -344,7 +344,7 @@
> #size-cells = <0>;
> reg = <0x0 0x2020000 0x0 0x10000>;
> interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 3>;
> + clocks = <&clockgen 4 7>;
> status = "disabled";
> };
>
> @@ -354,7 +354,7 @@
> #size-cells = <0>;
> reg = <0x0 0x2030000 0x0 0x10000>;
> interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 3>;
> + clocks = <&clockgen 4 7>;
> status = "disabled";
> };
>
> --
> 2.9.5
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH 1/4] arm64: dts: ls1088a: Fix incorrect I2C clock divider
2019-08-12 14:17 ` [PATCH 1/4] arm64: dts: ls1088a: " Shawn Guo
@ 2019-08-12 20:59 ` Leo Li
0 siblings, 0 replies; 7+ messages in thread
From: Leo Li @ 2019-08-12 20:59 UTC (permalink / raw)
To: Shawn Guo, Chuanhua Han
Cc: robh+dt, mark.rutland, linux-arm-kernel, devicetree, linux-kernel
> -----Original Message-----
> From: Shawn Guo <shawnguo@kernel.org>
> Sent: Monday, August 12, 2019 9:17 AM
> To: Chuanhua Han <chuanhua.han@nxp.com>
> Cc: Leo Li <leoyang.li@nxp.com>; robh+dt@kernel.org;
> mark.rutland@arm.com; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 1/4] arm64: dts: ls1088a: Fix incorrect I2C clock divider
>
> On Tue, Aug 06, 2019 at 04:42:20PM +0800, Chuanhua Han wrote:
> > Ls1088a platform, the i2c input clock is actually platform pll CLK / 8
> > (this is the hardware connection), other clock divider can not get the
> > correct i2c clock, resulting in the output of SCL pin clock is not
> > accurate.
> >
> > Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
>
> @Leo, looks good?
Yes.
Acked-by: Li Yang <leoyang.li@nxp.com>
>
> Shawn
>
> > ---
> > arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 8 ++++----
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > index 20f5ebd..30b760e 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > @@ -324,7 +324,7 @@
> > #size-cells = <0>;
> > reg = <0x0 0x2000000 0x0 0x10000>;
> > interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
> > - clocks = <&clockgen 4 3>;
> > + clocks = <&clockgen 4 7>;
> > status = "disabled";
> > };
> >
> > @@ -334,7 +334,7 @@
> > #size-cells = <0>;
> > reg = <0x0 0x2010000 0x0 0x10000>;
> > interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
> > - clocks = <&clockgen 4 3>;
> > + clocks = <&clockgen 4 7>;
> > status = "disabled";
> > };
> >
> > @@ -344,7 +344,7 @@
> > #size-cells = <0>;
> > reg = <0x0 0x2020000 0x0 0x10000>;
> > interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
> > - clocks = <&clockgen 4 3>;
> > + clocks = <&clockgen 4 7>;
> > status = "disabled";
> > };
> >
> > @@ -354,7 +354,7 @@
> > #size-cells = <0>;
> > reg = <0x0 0x2030000 0x0 0x10000>;
> > interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
> > - clocks = <&clockgen 4 3>;
> > + clocks = <&clockgen 4 7>;
> > status = "disabled";
> > };
> >
> > --
> > 2.9.5
> >
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/4] arm64: dts: ls1088a: Fix incorrect I2C clock divider
2019-08-06 8:42 [PATCH 1/4] arm64: dts: ls1088a: Fix incorrect I2C clock divider Chuanhua Han
` (3 preceding siblings ...)
2019-08-12 14:17 ` [PATCH 1/4] arm64: dts: ls1088a: " Shawn Guo
@ 2019-08-19 7:43 ` Shawn Guo
4 siblings, 0 replies; 7+ messages in thread
From: Shawn Guo @ 2019-08-19 7:43 UTC (permalink / raw)
To: Chuanhua Han
Cc: leoyang.li, robh+dt, mark.rutland, linux-arm-kernel, devicetree,
linux-kernel
On Tue, Aug 06, 2019 at 04:42:20PM +0800, Chuanhua Han wrote:
> Ls1088a platform, the i2c input clock is actually platform pll CLK / 8
> (this is the hardware connection), other clock divider can not get the
> correct i2c clock, resulting in the output of SCL pin clock is not
> accurate.
>
> Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Applied all, thanks.
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-08-19 7:43 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-06 8:42 [PATCH 1/4] arm64: dts: ls1088a: Fix incorrect I2C clock divider Chuanhua Han
2019-08-06 8:42 ` [PATCH 2/4] arm64: dts: ls1012a: " Chuanhua Han
2019-08-06 8:42 ` [PATCH 3/4] arm64: dts: ls1028a: " Chuanhua Han
2019-08-06 8:42 ` [PATCH 4/4] arm64: dts: lx2160a: " Chuanhua Han
2019-08-12 14:17 ` [PATCH 1/4] arm64: dts: ls1088a: " Shawn Guo
2019-08-12 20:59 ` Leo Li
2019-08-19 7:43 ` Shawn Guo
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).