From: Wen He <wen.he_1@nxp.com>
To: linux-devel@linux.nxdi.nxp.com, Rob Herring <robh+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Shawn Guo <shawnguo@kernel.org>,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: leoyang.li@nxp.com, liviu.dudau@arm.com, Wen He <wen.he_1@nxp.com>
Subject: [v2 1/3] dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings
Date: Thu, 15 Aug 2019 18:16:11 +0800 [thread overview]
Message-ID: <20190815101613.22872-1-wen.he_1@nxp.com> (raw)
LS1028A has a clock domain PXLCLK0 used for provide pixel clocks to Display
output interface. Add a YAML schema for this.
Signed-off-by: Wen He <wen.he_1@nxp.com>
---
change in v2:
- Convert bindings to YAML format
.../devicetree/bindings/clock/fsl,plldig.yaml | 43 +++++++++++++++++++
1 file changed, 43 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/fsl,plldig.yaml
diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.yaml b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml
new file mode 100644
index 000000000000..32274e94aafc
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/clock/fsl,plldig.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding
+
+maintainers:
+ - Wen He <wen.he_1@nxp.com>
+
+description: |
+ NXP LS1028A has a clock domain PXLCLK0 used for the Display output
+ interface in the display core, as implemented in TSMC CLN28HPM PLL.
+ which generate and offers pixel clocks to Display.
+
+properties:
+ compatible:
+ const: fsl,ls1028a-plldig
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+examples:
+ # Display PIXEL Clock node:
+ - |
+ dpclk: clock-display@f1f0000 {
+ compatible = "fsl,ls1028a-plldig";
+ reg = <0x0 0xf1f0000 0x0 0xffff>;
+ #clock-cells = <0>;
+ clocks = <&osc_27m>;
+ };
+
+...
--
2.17.1
next reply other threads:[~2019-08-15 10:26 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-15 10:16 Wen He [this message]
2019-08-15 10:16 ` [v2 2/3] clk: ls1028a: Add clock driver for Display output interface Wen He
2019-08-16 17:46 ` Stephen Boyd
2019-08-19 7:30 ` [EXT] " Wen He
2019-08-19 18:29 ` Stephen Boyd
2019-08-20 2:24 ` Wen He
2019-09-16 18:32 ` Stephen Boyd
2019-08-15 10:16 ` [v2 3/3] arm64: dts: ls1028a: Add properties node for Display output pixel clock Wen He
2019-08-15 13:49 ` [v2 1/3] dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings Rob Herring
2019-08-16 17:47 ` Stephen Boyd
2019-08-19 2:14 ` [EXT] " Wen He
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