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Sat, 24 Aug 2019 12:07:17 +0000 From: To: , , , , , , CC: , Subject: [PATCH v2 6/6] mtd: spi-nor: Add the SPI_NOR_XSR_RDY flag Thread-Topic: [PATCH v2 6/6] mtd: spi-nor: Add the SPI_NOR_XSR_RDY flag Thread-Index: AQHVWnR525fTUtp96EeU3jpXKgU9Ug== Date: Sat, 24 Aug 2019 12:07:17 +0000 Message-ID: <20190824120650.14752-7-tudor.ambarus@microchip.com> References: <20190824120650.14752-1-tudor.ambarus@microchip.com> In-Reply-To: <20190824120650.14752-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1P190CA0024.EURP190.PROD.OUTLOOK.COM (2603:10a6:802:2b::37) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [86.127.53.184] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: d918e984-208a-4362-9785-08d7288b9bea x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600166)(711020)(4605104)(1401327)(2017052603328)(7193020);SRVR:MN2PR11MB4301; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: d918e984-208a-4362-9785-08d7288b9bea X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Aug 2019 12:07:17.8971 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: EEe7nwo97LorajRvqDswtw7PuXniLORxPglFiXMYloOZ+0V6hHq6yy3YeeAiirnHtlKboFOA3cHh1QtGEN2I7l9vQmMKp85G2EkkNA8P8lE= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4301 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Boris Brezillon S3AN flashes use a specific opcode to read the status register. We currently use the SPI_S3AN flag to decide whether this specific SR read opcode should be used, but SPI_S3AN is about to disappear, so let's add a new flag. Note that we use the same bit as SPI_S3AN implies SPI_NOR_XSR_RDY and vice versa. Signed-off-by: Boris Brezillon Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 5e16f293a83b..e76c23d1c54a 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -211,6 +211,14 @@ struct flash_info { * bit. Must be used with * SPI_NOR_HAS_LOCK. */ +#define SPI_NOR_XSR_RDY BIT(10) /* + * S3AN flashes have specific opcode to + * read the status register. + * Flags SPI_NOR_XSR_RDY and SPI_S3AN + * use the same bit as one implies the + * other, but we will get rid of + * SPI_S3AN soon. + */ #define SPI_S3AN BIT(10) /* * Xilinx Spartan 3AN In-System Flash * (MFR cannot be used for probing @@ -4839,7 +4847,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *nam= e, * spi_nor_wait_till_ready(). Xilinx S3AN share MFR * with Atmel spi-nor */ - if (info->flags & SPI_S3AN) + if (info->flags & SPI_NOR_XSR_RDY) nor->flags |=3D SNOR_F_READY_XSR_RDY; =20 if (info->flags & SPI_NOR_HAS_LOCK) { --=20 2.9.5