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From:   Vidya Sagar <vidyas@nvidia.com>
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Subject: [PATCH 0/6] PCI: tegra: Enable PCIe C5 controller of Tegra194 in p2972-0000 platform
Date:   Mon, 26 Aug 2019 13:01:37 +0530
Message-ID: <20190826073143.4582-1-vidyas@nvidia.com>
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This patch series enables Tegra194's C5 controller which owns x16 slot in
p2972-0000 platform. C5 controller's PERST# and CLKREQ# are not configured as
output and bi-directional signals by default and hence they need to be
configured explicitly. Also, x16 slot's 3.3V and 12V supplies are controlled
through GPIOs and hence they need to be enabled through regulator framework.
This patch series adds required infrastructural support to address both the
aforementioned requirements.
Testing done on p2972-0000 platform
- Able to enumerate devices connected to x16 slot (owned by C5 controller)
- Enumerated device's functionality verified
- Suspend-Resume sequence is verified with device connected to x16 slot

Vidya Sagar (6):
  dt-bindings: PCI: tegra: Add sideband pins configuration entries
  arm64: tegra: Add configuration for PCIe C5 sideband signals
  PCI: tegra: Add support to configure sideband pins
  dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries
  arm64: tegra: Add PCIe slot supply information in p2972-0000 platform
  PCI: tegra: Add support to enable slot regulators

 .../bindings/pci/nvidia,tegra194-pcie.txt     | 16 +++++
 .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 24 +++++++
 .../boot/dts/nvidia/tegra194-p2972-0000.dts   |  4 +-
 arch/arm64/boot/dts/nvidia/tegra194.dtsi      | 38 +++++++++-
 drivers/pci/controller/dwc/pcie-tegra194.c    | 71 +++++++++++++++++++
 5 files changed, 151 insertions(+), 2 deletions(-)

-- 
2.17.1