From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53BADC3A5A3 for ; Tue, 27 Aug 2019 15:30:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2893C2184D for ; Tue, 27 Aug 2019 15:30:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730210AbfH0Pad (ORCPT ); Tue, 27 Aug 2019 11:30:33 -0400 Received: from foss.arm.com ([217.140.110.172]:46802 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727910AbfH0Pac (ORCPT ); Tue, 27 Aug 2019 11:30:32 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CDB94337; Tue, 27 Aug 2019 08:30:31 -0700 (PDT) Received: from localhost (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 28B733F59C; Tue, 27 Aug 2019 08:30:31 -0700 (PDT) Date: Tue, 27 Aug 2019 16:30:29 +0100 From: Andrew Murray To: Vidya Sagar Cc: lorenzo.pieralisi@arm.com, bhelgaas@google.com, robh+dt@kernel.org, thierry.reding@gmail.com, jonathanh@nvidia.com, kishon@ti.com, gustavo.pimentel@synopsys.com, digetx@gmail.com, mperttunen@nvidia.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kthota@nvidia.com, mmaddireddy@nvidia.com, sagar.tv@gmail.com Subject: Re: [PATCH 3/6] PCI: tegra: Add support to configure sideband pins Message-ID: <20190827153029.GO14582@e119886-lin.cambridge.arm.com> References: <20190826073143.4582-1-vidyas@nvidia.com> <20190826073143.4582-4-vidyas@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190826073143.4582-4-vidyas@nvidia.com> User-Agent: Mutt/1.10.1+81 (426a6c1) (2018-08-26) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Aug 26, 2019 at 01:01:40PM +0530, Vidya Sagar wrote: > Add support to configure sideband signal pins when information is present > in respective controller's device-tree node. > > Signed-off-by: Vidya Sagar > --- > drivers/pci/controller/dwc/pcie-tegra194.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c > index fc0dbeb31d78..8a27b25893c9 100644 > --- a/drivers/pci/controller/dwc/pcie-tegra194.c > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c > @@ -1308,6 +1308,12 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) > return ret; > } > > + ret = pinctrl_pm_select_default_state(pcie->dev); > + if (ret < 0) { > + dev_err(pcie->dev, "Failed to configure sideband pins\n"); I think you can just use dev instead of pcie->dev here. > + return ret; Don't you need to pm_runtime_put_sync and pm_runtime_disable here? Thanks, Andrew Murray > + } > + > tegra_pcie_init_controller(pcie); > > pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci); > -- > 2.17.1 >