* [PATCH] perf/x86/intel: Update ICL Core and Package C-state event counters
@ 2019-07-26 9:08 Harry Pan
2019-08-30 11:33 ` Peter Zijlstra
2019-09-02 3:35 ` [PATCH v2] " Harry Pan
0 siblings, 2 replies; 4+ messages in thread
From: Harry Pan @ 2019-07-26 9:08 UTC (permalink / raw)
To: LKML
Cc: gs0622, Harry Pan, Namhyung Kim, H. Peter Anvin, Peter Zijlstra,
Borislav Petkov, x86, Thomas Gleixner, Ingo Molnar, Jiri Olsa,
Alexander Shishkin, Arnaldo Carvalho de Melo
Ice Lake microarchitecture inherits Cannon Lake, it has CC1/PC8/PC9/PC10
residency counters.
Update the list of Ice Lake PMU event counters from the snb_cstates[] list
of events to the cnl_cstates[] list of events, which keeps all previously
supported events and also adds the CORE_C1, PKG_C8, PKG_C9, and PKG_C10
residency counters.
This benefits users to profile them through the perf interface.
Signed-off-by: Harry Pan <harry.pan@intel.com>
---
arch/x86/events/intel/cstate.c | 26 ++++++++++++++------------
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 688592b34564..08291233f5c9 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -40,51 +40,53 @@
* Model specific counters:
* MSR_CORE_C1_RES: CORE C1 Residency Counter
* perf code: 0x00
- * Available model: SLM,AMT,GLM,CNL
+ * Available model: SLM,AMT,GLM,CNL,ICL
* Scope: Core (each processor core has a MSR)
* MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
* perf code: 0x01
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,
- CNL
+ CNL,ICL
* Scope: Core
* MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
- * SKL,KNL,GLM,CNL
+ * SKL,KNL,GLM,CNL,ICL
* Scope: Core
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
* perf code: 0x03
- * Available model: SNB,IVB,HSW,BDW,SKL,CNL
+ * Available model: SNB,IVB,HSW,BDW,SKL,CNL,ICL
* Scope: Core
* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
* perf code: 0x00
- * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL
+ * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
+ ICL
* Scope: Package (physical package)
* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
* perf code: 0x01
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
- * GLM,CNL
+ * GLM,CNL,ICL
* Scope: Package (physical package)
* MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- * SKL,KNL,GLM,CNL
+ * SKL,KNL,GLM,CNL,ICL
* Scope: Package (physical package)
* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
* perf code: 0x03
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL
+ ICL
* Scope: Package (physical package)
* MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
* perf code: 0x04
- * Available model: HSW ULT,KBL,CNL
+ * Available model: HSW ULT,KBL,CNL,ICL
* Scope: Package (physical package)
* MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
* perf code: 0x05
- * Available model: HSW ULT,KBL,CNL
+ * Available model: HSW ULT,KBL,CNL,ICL
* Scope: Package (physical package)
* MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
* perf code: 0x06
- * Available model: HSW ULT,KBL,GLM,CNL
+ * Available model: HSW ULT,KBL,GLM,CNL,ICL
* Scope: Package (physical package)
*
*/
@@ -625,8 +627,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates),
- X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_MOBILE, snb_cstates),
- X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_DESKTOP, snb_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_MOBILE, cnl_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_DESKTOP, cnl_cstates),
{ },
};
MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
--
2.20.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] perf/x86/intel: Update ICL Core and Package C-state event counters
2019-07-26 9:08 [PATCH] perf/x86/intel: Update ICL Core and Package C-state event counters Harry Pan
@ 2019-08-30 11:33 ` Peter Zijlstra
2019-09-03 3:00 ` Pan, Harry
2019-09-02 3:35 ` [PATCH v2] " Harry Pan
1 sibling, 1 reply; 4+ messages in thread
From: Peter Zijlstra @ 2019-08-30 11:33 UTC (permalink / raw)
To: Harry Pan
Cc: LKML, gs0622, Namhyung Kim, H. Peter Anvin, Borislav Petkov, x86,
Thomas Gleixner, Ingo Molnar, Jiri Olsa, Alexander Shishkin,
Arnaldo Carvalho de Melo
On Fri, Jul 26, 2019 at 05:08:46PM +0800, Harry Pan wrote:
> Ice Lake microarchitecture inherits Cannon Lake, it has CC1/PC8/PC9/PC10
> residency counters.
>
> Update the list of Ice Lake PMU event counters from the snb_cstates[] list
> of events to the cnl_cstates[] list of events, which keeps all previously
> supported events and also adds the CORE_C1, PKG_C8, PKG_C9, and PKG_C10
> residency counters.
>
> This benefits users to profile them through the perf interface.
>
> Signed-off-by: Harry Pan <harry.pan@intel.com>
>
> ---
>
> arch/x86/events/intel/cstate.c | 26 ++++++++++++++------------
> 1 file changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
> index 688592b34564..08291233f5c9 100644
> --- a/arch/x86/events/intel/cstate.c
> +++ b/arch/x86/events/intel/cstate.c
> @@ -40,51 +40,53 @@
> * Model specific counters:
> * MSR_CORE_C1_RES: CORE C1 Residency Counter
> * perf code: 0x00
> - * Available model: SLM,AMT,GLM,CNL
> + * Available model: SLM,AMT,GLM,CNL,ICL
> * Scope: Core (each processor core has a MSR)
> * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
> * perf code: 0x01
> * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,
> - CNL
> + CNL,ICL
That has a missing * introduced by the last such patch. Please take this
opportunity to put it back in.
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v2] perf/x86/intel: Update ICL Core and Package C-state event counters
2019-07-26 9:08 [PATCH] perf/x86/intel: Update ICL Core and Package C-state event counters Harry Pan
2019-08-30 11:33 ` Peter Zijlstra
@ 2019-09-02 3:35 ` Harry Pan
1 sibling, 0 replies; 4+ messages in thread
From: Harry Pan @ 2019-09-02 3:35 UTC (permalink / raw)
To: LKML
Cc: gs0622, Harry Pan, Namhyung Kim, H. Peter Anvin, Peter Zijlstra,
Borislav Petkov, x86, Thomas Gleixner, Ingo Molnar, Jiri Olsa,
Alexander Shishkin, Arnaldo Carvalho de Melo
Ice Lake microarchitecture inherits Cannon Lake, it has CC1/PC8/PC9/PC10
residency counters.
Update the list of Ice Lake PMU event counters from the snb_cstates[] list
of events to the cnl_cstates[] list of events, which keeps all previously
supported events and also adds the CORE_C1, PKG_C8, PKG_C9, and PKG_C10
residency counters.
This benefits users to profile them through the perf interface.
Signed-off-by: Harry Pan <harry.pan@intel.com>
---
arch/x86/events/intel/cstate.c | 32 +++++++++++++++++---------------
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 688592b34564..82fbc4c6e5e6 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -35,56 +35,58 @@
* The counters include PKG_C*_RESIDENCY.
*
* All of these counters are specified in the Intel® 64 and IA-32
- * Architectures Software Developer.s Manual Vol3b.
+ * Architectures Software Developer's Manual Vol4.
*
* Model specific counters:
* MSR_CORE_C1_RES: CORE C1 Residency Counter
* perf code: 0x00
- * Available model: SLM,AMT,GLM,CNL
+ * Available model: SLM,AMT,GLM,CNL,ICL
* Scope: Core (each processor core has a MSR)
* MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
* perf code: 0x01
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,
- CNL
+ * CNL,ICL
* Scope: Core
* MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
- * SKL,KNL,GLM,CNL
+ * SKL,KNL,GLM,CNL,ICL
* Scope: Core
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
* perf code: 0x03
- * Available model: SNB,IVB,HSW,BDW,SKL,CNL
+ * Available model: SNB,IVB,HSW,BDW,SKL,CNL,ICL
* Scope: Core
* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
* perf code: 0x00
- * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL
+ * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
+ * ICL
* Scope: Package (physical package)
* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
* perf code: 0x01
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
- * GLM,CNL
+ * GLM,CNL,ICL
* Scope: Package (physical package)
* MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
* perf code: 0x02
- * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- * SKL,KNL,GLM,CNL
+ * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
+ * SKL,KNL,GLM,CNL,ICL
* Scope: Package (physical package)
* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
* perf code: 0x03
- * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL
+ * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,
+ * ICL
* Scope: Package (physical package)
* MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
* perf code: 0x04
- * Available model: HSW ULT,KBL,CNL
+ * Available model: HSW ULT,KBL,CNL,ICL
* Scope: Package (physical package)
* MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
* perf code: 0x05
- * Available model: HSW ULT,KBL,CNL
+ * Available model: HSW ULT,KBL,CNL,ICL
* Scope: Package (physical package)
* MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
* perf code: 0x06
- * Available model: HSW ULT,KBL,GLM,CNL
+ * Available model: HSW ULT,KBL,GLM,CNL,ICL
* Scope: Package (physical package)
*
*/
@@ -625,8 +627,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates),
- X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_MOBILE, snb_cstates),
- X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_DESKTOP, snb_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_MOBILE, cnl_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_DESKTOP, cnl_cstates),
{ },
};
MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
--
2.21.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* RE: [PATCH] perf/x86/intel: Update ICL Core and Package C-state event counters
2019-08-30 11:33 ` Peter Zijlstra
@ 2019-09-03 3:00 ` Pan, Harry
0 siblings, 0 replies; 4+ messages in thread
From: Pan, Harry @ 2019-09-03 3:00 UTC (permalink / raw)
To: Peter Zijlstra; +Cc: LKML, x86
Thank you Peter for pointing out my miss, I appreciate that sincerely.
> * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
> * perf code: 0x01
> * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,
> - CNL
> + CNL,ICL
That has a missing * introduced by the last such patch. Please take this
opportunity to put it back in.
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-09-03 3:07 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-07-26 9:08 [PATCH] perf/x86/intel: Update ICL Core and Package C-state event counters Harry Pan
2019-08-30 11:33 ` Peter Zijlstra
2019-09-03 3:00 ` Pan, Harry
2019-09-02 3:35 ` [PATCH v2] " Harry Pan
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).