From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Jethro Beekman <jethro@fortanix.com>
Cc: Marek Vasut <marek.vasut@gmail.com>,
Tudor Ambarus <tudor.ambarus@microchip.com>,
David Woodhouse <dwmw2@infradead.org>,
Brian Norris <computersforpeace@gmail.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Allison Randal <allison@lohutok.net>,
Thomas Gleixner <tglx@linutronix.de>,
Enrico Weigelt <info@metux.net>,
"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/2] mtd: spi-nor: intel-spi: add support for Intel Cannon Lake SPI flash
Date: Sat, 31 Aug 2019 18:44:32 +0300 [thread overview]
Message-ID: <20190831154432.GS3177@lahna.fi.intel.com> (raw)
In-Reply-To: <74545c4c-a9fc-77c8-cb54-6fbf747f0eea@fortanix.com>
On Sat, Aug 31, 2019 at 03:29:21PM +0000, Jethro Beekman wrote:
> > > + ispi->sregs = NULL;
> > > + ispi->pregs = ispi->base + CNL_PR;
> > > + ispi->nregions = CNL_FREG_NUM;
> > > + ispi->pr_num = CNL_PR_NUM;
> >
> > Does CNL really have a different number of PR and FR regions than the
> > previous generations?
>
> I'm using this as a reference: https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/300-series-chipset-pch-datasheet-vol-2.pdf
> . If you have more accurate information, please let me know.
No looks correct to me. I think it is a good idea to mention this in the
changelog, though.
next prev parent reply other threads:[~2019-08-31 15:44 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-31 5:50 [PATCH 2/2] mtd: spi-nor: intel-spi: add support for Intel Cannon Lake SPI flash Jethro Beekman
2019-08-31 13:36 ` Mika Westerberg
2019-08-31 15:29 ` Jethro Beekman
2019-08-31 15:44 ` Mika Westerberg [this message]
-- strict thread matches above, loose matches on Subject: below --
2019-08-31 5:50 Jethro Beekman
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