From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2006BC3A59E for ; Tue, 3 Sep 2019 01:39:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EBF78217D7 for ; Tue, 3 Sep 2019 01:39:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726260AbfICBjW (ORCPT ); Mon, 2 Sep 2019 21:39:22 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:2193 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725854AbfICBjV (ORCPT ); Mon, 2 Sep 2019 21:39:21 -0400 X-UUID: 6d6db5c5ebc44cf2b5ad3837c9d4759b-20190903 X-UUID: 6d6db5c5ebc44cf2b5ad3837c9d4759b-20190903 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1775787851; Tue, 03 Sep 2019 09:39:12 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 Sep 2019 09:39:12 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 3 Sep 2019 09:39:12 +0800 From: Bibby Hsieh To: David Airlie , Matthias Brugger , Daniel Vetter , , CC: Philipp Zabel , YT Shen , Thierry Reding , CK Hu , , , , , Bibby Hsieh , Yongqiang Niu Subject: [PATCH] arm64: dts: mt8183: Add gce setting in display node Date: Tue, 3 Sep 2019 09:39:10 +0800 Message-ID: <20190903013910.30225-1-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In order to use GCE function, we need add some informations into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events). Signed-off-by: Bibby Hsieh Signed-off-by: Yongqiang Niu --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 5616d158a4fa..b7d294c1c5b4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -485,6 +485,11 @@ compatible = "mediatek,mt8183-display"; reg = <0 0x14000000 0 0x1000>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; + mediatek,gce-events = , + ; }; ovl0: ovl@14008000 { @@ -494,6 +499,7 @@ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL0>; mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; }; ovl_2l0: ovl@14009000 { @@ -503,6 +509,7 @@ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; }; ovl_2l1: ovl@1400a000 { @@ -512,6 +519,7 @@ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; }; rdma0: rdma@1400b000 { @@ -522,6 +530,7 @@ clocks = <&mmsys CLK_MM_DISP_RDMA0>; mediatek,larb = <&larb0>; mediatek,rdma_fifo_size = <5>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; }; rdma1: rdma@1400c000 { @@ -532,6 +541,7 @@ clocks = <&mmsys CLK_MM_DISP_RDMA1>; mediatek,larb = <&larb0>; mediatek,rdma_fifo_size = <2>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; color0: color@1400e000 { @@ -541,6 +551,7 @@ interrupts = ; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; }; ccorr0: ccorr@1400f000 { @@ -549,6 +560,7 @@ interrupts = ; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_CCORR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; }; aal0: aal@14010000 { @@ -558,6 +570,7 @@ interrupts = ; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_AAL0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; }; gamma0: gamma@14011000 { @@ -567,6 +580,7 @@ interrupts = ; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; }; dither0: dither@14012000 { @@ -575,6 +589,7 @@ interrupts = ; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_DITHER0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; }; mutex: mutex@14016000 { -- 2.18.0