From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8104C49ED6 for ; Tue, 10 Sep 2019 11:51:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 995002084D for ; Tue, 10 Sep 2019 11:51:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=alien8.de header.i=@alien8.de header.b="fLz3HvLx" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730029AbfIJLvX (ORCPT ); Tue, 10 Sep 2019 07:51:23 -0400 Received: from mail.skyhub.de ([5.9.137.197]:60502 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725981AbfIJLvX (ORCPT ); Tue, 10 Sep 2019 07:51:23 -0400 Received: from zn.tnic (p200300EC2F0ABE00B4DC6059A6D53D5D.dip0.t-ipconnect.de [IPv6:2003:ec:2f0a:be00:b4dc:6059:a6d5:3d5d]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTPSA id DEB3D1EC09F7; Tue, 10 Sep 2019 13:51:21 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alien8.de; s=dkim; t=1568116282; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:in-reply-to:in-reply-to: references:references; bh=OF2GNeo9EcoV7r2cxiD5XuZ5iJsWKvLEg2fxOrk40c8=; b=fLz3HvLx3ynrT+1I5v54lpWSEP0T5DZtDyTIyhmmXWLKHuL1r6rIfCW/9jCtoY3MzqyKYy hSkVCejAFaityap4Vi2JjYj5R4mVLRnlmF+WdQ7c7ec0iayRvWnFggfJDZoijnK/8mVzOM pIDycg6TvNudv251RJWFzwSVD21fWhw= Date: Tue, 10 Sep 2019 13:51:16 +0200 From: Borislav Petkov To: Tony W Wang-oc Cc: "tony.luck@intel.com" , "tglx@linutronix.de" , "mingo@redhat.com" , "hpa@zytor.com" , "x86@kernel.org" , "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "yazen.ghannam@amd.com" , "vishal.l.verma@intel.com" , "qiuxu.zhuo@intel.com" , David Wang , "Cooper Yan(BJ-RD)" , "Qiyuan Wang(BJ-RD)" , "Herry Yang(BJ-RD)" Subject: Re: [PATCH v2 1/4] x86/mce: Add Zhaoxin MCE support Message-ID: <20190910115116.GD23931@zn.tnic> References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 10, 2019 at 08:19:08AM +0000, Tony W Wang-oc wrote: > All Zhaoxin newer CPUs support MCE that compatible with Intel's > "Machine-Check Architecture", so add support for Zhaoxin MCE in > mce/core.c. > > Signed-off-by: Tony W Wang-oc > --- > arch/x86/kernel/cpu/mce/core.c | 30 ++++++++++++++++++++++++------ > 1 file changed, 24 insertions(+), 6 deletions(-) > > diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c > index 743370e..3f878f6 100644 > --- a/arch/x86/kernel/cpu/mce/core.c > +++ b/arch/x86/kernel/cpu/mce/core.c > @@ -488,8 +488,9 @@ int mce_usable_address(struct mce *m) > if (!(m->status & MCI_STATUS_ADDRV)) > return 0; > > - /* Checks after this one are Intel-specific: */ > - if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) > + /* Checks after this one are Intel/Zhaoxin-specific: */ > + if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && > + boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) > return 1; > > if (!(m->status & MCI_STATUS_MISCV)) > @@ -510,7 +511,8 @@ bool mce_is_memory_error(struct mce *m) > if (m->cpuvendor == X86_VENDOR_AMD || > m->cpuvendor == X86_VENDOR_HYGON) { > return amd_mce_is_memory_error(m); > - } else if (m->cpuvendor == X86_VENDOR_INTEL) { > + } else if (m->cpuvendor == X86_VENDOR_INTEL || > + m->cpuvendor == X86_VENDOR_ZHAOXIN) { > /* > * Intel SDM Volume 3B - 15.9.2 Compound Error Codes > * Make that a switch-case for better readability pls. > @@ -1697,6 +1699,21 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) > if (c->x86 == 6 && c->x86_model == 45) > quirk_no_way_out = quirk_sandybridge_ifu; > } > + > + if (c->x86_vendor == X86_VENDOR_ZHAOXIN) { > + /* > + * All newer Zhaoxin CPUs support MCE broadcasting. Enable > + * synchronization with a one second timeout. > + */ > + if ((c->x86 == 6 && c->x86_model == 0x19 && > + (c->x86_stepping > 3 && c->x86_stepping < 8)) || > + (c->x86 == 6 && c->x86_model == 0x1f) || > + c->x86 > 6) { Can this be simplified into maybe something like this: if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) this is, of course, assuming that Zhaoxin doesn't do family < 6 and that the other steppings for model 0x19 don't matter because they don't exist or so... -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette