[PATCH v2 0/5] irqchip/irq-bcm7038-l1 updates

[PATCH v2 0/5] irqchip/irq-bcm7038-l1 updates

[Florian Fainelli]

Hi Marc, Jason, Thomas,

This patch series contains some updates from our internal tree to
support power management and allow configuring specific instances of the
brcm,bcm7038-l1-intc to leave some interrupts untouched and how the
firmware might have configured them.

Changes in v2:

- dropped the accidental fixup patch that made it to the list and squash
  it with patch #1 as it should have

Florian Fainelli (4):
  dt-bindings: Document brcm,irq-can-wake for brcm,bcm7038-l1-intc.txt
  irqchip/irq-bcm7038-l1: Enable parent IRQ if necessary
  dt-bindings: Document brcm,int-fwd-mask property for bcm7038-l1-intc
  irqchip/irq-bcm7038-l1: Support brcm,int-fwd-mask

Justin Chen (1):
  irqchip/irq-bcm7038-l1: Add PM support

 .../brcm,bcm7038-l1-intc.txt                  |   9 ++
 drivers/irqchip/irq-bcm7038-l1.c              | 117 +++++++++++++++++-
 2 files changed, 124 insertions(+), 2 deletions(-)

-- 
2.17.1

[PATCH v2 1/5] irqchip/irq-bcm7038-l1: Add PM support

[Florian Fainelli]

From: Justin Chen <justinpopo6@gmail.com>

The current l1 controller does not mask any interrupts when dropping
into suspend. This mean we can receive unexpected wake up sources.
Modified MIPS l1 controller to mask the all non-wake interrupts before
dropping into suspend.

Signed-off-by: Justin Chen <justinpopo6@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 drivers/irqchip/irq-bcm7038-l1.c | 98 ++++++++++++++++++++++++++++++++
 1 file changed, 98 insertions(+)

diff --git a/drivers/irqchip/irq-bcm7038-l1.c b/drivers/irqchip/irq-bcm7038-l1.c
index fc75c61233aa..f5e4ff5251ab 100644
--- a/drivers/irqchip/irq-bcm7038-l1.c
+++ b/drivers/irqchip/irq-bcm7038-l1.c
@@ -27,6 +27,7 @@
 #include <linux/types.h>
 #include <linux/irqchip.h>
 #include <linux/irqchip/chained_irq.h>
+#include <linux/syscore_ops.h>
 
 #define IRQS_PER_WORD		32
 #define REG_BYTES_PER_IRQ_WORD	(sizeof(u32) * 4)
@@ -39,6 +40,10 @@ struct bcm7038_l1_chip {
 	unsigned int		n_words;
 	struct irq_domain	*domain;
 	struct bcm7038_l1_cpu	*cpus[NR_CPUS];
+#ifdef CONFIG_PM_SLEEP
+	struct list_head	list;
+	u32			wake_mask[MAX_WORDS];
+#endif
 	u8			affinity[MAX_WORDS * IRQS_PER_WORD];
 };
 
@@ -47,6 +52,17 @@ struct bcm7038_l1_cpu {
 	u32			mask_cache[0];
 };
 
+/*
+ * We keep a list of bcm7038_l1_chip used for suspend/resume. This hack is
+ * used because the struct chip_type suspend/resume hooks are not called
+ * unless chip_type is hooked onto a generic_chip. Since this driver does
+ * not use generic_chip, we need to manually hook our resume/suspend to
+ * syscore_ops.
+ */
+#ifdef CONFIG_PM_SLEEP
+static LIST_HEAD(bcm7038_l1_intcs_list);
+#endif
+
 /*
  * STATUS/MASK_STATUS/MASK_SET/MASK_CLEAR are packed one right after another:
  *
@@ -287,6 +303,77 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
 	return 0;
 }
 
+#ifdef CONFIG_PM_SLEEP
+static int bcm7038_l1_suspend(void)
+{
+	struct bcm7038_l1_chip *intc;
+	unsigned long flags;
+	int boot_cpu, word;
+
+	/* Wakeup interrupt should only come from the boot cpu */
+	boot_cpu = cpu_logical_map(smp_processor_id());
+
+	list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
+		raw_spin_lock_irqsave(&intc->lock, flags);
+		for (word = 0; word < intc->n_words; word++) {
+			l1_writel(~intc->wake_mask[word],
+				intc->cpus[boot_cpu]->map_base +
+				reg_mask_set(intc, word));
+			l1_writel(intc->wake_mask[word],
+				intc->cpus[boot_cpu]->map_base +
+				reg_mask_clr(intc, word));
+		}
+		raw_spin_unlock_irqrestore(&intc->lock, flags);
+	}
+
+	return 0;
+}
+
+static void bcm7038_l1_resume(void)
+{
+	struct bcm7038_l1_chip *intc;
+	unsigned long flags;
+	int boot_cpu, word;
+
+	boot_cpu = cpu_logical_map(smp_processor_id());
+
+	list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
+		raw_spin_lock_irqsave(&intc->lock, flags);
+		for (word = 0; word < intc->n_words; word++) {
+			l1_writel(intc->cpus[boot_cpu]->mask_cache[word],
+				intc->cpus[boot_cpu]->map_base +
+				reg_mask_set(intc, word));
+			l1_writel(~intc->cpus[boot_cpu]->mask_cache[word],
+				intc->cpus[boot_cpu]->map_base +
+				reg_mask_clr(intc, word));
+		}
+		raw_spin_unlock_irqrestore(&intc->lock, flags);
+	}
+}
+
+static struct syscore_ops bcm7038_l1_syscore_ops = {
+	.suspend	= bcm7038_l1_suspend,
+	.resume		= bcm7038_l1_resume,
+};
+
+static int bcm7038_l1_set_wake(struct irq_data *d, unsigned int on)
+{
+	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
+	unsigned long flags;
+	u32 word = d->hwirq / IRQS_PER_WORD;
+	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
+
+	raw_spin_lock_irqsave(&intc->lock, flags);
+	if (on)
+		intc->wake_mask[word] |= mask;
+	else
+		intc->wake_mask[word] &= ~mask;
+	raw_spin_unlock_irqrestore(&intc->lock, flags);
+
+	return 0;
+}
+#endif
+
 static struct irq_chip bcm7038_l1_irq_chip = {
 	.name			= "bcm7038-l1",
 	.irq_mask		= bcm7038_l1_mask,
@@ -295,6 +382,9 @@ static struct irq_chip bcm7038_l1_irq_chip = {
 #ifdef CONFIG_SMP
 	.irq_cpu_offline	= bcm7038_l1_cpu_offline,
 #endif
+#ifdef CONFIG_PM_SLEEP
+	.irq_set_wake		= bcm7038_l1_set_wake,
+#endif
 };
 
 static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq,
@@ -340,6 +430,14 @@ int __init bcm7038_l1_of_init(struct device_node *dn,
 		goto out_unmap;
 	}
 
+#ifdef CONFIG_PM_SLEEP
+	/* Add bcm7038_l1_chip into a list */
+	INIT_LIST_HEAD(&intc->list);
+	list_add_tail(&intc->list, &bcm7038_l1_intcs_list);
+
+	register_syscore_ops(&bcm7038_l1_syscore_ops);
+#endif
+
 	pr_info("registered BCM7038 L1 intc (%pOF, IRQs: %d)\n",
 		dn, IRQS_PER_WORD * intc->n_words);
 
-- 
2.17.1

[PATCH v2 2/5] dt-bindings: Document brcm,irq-can-wake for brcm,bcm7038-l1-intc.txt

[Florian Fainelli]

The BCM7038 L1 interrupt controller can be used as a wake-up interrupt
controller on MIPS and ARM-based systems, document the brcm,irq-can-wake
which has been "standardized" across Broadcom interrupt controllers.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 .../bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt   | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
index 2117d4ac1ae5..4eb043270f5b 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
@@ -31,6 +31,11 @@ Required properties:
 - interrupts: specifies the interrupt line(s) in the interrupt-parent controller
   node; valid values depend on the type of parent interrupt controller
 
+Optional properties:
+
+- brcm,irq-can-wake: If present, this means the L1 controller can be used as a
+  wakeup source for system suspend/resume.
+
 If multiple reg ranges and interrupt-parent entries are present on an SMP
 system, the driver will allow IRQ SMP affinity to be set up through the
 /proc/irq/ interface.  In the simplest possible configuration, only one
-- 
2.17.1

[PATCH v2 3/5] irqchip/irq-bcm7038-l1: Enable parent IRQ if necessary

[Florian Fainelli]

If the 'brcm,irq-can-wake' property is specified, make sure we also
enable the corresponding parent interrupt we are attached to.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 drivers/irqchip/irq-bcm7038-l1.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/irqchip/irq-bcm7038-l1.c b/drivers/irqchip/irq-bcm7038-l1.c
index f5e4ff5251ab..0673a44bbdc2 100644
--- a/drivers/irqchip/irq-bcm7038-l1.c
+++ b/drivers/irqchip/irq-bcm7038-l1.c
@@ -297,6 +297,10 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
 		pr_err("failed to map parent interrupt %d\n", parent_irq);
 		return -EINVAL;
 	}
+
+	if (of_property_read_bool(dn, "brcm,irq-can-wake"))
+		enable_irq_wake(parent_irq);
+
 	irq_set_chained_handler_and_data(parent_irq, bcm7038_l1_irq_handle,
 					 intc);
 
-- 
2.17.1

[PATCH v2 4/5] dt-bindings: Document brcm,int-fwd-mask property for bcm7038-l1-intc

[Florian Fainelli]

Indicate that the brcm,int-fwd-mask property is optional and can be
optionaly set on platforms which require to leave specific interrupts
untouched from Linux and retain the firmware configuration.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 .../bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt    | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
index 4eb043270f5b..31d31af408c5 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
@@ -36,6 +36,10 @@ Optional properties:
 - brcm,irq-can-wake: If present, this means the L1 controller can be used as a
   wakeup source for system suspend/resume.
 
+- brcm,int-fwd-mask: if present, a bit mask to indicate which interrupts
+  have already been configured by the firmware and should be left untouched.
+  This should have one 32-bit word per status/set/clear/mask group.
+
 If multiple reg ranges and interrupt-parent entries are present on an SMP
 system, the driver will allow IRQ SMP affinity to be set up through the
 /proc/irq/ interface.  In the simplest possible configuration, only one
-- 
2.17.1

[PATCH v2 5/5] irqchip/irq-bcm7038-l1: Support brcm,int-fwd-mask

[Florian Fainelli]

On some specific chips like 7211 we need to leave some interrupts
untouched/forwarded to the VPU which is another agent in the system
making use of that interrupt controller hardware (goes to both ARM GIC
and VPU L1 interrupt controller). Make that possible by using the
existing brcm,int-fwd-mask property.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 drivers/irqchip/irq-bcm7038-l1.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-bcm7038-l1.c b/drivers/irqchip/irq-bcm7038-l1.c
index 0673a44bbdc2..811a34201dd4 100644
--- a/drivers/irqchip/irq-bcm7038-l1.c
+++ b/drivers/irqchip/irq-bcm7038-l1.c
@@ -44,6 +44,7 @@ struct bcm7038_l1_chip {
 	struct list_head	list;
 	u32			wake_mask[MAX_WORDS];
 #endif
+	u32			irq_fwd_mask[MAX_WORDS];
 	u8			affinity[MAX_WORDS * IRQS_PER_WORD];
 };
 
@@ -265,6 +266,7 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
 	resource_size_t sz;
 	struct bcm7038_l1_cpu *cpu;
 	unsigned int i, n_words, parent_irq;
+	int ret;
 
 	if (of_address_to_resource(dn, idx, &res))
 		return -EINVAL;
@@ -278,6 +280,14 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
 	else if (intc->n_words != n_words)
 		return -EINVAL;
 
+	ret = of_property_read_u32_array(dn , "brcm,int-fwd-mask",
+					 intc->irq_fwd_mask, n_words);
+	if (ret != 0 && ret != -EINVAL) {
+		/* property exists but has the wrong number of words */
+		pr_err("invalid brcm,int-fwd-mask property\n");
+		return -EINVAL;
+	}
+
 	cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
 					GFP_KERNEL);
 	if (!cpu)
@@ -288,8 +298,9 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
 		return -ENOMEM;
 
 	for (i = 0; i < n_words; i++) {
-		l1_writel(0xffffffff, cpu->map_base + reg_mask_set(intc, i));
-		cpu->mask_cache[i] = 0xffffffff;
+		l1_writel(0xffffffff & ~intc->irq_fwd_mask[i],
+			  cpu->map_base + reg_mask_set(intc, i));
+		cpu->mask_cache[i] = 0xffffffff & ~intc->irq_fwd_mask[i];
 	}
 
 	parent_irq = irq_of_parse_and_map(dn, idx);
-- 
2.17.1

Re: [PATCH v2 1/5] irqchip/irq-bcm7038-l1: Add PM support

[Marc Zyngier]

On Fri, 13 Sep 2019 12:15:38 -0700
Florian Fainelli <f.fainelli@gmail.com> wrote:

> From: Justin Chen <justinpopo6@gmail.com>
> 
> The current l1 controller does not mask any interrupts when dropping
> into suspend. This mean we can receive unexpected wake up sources.
> Modified MIPS l1 controller to mask the all non-wake interrupts before
> dropping into suspend.
> 
> Signed-off-by: Justin Chen <justinpopo6@gmail.com>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
>  drivers/irqchip/irq-bcm7038-l1.c | 98 ++++++++++++++++++++++++++++++++
>  1 file changed, 98 insertions(+)
> 
> diff --git a/drivers/irqchip/irq-bcm7038-l1.c b/drivers/irqchip/irq-bcm7038-l1.c
> index fc75c61233aa..f5e4ff5251ab 100644
> --- a/drivers/irqchip/irq-bcm7038-l1.c
> +++ b/drivers/irqchip/irq-bcm7038-l1.c
> @@ -27,6 +27,7 @@
>  #include <linux/types.h>
>  #include <linux/irqchip.h>
>  #include <linux/irqchip/chained_irq.h>
> +#include <linux/syscore_ops.h>
>  
>  #define IRQS_PER_WORD		32
>  #define REG_BYTES_PER_IRQ_WORD	(sizeof(u32) * 4)
> @@ -39,6 +40,10 @@ struct bcm7038_l1_chip {
>  	unsigned int		n_words;
>  	struct irq_domain	*domain;
>  	struct bcm7038_l1_cpu	*cpus[NR_CPUS];
> +#ifdef CONFIG_PM_SLEEP
> +	struct list_head	list;
> +	u32			wake_mask[MAX_WORDS];
> +#endif
>  	u8			affinity[MAX_WORDS * IRQS_PER_WORD];
>  };
>  
> @@ -47,6 +52,17 @@ struct bcm7038_l1_cpu {
>  	u32			mask_cache[0];
>  };
>  
> +/*
> + * We keep a list of bcm7038_l1_chip used for suspend/resume. This hack is
> + * used because the struct chip_type suspend/resume hooks are not called
> + * unless chip_type is hooked onto a generic_chip. Since this driver does
> + * not use generic_chip, we need to manually hook our resume/suspend to
> + * syscore_ops.
> + */
> +#ifdef CONFIG_PM_SLEEP
> +static LIST_HEAD(bcm7038_l1_intcs_list);
> +#endif

nit: this could be moved down to be close to the rest of the PM_SLEEP
ifdefery.

> +
>  /*
>   * STATUS/MASK_STATUS/MASK_SET/MASK_CLEAR are packed one right after another:
>   *
> @@ -287,6 +303,77 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
>  	return 0;
>  }
>  
> +#ifdef CONFIG_PM_SLEEP
> +static int bcm7038_l1_suspend(void)
> +{
> +	struct bcm7038_l1_chip *intc;
> +	unsigned long flags;
> +	int boot_cpu, word;
> +
> +	/* Wakeup interrupt should only come from the boot cpu */
> +	boot_cpu = cpu_logical_map(smp_processor_id());

What guarantees that you're actually running on the boot CPU at this
point? If that's actually the case, why isn't cpu_logical_map(0) enough?

> +
> +	list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
> +		raw_spin_lock_irqsave(&intc->lock, flags);

And if this can only run on a single CPU, what's the purpose of this
lock?

> +		for (word = 0; word < intc->n_words; word++) {
> +			l1_writel(~intc->wake_mask[word],
> +				intc->cpus[boot_cpu]->map_base +
> +				reg_mask_set(intc, word));
> +			l1_writel(intc->wake_mask[word],
> +				intc->cpus[boot_cpu]->map_base +
> +				reg_mask_clr(intc, word));

nit: Please don't split the write address across two lines, it makes it
harder to read.

> +		}
> +		raw_spin_unlock_irqrestore(&intc->lock, flags);
> +	}
> +
> +	return 0;
> +}
> +
> +static void bcm7038_l1_resume(void)
> +{
> +	struct bcm7038_l1_chip *intc;
> +	unsigned long flags;
> +	int boot_cpu, word;
> +
> +	boot_cpu = cpu_logical_map(smp_processor_id());
> +
> +	list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
> +		raw_spin_lock_irqsave(&intc->lock, flags);
> +		for (word = 0; word < intc->n_words; word++) {
> +			l1_writel(intc->cpus[boot_cpu]->mask_cache[word],
> +				intc->cpus[boot_cpu]->map_base +
> +				reg_mask_set(intc, word));
> +			l1_writel(~intc->cpus[boot_cpu]->mask_cache[word],
> +				intc->cpus[boot_cpu]->map_base +
> +				reg_mask_clr(intc, word));
> +		}
> +		raw_spin_unlock_irqrestore(&intc->lock, flags);
> +	}
> +}
> +
> +static struct syscore_ops bcm7038_l1_syscore_ops = {
> +	.suspend	= bcm7038_l1_suspend,
> +	.resume		= bcm7038_l1_resume,
> +};
> +
> +static int bcm7038_l1_set_wake(struct irq_data *d, unsigned int on)
> +{
> +	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
> +	unsigned long flags;
> +	u32 word = d->hwirq / IRQS_PER_WORD;
> +	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
> +
> +	raw_spin_lock_irqsave(&intc->lock, flags);
> +	if (on)
> +		intc->wake_mask[word] |= mask;
> +	else
> +		intc->wake_mask[word] &= ~mask;
> +	raw_spin_unlock_irqrestore(&intc->lock, flags);
> +
> +	return 0;
> +}
> +#endif
> +
>  static struct irq_chip bcm7038_l1_irq_chip = {
>  	.name			= "bcm7038-l1",
>  	.irq_mask		= bcm7038_l1_mask,
> @@ -295,6 +382,9 @@ static struct irq_chip bcm7038_l1_irq_chip = {
>  #ifdef CONFIG_SMP
>  	.irq_cpu_offline	= bcm7038_l1_cpu_offline,
>  #endif
> +#ifdef CONFIG_PM_SLEEP
> +	.irq_set_wake		= bcm7038_l1_set_wake,
> +#endif
>  };
>  
>  static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq,
> @@ -340,6 +430,14 @@ int __init bcm7038_l1_of_init(struct device_node *dn,
>  		goto out_unmap;
>  	}
>  
> +#ifdef CONFIG_PM_SLEEP
> +	/* Add bcm7038_l1_chip into a list */
> +	INIT_LIST_HEAD(&intc->list);
> +	list_add_tail(&intc->list, &bcm7038_l1_intcs_list);

No locking to manipulate this list? Is that safe?

> +
> +	register_syscore_ops(&bcm7038_l1_syscore_ops);

Do you really register the syscore_ops for each and every L1 irqchip?

> +#endif
> +
>  	pr_info("registered BCM7038 L1 intc (%pOF, IRQs: %d)\n",
>  		dn, IRQS_PER_WORD * intc->n_words);
>  

Thanks,

	M.
-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH v2 5/5] irqchip/irq-bcm7038-l1: Support brcm,int-fwd-mask

[Marc Zyngier]

On Fri, 13 Sep 2019 12:15:42 -0700
Florian Fainelli <f.fainelli@gmail.com> wrote:

> On some specific chips like 7211 we need to leave some interrupts
> untouched/forwarded to the VPU which is another agent in the system
> making use of that interrupt controller hardware (goes to both ARM GIC
> and VPU L1 interrupt controller). Make that possible by using the
> existing brcm,int-fwd-mask property.
> 
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
>  drivers/irqchip/irq-bcm7038-l1.c | 15 +++++++++++++--
>  1 file changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-bcm7038-l1.c b/drivers/irqchip/irq-bcm7038-l1.c
> index 0673a44bbdc2..811a34201dd4 100644
> --- a/drivers/irqchip/irq-bcm7038-l1.c
> +++ b/drivers/irqchip/irq-bcm7038-l1.c
> @@ -44,6 +44,7 @@ struct bcm7038_l1_chip {
>  	struct list_head	list;
>  	u32			wake_mask[MAX_WORDS];
>  #endif
> +	u32			irq_fwd_mask[MAX_WORDS];
>  	u8			affinity[MAX_WORDS * IRQS_PER_WORD];
>  };
>  
> @@ -265,6 +266,7 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
>  	resource_size_t sz;
>  	struct bcm7038_l1_cpu *cpu;
>  	unsigned int i, n_words, parent_irq;
> +	int ret;
>  
>  	if (of_address_to_resource(dn, idx, &res))
>  		return -EINVAL;
> @@ -278,6 +280,14 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
>  	else if (intc->n_words != n_words)
>  		return -EINVAL;
>  
> +	ret = of_property_read_u32_array(dn , "brcm,int-fwd-mask",

What is the exact meaning of "fwd"? Forward? FirmWare Dementia?

> +					 intc->irq_fwd_mask, n_words);
> +	if (ret != 0 && ret != -EINVAL) {
> +		/* property exists but has the wrong number of words */
> +		pr_err("invalid brcm,int-fwd-mask property\n");
> +		return -EINVAL;
> +	}
> +
>  	cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
>  					GFP_KERNEL);
>  	if (!cpu)
> @@ -288,8 +298,9 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
>  		return -ENOMEM;
>  
>  	for (i = 0; i < n_words; i++) {
> -		l1_writel(0xffffffff, cpu->map_base + reg_mask_set(intc, i));
> -		cpu->mask_cache[i] = 0xffffffff;
> +		l1_writel(0xffffffff & ~intc->irq_fwd_mask[i],
> +			  cpu->map_base + reg_mask_set(intc, i));
> +		cpu->mask_cache[i] = 0xffffffff & ~intc->irq_fwd_mask[i];

I seem to remember that (0xffffffff & whatever) == whatever, as long as
'whatever' is a 32bit quantity. So what it this for?

	M.
-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH v2 1/5] irqchip/irq-bcm7038-l1: Add PM support

[Florian Fainelli]

On 9/22/2019 5:31 AM, Marc Zyngier wrote:
>> +#ifdef CONFIG_PM_SLEEP
>> +static int bcm7038_l1_suspend(void)
>> +{
>> +	struct bcm7038_l1_chip *intc;
>> +	unsigned long flags;
>> +	int boot_cpu, word;
>> +
>> +	/* Wakeup interrupt should only come from the boot cpu */
>> +	boot_cpu = cpu_logical_map(smp_processor_id());
> 
> What guarantees that you're actually running on the boot CPU at this
> point? If that's actually the case, why isn't cpu_logical_map(0) enough?

This is executed from syscore_suspend() which is executed after
suspend_disable_secondary_cpus(), so we are guaranteed to be
uni-processor at that point. Good point about using 0 for addressing the
boot CPU.

> 
>> +
>> +	list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
>> +		raw_spin_lock_irqsave(&intc->lock, flags);
> 
> And if this can only run on a single CPU, what's the purpose of this
> lock?

Humm, yes, we probably do not need that lock, syscore_suspend() is after
arch_suspend_disable_irqs().

> 
>> +		for (word = 0; word < intc->n_words; word++) {
>> +			l1_writel(~intc->wake_mask[word],
>> +				intc->cpus[boot_cpu]->map_base +
>> +				reg_mask_set(intc, word));
>> +			l1_writel(intc->wake_mask[word],
>> +				intc->cpus[boot_cpu]->map_base +
>> +				reg_mask_clr(intc, word));
> 
> nit: Please don't split the write address across two lines, it makes it
> harder to read.
> 
>> +		}
>> +		raw_spin_unlock_irqrestore(&intc->lock, flags);
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static void bcm7038_l1_resume(void)
>> +{
>> +	struct bcm7038_l1_chip *intc;
>> +	unsigned long flags;
>> +	int boot_cpu, word;
>> +
>> +	boot_cpu = cpu_logical_map(smp_processor_id());
>> +
>> +	list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
>> +		raw_spin_lock_irqsave(&intc->lock, flags);
>> +		for (word = 0; word < intc->n_words; word++) {
>> +			l1_writel(intc->cpus[boot_cpu]->mask_cache[word],
>> +				intc->cpus[boot_cpu]->map_base +
>> +				reg_mask_set(intc, word));
>> +			l1_writel(~intc->cpus[boot_cpu]->mask_cache[word],
>> +				intc->cpus[boot_cpu]->map_base +
>> +				reg_mask_clr(intc, word));
>> +		}
>> +		raw_spin_unlock_irqrestore(&intc->lock, flags);
>> +	}
>> +}
>> +
>> +static struct syscore_ops bcm7038_l1_syscore_ops = {
>> +	.suspend	= bcm7038_l1_suspend,
>> +	.resume		= bcm7038_l1_resume,
>> +};
>> +
>> +static int bcm7038_l1_set_wake(struct irq_data *d, unsigned int on)
>> +{
>> +	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
>> +	unsigned long flags;
>> +	u32 word = d->hwirq / IRQS_PER_WORD;
>> +	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
>> +
>> +	raw_spin_lock_irqsave(&intc->lock, flags);
>> +	if (on)
>> +		intc->wake_mask[word] |= mask;
>> +	else
>> +		intc->wake_mask[word] &= ~mask;
>> +	raw_spin_unlock_irqrestore(&intc->lock, flags);
>> +
>> +	return 0;
>> +}
>> +#endif
>> +
>>  static struct irq_chip bcm7038_l1_irq_chip = {
>>  	.name			= "bcm7038-l1",
>>  	.irq_mask		= bcm7038_l1_mask,
>> @@ -295,6 +382,9 @@ static struct irq_chip bcm7038_l1_irq_chip = {
>>  #ifdef CONFIG_SMP
>>  	.irq_cpu_offline	= bcm7038_l1_cpu_offline,
>>  #endif
>> +#ifdef CONFIG_PM_SLEEP
>> +	.irq_set_wake		= bcm7038_l1_set_wake,
>> +#endif
>>  };
>>  
>>  static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq,
>> @@ -340,6 +430,14 @@ int __init bcm7038_l1_of_init(struct device_node *dn,
>>  		goto out_unmap;
>>  	}
>>  
>> +#ifdef CONFIG_PM_SLEEP
>> +	/* Add bcm7038_l1_chip into a list */
>> +	INIT_LIST_HEAD(&intc->list);
>> +	list_add_tail(&intc->list, &bcm7038_l1_intcs_list);
> 
> No locking to manipulate this list? Is that safe?

It is safe, by virtue of of_irq_init() having being called at init_IRQ()
and that interrupt controller being initialized early on boot, but it
does not feel safe to assume that, I will add relevant protection to the
list.

> 
>> +
>> +	register_syscore_ops(&bcm7038_l1_syscore_ops);
> 
> Do you really register the syscore_ops for each and every L1 irqchip?

We do not need, indeed thanks, I will fix those things in v3.
-- 
Florian

Re: [PATCH v2 5/5] irqchip/irq-bcm7038-l1: Support brcm,int-fwd-mask

[Florian Fainelli]

On 9/22/2019 5:38 AM, Marc Zyngier wrote:
> On Fri, 13 Sep 2019 12:15:42 -0700
> Florian Fainelli <f.fainelli@gmail.com> wrote:
> 
>> On some specific chips like 7211 we need to leave some interrupts
>> untouched/forwarded to the VPU which is another agent in the system
>> making use of that interrupt controller hardware (goes to both ARM GIC
>> and VPU L1 interrupt controller). Make that possible by using the
>> existing brcm,int-fwd-mask property.
>>
>> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
>> ---
>>  drivers/irqchip/irq-bcm7038-l1.c | 15 +++++++++++++--
>>  1 file changed, 13 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/irqchip/irq-bcm7038-l1.c b/drivers/irqchip/irq-bcm7038-l1.c
>> index 0673a44bbdc2..811a34201dd4 100644
>> --- a/drivers/irqchip/irq-bcm7038-l1.c
>> +++ b/drivers/irqchip/irq-bcm7038-l1.c
>> @@ -44,6 +44,7 @@ struct bcm7038_l1_chip {
>>  	struct list_head	list;
>>  	u32			wake_mask[MAX_WORDS];
>>  #endif
>> +	u32			irq_fwd_mask[MAX_WORDS];
>>  	u8			affinity[MAX_WORDS * IRQS_PER_WORD];
>>  };
>>  
>> @@ -265,6 +266,7 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
>>  	resource_size_t sz;
>>  	struct bcm7038_l1_cpu *cpu;
>>  	unsigned int i, n_words, parent_irq;
>> +	int ret;
>>  
>>  	if (of_address_to_resource(dn, idx, &res))
>>  		return -EINVAL;
>> @@ -278,6 +280,14 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
>>  	else if (intc->n_words != n_words)
>>  		return -EINVAL;
>>  
>> +	ret = of_property_read_u32_array(dn , "brcm,int-fwd-mask",
> 
> What is the exact meaning of "fwd"? Forward? FirmWare Dementia?

Here it is meant to be "forward", we have defined this property name
before for irq-bcm7120-l2.c and felt like reusing the same name to avoid
multiplying properties would be appropriate, see patch #4. If you prefer
something named brcm,firmware-configured-mask, let me know.

> 
>> +					 intc->irq_fwd_mask, n_words);
>> +	if (ret != 0 && ret != -EINVAL) {
>> +		/* property exists but has the wrong number of words */
>> +		pr_err("invalid brcm,int-fwd-mask property\n");
>> +		return -EINVAL;
>> +	}
>> +
>>  	cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
>>  					GFP_KERNEL);
>>  	if (!cpu)
>> @@ -288,8 +298,9 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
>>  		return -ENOMEM;
>>  
>>  	for (i = 0; i < n_words; i++) {
>> -		l1_writel(0xffffffff, cpu->map_base + reg_mask_set(intc, i));
>> -		cpu->mask_cache[i] = 0xffffffff;
>> +		l1_writel(0xffffffff & ~intc->irq_fwd_mask[i],
>> +			  cpu->map_base + reg_mask_set(intc, i));
>> +		cpu->mask_cache[i] = 0xffffffff & ~intc->irq_fwd_mask[i];
> 
> I seem to remember that (0xffffffff & whatever) == whatever, as long as
> 'whatever' is a 32bit quantity. So what it this for?

It is 0xffff_ffff & ~whatever here. In the absence of this property
being specified, the data is all zeroed out, so we would have
0xffff_ffff & 0xffff_ffff which is 0xffff_ffff. If this property is
specified, we would have one more or bits set, and it would be e.g.:
0x100 so we would have 0xffff_ffff & ~(0x100) = 0xffff_feff which is
what we would want here to preserve whatever the firmware has already
configured. In hindsight, it may be safer to make sure no one in Linux
can actually map that interrupt, so we would need something like this in
addition to what we already have in this patch:

diff --git a/drivers/irqchip/irq-bcm7038-l1.c
b/drivers/irqchip/irq-bcm7038-l1.c
index fc75c61233aa..558e74be0d60 100644
--- a/drivers/irqchip/irq-bcm7038-l1.c
+++ b/drivers/irqchip/irq-bcm7038-l1.c
@@ -300,6 +300,14 @@ static struct irq_chip bcm7038_l1_irq_chip = {
 static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq,
                          irq_hw_number_t hw_irq)
 {
+       struct bcm7038_l1_chip *intc = d->host_data;
+       int i;
+
+       for (i = 0; i < intc->n_words; i++) {
+               if (intc->irq_fwd_mask[i] & BIT(hw_irq))
+                       return -EINVAL;
+       }
+
        irq_set_chip_and_handler(virq, &bcm7038_l1_irq_chip,
handle_level_irq);
        irq_set_chip_data(virq, d->host_data);
        irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
-- 
Florian

Re: [PATCH v2 5/5] irqchip/irq-bcm7038-l1: Support brcm,int-fwd-mask

[Marc Zyngier]

On 22/09/2019 20:08, Florian Fainelli wrote:
> 
> 
> On 9/22/2019 5:38 AM, Marc Zyngier wrote:
>> On Fri, 13 Sep 2019 12:15:42 -0700
>> Florian Fainelli <f.fainelli@gmail.com> wrote:
>>
>>> On some specific chips like 7211 we need to leave some interrupts
>>> untouched/forwarded to the VPU which is another agent in the system
>>> making use of that interrupt controller hardware (goes to both ARM GIC
>>> and VPU L1 interrupt controller). Make that possible by using the
>>> existing brcm,int-fwd-mask property.
>>>
>>> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
>>> ---
>>>  drivers/irqchip/irq-bcm7038-l1.c | 15 +++++++++++++--
>>>  1 file changed, 13 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/irqchip/irq-bcm7038-l1.c b/drivers/irqchip/irq-bcm7038-l1.c
>>> index 0673a44bbdc2..811a34201dd4 100644
>>> --- a/drivers/irqchip/irq-bcm7038-l1.c
>>> +++ b/drivers/irqchip/irq-bcm7038-l1.c
>>> @@ -44,6 +44,7 @@ struct bcm7038_l1_chip {
>>>  	struct list_head	list;
>>>  	u32			wake_mask[MAX_WORDS];
>>>  #endif
>>> +	u32			irq_fwd_mask[MAX_WORDS];
>>>  	u8			affinity[MAX_WORDS * IRQS_PER_WORD];
>>>  };
>>>  
>>> @@ -265,6 +266,7 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
>>>  	resource_size_t sz;
>>>  	struct bcm7038_l1_cpu *cpu;
>>>  	unsigned int i, n_words, parent_irq;
>>> +	int ret;
>>>  
>>>  	if (of_address_to_resource(dn, idx, &res))
>>>  		return -EINVAL;
>>> @@ -278,6 +280,14 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
>>>  	else if (intc->n_words != n_words)
>>>  		return -EINVAL;
>>>  
>>> +	ret = of_property_read_u32_array(dn , "brcm,int-fwd-mask",
>>
>> What is the exact meaning of "fwd"? Forward? FirmWare Dementia?
> 
> Here it is meant to be "forward", we have defined this property name
> before for irq-bcm7120-l2.c and felt like reusing the same name to avoid
> multiplying properties would be appropriate, see patch #4. If you prefer
> something named brcm,firmware-configured-mask, let me know.

It's just a name, but I found it a bit confusing. Bah, never mind.

>>
>>> +					 intc->irq_fwd_mask, n_words);
>>> +	if (ret != 0 && ret != -EINVAL) {
>>> +		/* property exists but has the wrong number of words */
>>> +		pr_err("invalid brcm,int-fwd-mask property\n");
>>> +		return -EINVAL;
>>> +	}
>>> +
>>>  	cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
>>>  					GFP_KERNEL);
>>>  	if (!cpu)
>>> @@ -288,8 +298,9 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
>>>  		return -ENOMEM;
>>>  
>>>  	for (i = 0; i < n_words; i++) {
>>> -		l1_writel(0xffffffff, cpu->map_base + reg_mask_set(intc, i));
>>> -		cpu->mask_cache[i] = 0xffffffff;
>>> +		l1_writel(0xffffffff & ~intc->irq_fwd_mask[i],
>>> +			  cpu->map_base + reg_mask_set(intc, i));
>>> +		cpu->mask_cache[i] = 0xffffffff & ~intc->irq_fwd_mask[i];
>>
>> I seem to remember that (0xffffffff & whatever) == whatever, as long as
>> 'whatever' is a 32bit quantity. So what it this for?
> 
> It is 0xffff_ffff & ~whatever here.

Which doesn't change anything.

> In the absence of this property
> being specified, the data is all zeroed out, so we would have
> 0xffff_ffff & 0xffff_ffff which is 0xffff_ffff. If this property is
> specified, we would have one more or bits set, and it would be e.g.:
> 0x100 so we would have 0xffff_ffff & ~(0x100) = 0xffff_feff which is
> what we would want here to preserve whatever the firmware has already
> configured.

OK, I must be stupid:

#include <stdio.h>

int main(int argc, char *argv[])
{
	unsigned int v = 0x100;
	printf ("%x\n", ~v);
}
maz@filthy-habit$ ./x
fffffeff

You might as well OR it with zeroes, if you want.

	M.
-- 
Jazz is not dead, it just smells funny...

Re: [PATCH v2 5/5] irqchip/irq-bcm7038-l1: Support brcm,int-fwd-mask

[Florian Fainelli]

On 9/23/2019 1:52 AM, Marc Zyngier wrote:
> On 22/09/2019 20:08, Florian Fainelli wrote:
>>
>>
>> On 9/22/2019 5:38 AM, Marc Zyngier wrote:
>>> On Fri, 13 Sep 2019 12:15:42 -0700
>>> Florian Fainelli <f.fainelli@gmail.com> wrote:
>>>
>>>> On some specific chips like 7211 we need to leave some interrupts
>>>> untouched/forwarded to the VPU which is another agent in the system
>>>> making use of that interrupt controller hardware (goes to both ARM GIC
>>>> and VPU L1 interrupt controller). Make that possible by using the
>>>> existing brcm,int-fwd-mask property.
>>>>
>>>> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
>>>> ---
>>>>  drivers/irqchip/irq-bcm7038-l1.c | 15 +++++++++++++--
>>>>  1 file changed, 13 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/irqchip/irq-bcm7038-l1.c b/drivers/irqchip/irq-bcm7038-l1.c
>>>> index 0673a44bbdc2..811a34201dd4 100644
>>>> --- a/drivers/irqchip/irq-bcm7038-l1.c
>>>> +++ b/drivers/irqchip/irq-bcm7038-l1.c
>>>> @@ -44,6 +44,7 @@ struct bcm7038_l1_chip {
>>>>  	struct list_head	list;
>>>>  	u32			wake_mask[MAX_WORDS];
>>>>  #endif
>>>> +	u32			irq_fwd_mask[MAX_WORDS];
>>>>  	u8			affinity[MAX_WORDS * IRQS_PER_WORD];
>>>>  };
>>>>  
>>>> @@ -265,6 +266,7 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
>>>>  	resource_size_t sz;
>>>>  	struct bcm7038_l1_cpu *cpu;
>>>>  	unsigned int i, n_words, parent_irq;
>>>> +	int ret;
>>>>  
>>>>  	if (of_address_to_resource(dn, idx, &res))
>>>>  		return -EINVAL;
>>>> @@ -278,6 +280,14 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
>>>>  	else if (intc->n_words != n_words)
>>>>  		return -EINVAL;
>>>>  
>>>> +	ret = of_property_read_u32_array(dn , "brcm,int-fwd-mask",
>>>
>>> What is the exact meaning of "fwd"? Forward? FirmWare Dementia?
>>
>> Here it is meant to be "forward", we have defined this property name
>> before for irq-bcm7120-l2.c and felt like reusing the same name to avoid
>> multiplying properties would be appropriate, see patch #4. If you prefer
>> something named brcm,firmware-configured-mask, let me know.
> 
> It's just a name, but I found it a bit confusing. Bah, never mind.
> 
>>>
>>>> +					 intc->irq_fwd_mask, n_words);
>>>> +	if (ret != 0 && ret != -EINVAL) {
>>>> +		/* property exists but has the wrong number of words */
>>>> +		pr_err("invalid brcm,int-fwd-mask property\n");
>>>> +		return -EINVAL;
>>>> +	}
>>>> +
>>>>  	cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
>>>>  					GFP_KERNEL);
>>>>  	if (!cpu)
>>>> @@ -288,8 +298,9 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
>>>>  		return -ENOMEM;
>>>>  
>>>>  	for (i = 0; i < n_words; i++) {
>>>> -		l1_writel(0xffffffff, cpu->map_base + reg_mask_set(intc, i));
>>>> -		cpu->mask_cache[i] = 0xffffffff;
>>>> +		l1_writel(0xffffffff & ~intc->irq_fwd_mask[i],
>>>> +			  cpu->map_base + reg_mask_set(intc, i));
>>>> +		cpu->mask_cache[i] = 0xffffffff & ~intc->irq_fwd_mask[i];
>>>
>>> I seem to remember that (0xffffffff & whatever) == whatever, as long as
>>> 'whatever' is a 32bit quantity. So what it this for?
>>
>> It is 0xffff_ffff & ~whatever here.
> 
> Which doesn't change anything.
> 
>> In the absence of this property
>> being specified, the data is all zeroed out, so we would have
>> 0xffff_ffff & 0xffff_ffff which is 0xffff_ffff. If this property is
>> specified, we would have one more or bits set, and it would be e.g.:
>> 0x100 so we would have 0xffff_ffff & ~(0x100) = 0xffff_feff which is
>> what we would want here to preserve whatever the firmware has already
>> configured.
> 
> OK, I must be stupid:
> 
> #include <stdio.h>
> 
> int main(int argc, char *argv[])
> {
> 	unsigned int v = 0x100;
> 	printf ("%x\n", ~v);
> }
> maz@filthy-habit$ ./x
> fffffeff
> 
> You might as well OR it with zeroes, if you want.

Not sure I understand your point here.

We used to write 0xffff_ffff to both the hardware and the mask cache to
have all interrupts masked by default. Now we want to have some bits
optionally set to 0 (unmasked), based on the brcm,int-fwd-mask property,
which is what this patch achieves (or tries to). If we write, say
0xffff_feff to the hardware, which has a Write Only register behavior,
then we also want to have the mask cache be set to the same value for
consistency if nothing else. Am I failing at doing what I just described
and also failing at see it?
-- 
Florian

Re: [PATCH v2 5/5] irqchip/irq-bcm7038-l1: Support brcm,int-fwd-mask

[Marc Zyngier]

On 23/09/2019 15:39, Florian Fainelli wrote:
> 
> 
> On 9/23/2019 1:52 AM, Marc Zyngier wrote:
>> On 22/09/2019 20:08, Florian Fainelli wrote:
>>>
>>>
>>> On 9/22/2019 5:38 AM, Marc Zyngier wrote:
>>>> On Fri, 13 Sep 2019 12:15:42 -0700
>>>> Florian Fainelli <f.fainelli@gmail.com> wrote:
>>>>
>>>>> On some specific chips like 7211 we need to leave some interrupts
>>>>> untouched/forwarded to the VPU which is another agent in the system
>>>>> making use of that interrupt controller hardware (goes to both ARM GIC
>>>>> and VPU L1 interrupt controller). Make that possible by using the
>>>>> existing brcm,int-fwd-mask property.
>>>>>
>>>>> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
>>>>> ---
>>>>>  drivers/irqchip/irq-bcm7038-l1.c | 15 +++++++++++++--
>>>>>  1 file changed, 13 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/drivers/irqchip/irq-bcm7038-l1.c b/drivers/irqchip/irq-bcm7038-l1.c
>>>>> index 0673a44bbdc2..811a34201dd4 100644
>>>>> --- a/drivers/irqchip/irq-bcm7038-l1.c
>>>>> +++ b/drivers/irqchip/irq-bcm7038-l1.c
>>>>> @@ -44,6 +44,7 @@ struct bcm7038_l1_chip {
>>>>>  	struct list_head	list;
>>>>>  	u32			wake_mask[MAX_WORDS];
>>>>>  #endif
>>>>> +	u32			irq_fwd_mask[MAX_WORDS];
>>>>>  	u8			affinity[MAX_WORDS * IRQS_PER_WORD];
>>>>>  };
>>>>>  
>>>>> @@ -265,6 +266,7 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
>>>>>  	resource_size_t sz;
>>>>>  	struct bcm7038_l1_cpu *cpu;
>>>>>  	unsigned int i, n_words, parent_irq;
>>>>> +	int ret;
>>>>>  
>>>>>  	if (of_address_to_resource(dn, idx, &res))
>>>>>  		return -EINVAL;
>>>>> @@ -278,6 +280,14 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
>>>>>  	else if (intc->n_words != n_words)
>>>>>  		return -EINVAL;
>>>>>  
>>>>> +	ret = of_property_read_u32_array(dn , "brcm,int-fwd-mask",
>>>>
>>>> What is the exact meaning of "fwd"? Forward? FirmWare Dementia?
>>>
>>> Here it is meant to be "forward", we have defined this property name
>>> before for irq-bcm7120-l2.c and felt like reusing the same name to avoid
>>> multiplying properties would be appropriate, see patch #4. If you prefer
>>> something named brcm,firmware-configured-mask, let me know.
>>
>> It's just a name, but I found it a bit confusing. Bah, never mind.
>>
>>>>
>>>>> +					 intc->irq_fwd_mask, n_words);
>>>>> +	if (ret != 0 && ret != -EINVAL) {
>>>>> +		/* property exists but has the wrong number of words */
>>>>> +		pr_err("invalid brcm,int-fwd-mask property\n");
>>>>> +		return -EINVAL;
>>>>> +	}
>>>>> +
>>>>>  	cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
>>>>>  					GFP_KERNEL);
>>>>>  	if (!cpu)
>>>>> @@ -288,8 +298,9 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
>>>>>  		return -ENOMEM;
>>>>>  
>>>>>  	for (i = 0; i < n_words; i++) {
>>>>> -		l1_writel(0xffffffff, cpu->map_base + reg_mask_set(intc, i));
>>>>> -		cpu->mask_cache[i] = 0xffffffff;
>>>>> +		l1_writel(0xffffffff & ~intc->irq_fwd_mask[i],
>>>>> +			  cpu->map_base + reg_mask_set(intc, i));
>>>>> +		cpu->mask_cache[i] = 0xffffffff & ~intc->irq_fwd_mask[i];
>>>>
>>>> I seem to remember that (0xffffffff & whatever) == whatever, as long as
>>>> 'whatever' is a 32bit quantity. So what it this for?
>>>
>>> It is 0xffff_ffff & ~whatever here.
>>
>> Which doesn't change anything.
>>
>>> In the absence of this property
>>> being specified, the data is all zeroed out, so we would have
>>> 0xffff_ffff & 0xffff_ffff which is 0xffff_ffff. If this property is
>>> specified, we would have one more or bits set, and it would be e.g.:
>>> 0x100 so we would have 0xffff_ffff & ~(0x100) = 0xffff_feff which is
>>> what we would want here to preserve whatever the firmware has already
>>> configured.
>>
>> OK, I must be stupid:
>>
>> #include <stdio.h>
>>
>> int main(int argc, char *argv[])
>> {
>> 	unsigned int v = 0x100;
>> 	printf ("%x\n", ~v);
>> }
>> maz@filthy-habit$ ./x
>> fffffeff
>>
>> You might as well OR it with zeroes, if you want.
> 
> Not sure I understand your point here.
> 
> We used to write 0xffff_ffff to both the hardware and the mask cache to
> have all interrupts masked by default. Now we want to have some bits
> optionally set to 0 (unmasked), based on the brcm,int-fwd-mask property,
> which is what this patch achieves (or tries to). If we write, say
> 0xffff_feff to the hardware, which has a Write Only register behavior,
> then we also want to have the mask cache be set to the same value for
> consistency if nothing else. Am I failing at doing what I just described
> and also failing at see it?

You write this:

>  	for (i = 0; i < n_words; i++) {
> -		l1_writel(0xffffffff, cpu->map_base + reg_mask_set(intc, i));
> -		cpu->mask_cache[i] = 0xffffffff;
> +		l1_writel(0xffffffff & ~intc->irq_fwd_mask[i],
> +			  cpu->map_base + reg_mask_set(intc, i));
> +		cpu->mask_cache[i] = 0xffffffff & ~intc->irq_fwd_mask[i];
>  	}

And I'm saying that this is strictly equivalent to:

 	for (i = 0; i < n_words; i++) {
		l1_writel(~intc->irq_fwd_mask[i],
			  cpu->map_base + reg_mask_set(intc, i));
		cpu->mask_cache[i] = ~intc->irq_fwd_mask[i];
 	}

without this 0xffffffff that does exactly nothing (I'm pretty sure the
compiler drops it anyway).

	M.
-- 
Jazz is not dead, it just smells funny...

Re: [PATCH v2 5/5] irqchip/irq-bcm7038-l1: Support brcm,int-fwd-mask

[Florian Fainelli]

On 9/23/2019 7:57 AM, Marc Zyngier wrote:
> On 23/09/2019 15:39, Florian Fainelli wrote:
>>
>>
>> On 9/23/2019 1:52 AM, Marc Zyngier wrote:
>>> On 22/09/2019 20:08, Florian Fainelli wrote:
>>>>
>>>>
>>>> On 9/22/2019 5:38 AM, Marc Zyngier wrote:
>>>>> On Fri, 13 Sep 2019 12:15:42 -0700
>>>>> Florian Fainelli <f.fainelli@gmail.com> wrote:
>>>>>
>>>>>> On some specific chips like 7211 we need to leave some interrupts
>>>>>> untouched/forwarded to the VPU which is another agent in the system
>>>>>> making use of that interrupt controller hardware (goes to both ARM GIC
>>>>>> and VPU L1 interrupt controller). Make that possible by using the
>>>>>> existing brcm,int-fwd-mask property.
>>>>>>
>>>>>> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
>>>>>> ---
>>>>>>  drivers/irqchip/irq-bcm7038-l1.c | 15 +++++++++++++--
>>>>>>  1 file changed, 13 insertions(+), 2 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/irqchip/irq-bcm7038-l1.c b/drivers/irqchip/irq-bcm7038-l1.c
>>>>>> index 0673a44bbdc2..811a34201dd4 100644
>>>>>> --- a/drivers/irqchip/irq-bcm7038-l1.c
>>>>>> +++ b/drivers/irqchip/irq-bcm7038-l1.c
>>>>>> @@ -44,6 +44,7 @@ struct bcm7038_l1_chip {
>>>>>>  	struct list_head	list;
>>>>>>  	u32			wake_mask[MAX_WORDS];
>>>>>>  #endif
>>>>>> +	u32			irq_fwd_mask[MAX_WORDS];
>>>>>>  	u8			affinity[MAX_WORDS * IRQS_PER_WORD];
>>>>>>  };
>>>>>>  
>>>>>> @@ -265,6 +266,7 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
>>>>>>  	resource_size_t sz;
>>>>>>  	struct bcm7038_l1_cpu *cpu;
>>>>>>  	unsigned int i, n_words, parent_irq;
>>>>>> +	int ret;
>>>>>>  
>>>>>>  	if (of_address_to_resource(dn, idx, &res))
>>>>>>  		return -EINVAL;
>>>>>> @@ -278,6 +280,14 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
>>>>>>  	else if (intc->n_words != n_words)
>>>>>>  		return -EINVAL;
>>>>>>  
>>>>>> +	ret = of_property_read_u32_array(dn , "brcm,int-fwd-mask",
>>>>>
>>>>> What is the exact meaning of "fwd"? Forward? FirmWare Dementia?
>>>>
>>>> Here it is meant to be "forward", we have defined this property name
>>>> before for irq-bcm7120-l2.c and felt like reusing the same name to avoid
>>>> multiplying properties would be appropriate, see patch #4. If you prefer
>>>> something named brcm,firmware-configured-mask, let me know.
>>>
>>> It's just a name, but I found it a bit confusing. Bah, never mind.
>>>
>>>>>
>>>>>> +					 intc->irq_fwd_mask, n_words);
>>>>>> +	if (ret != 0 && ret != -EINVAL) {
>>>>>> +		/* property exists but has the wrong number of words */
>>>>>> +		pr_err("invalid brcm,int-fwd-mask property\n");
>>>>>> +		return -EINVAL;
>>>>>> +	}
>>>>>> +
>>>>>>  	cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
>>>>>>  					GFP_KERNEL);
>>>>>>  	if (!cpu)
>>>>>> @@ -288,8 +298,9 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
>>>>>>  		return -ENOMEM;
>>>>>>  
>>>>>>  	for (i = 0; i < n_words; i++) {
>>>>>> -		l1_writel(0xffffffff, cpu->map_base + reg_mask_set(intc, i));
>>>>>> -		cpu->mask_cache[i] = 0xffffffff;
>>>>>> +		l1_writel(0xffffffff & ~intc->irq_fwd_mask[i],
>>>>>> +			  cpu->map_base + reg_mask_set(intc, i));
>>>>>> +		cpu->mask_cache[i] = 0xffffffff & ~intc->irq_fwd_mask[i];
>>>>>
>>>>> I seem to remember that (0xffffffff & whatever) == whatever, as long as
>>>>> 'whatever' is a 32bit quantity. So what it this for?
>>>>
>>>> It is 0xffff_ffff & ~whatever here.
>>>
>>> Which doesn't change anything.
>>>
>>>> In the absence of this property
>>>> being specified, the data is all zeroed out, so we would have
>>>> 0xffff_ffff & 0xffff_ffff which is 0xffff_ffff. If this property is
>>>> specified, we would have one more or bits set, and it would be e.g.:
>>>> 0x100 so we would have 0xffff_ffff & ~(0x100) = 0xffff_feff which is
>>>> what we would want here to preserve whatever the firmware has already
>>>> configured.
>>>
>>> OK, I must be stupid:
>>>
>>> #include <stdio.h>
>>>
>>> int main(int argc, char *argv[])
>>> {
>>> 	unsigned int v = 0x100;
>>> 	printf ("%x\n", ~v);
>>> }
>>> maz@filthy-habit$ ./x
>>> fffffeff
>>>
>>> You might as well OR it with zeroes, if you want.
>>
>> Not sure I understand your point here.
>>
>> We used to write 0xffff_ffff to both the hardware and the mask cache to
>> have all interrupts masked by default. Now we want to have some bits
>> optionally set to 0 (unmasked), based on the brcm,int-fwd-mask property,
>> which is what this patch achieves (or tries to). If we write, say
>> 0xffff_feff to the hardware, which has a Write Only register behavior,
>> then we also want to have the mask cache be set to the same value for
>> consistency if nothing else. Am I failing at doing what I just described
>> and also failing at see it?
> 
> You write this:
> 
>>  	for (i = 0; i < n_words; i++) {
>> -		l1_writel(0xffffffff, cpu->map_base + reg_mask_set(intc, i));
>> -		cpu->mask_cache[i] = 0xffffffff;
>> +		l1_writel(0xffffffff & ~intc->irq_fwd_mask[i],
>> +			  cpu->map_base + reg_mask_set(intc, i));
>> +		cpu->mask_cache[i] = 0xffffffff & ~intc->irq_fwd_mask[i];
>>  	}
> 
> And I'm saying that this is strictly equivalent to:
> 
>  	for (i = 0; i < n_words; i++) {
> 		l1_writel(~intc->irq_fwd_mask[i],
> 			  cpu->map_base + reg_mask_set(intc, i));
> 		cpu->mask_cache[i] = ~intc->irq_fwd_mask[i];
>  	}
> 
> without this 0xffffffff that does exactly nothing (I'm pretty sure the
> compiler drops it anyway).

I understand quickly, you just need to repeat many times, thanks for
bearing with me, this is indeed simpler and clearer.
-- 
Florian

Re: [PATCH v2 2/5] dt-bindings: Document brcm,irq-can-wake for brcm,bcm7038-l1-intc.txt

[Rob Herring]

On Fri, Sep 13, 2019 at 12:15:39PM -0700, Florian Fainelli wrote:
> The BCM7038 L1 interrupt controller can be used as a wake-up interrupt
> controller on MIPS and ARM-based systems, document the brcm,irq-can-wake
> which has been "standardized" across Broadcom interrupt controllers.

Not clear that that got much review...

We have a defined way to indicate wakeup sources (which maybe didn't 
exist in 2014), why can't that be used? If a device can wakeup the 
system, I'd think we can just assume that the parent interrupt 
controller(s) can support that.

In any case, I'm not going to stand in the way of this:

Acked-by: Rob Herring <robh@kernel.org>

> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
>  .../bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt   | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
> index 2117d4ac1ae5..4eb043270f5b 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
> +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
> @@ -31,6 +31,11 @@ Required properties:
>  - interrupts: specifies the interrupt line(s) in the interrupt-parent controller
>    node; valid values depend on the type of parent interrupt controller
>  
> +Optional properties:
> +
> +- brcm,irq-can-wake: If present, this means the L1 controller can be used as a
> +  wakeup source for system suspend/resume.
> +
>  If multiple reg ranges and interrupt-parent entries are present on an SMP
>  system, the driver will allow IRQ SMP affinity to be set up through the
>  /proc/irq/ interface.  In the simplest possible configuration, only one
> -- 
> 2.17.1
> 

Re: [PATCH v2 4/5] dt-bindings: Document brcm,int-fwd-mask property for bcm7038-l1-intc

[Rob Herring]

On Fri, 13 Sep 2019 12:15:41 -0700, Florian Fainelli wrote:
> Indicate that the brcm,int-fwd-mask property is optional and can be
> optionaly set on platforms which require to leave specific interrupts
> untouched from Linux and retain the firmware configuration.
> 
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
>  .../bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt    | 4 ++++
>  1 file changed, 4 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>