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[80.67.176.117]) by smtp.gmail.com with ESMTPSA id e20sm70862642wrc.34.2019.09.15.02.09.31 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Sun, 15 Sep 2019 02:09:32 -0700 (PDT) Date: Sun, 15 Sep 2019 11:09:25 +0200 From: Sylvain 'ythier' Hitier To: Linus Torvalds Cc: Alex Shi , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , x86@kernel.org, Hans de Goede , "Rafael J. Wysocki" , Ricardo Neri , linux-kernel@vger.kernel.org, trivial@kernel.org Subject: [PATCH] x86: intel_tlb_table: small cleanups Message-ID: <20190915090917.GA5086@lilas> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Remove the unneeded backslash at EOL: that's not a macro. And let's please checkpatch by aligning to open parenthesis. For 0x4f descriptor, remove " */" from the info field. For 0xc2 descriptor, sync the beginning of info to match the tlb_type. (The value of info fields could be made more regular, but it's unused by the code and will be read only by developers, so don't bother.) Signed-off-by: Sylvain 'ythier' Hitier --- arch/x86/kernel/cpu/intel.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 8d6d92e..24e619d 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -813,7 +813,7 @@ static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" }, { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" }, { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" }, - { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" }, + { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages" }, { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, @@ -841,7 +841,7 @@ static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" }, { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" }, { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" }, - { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" }, + { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" }, { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" }, { 0x00, 0, 0 } }; @@ -853,8 +853,8 @@ static void intel_tlb_lookup(const unsigned char desc) return; /* look up this descriptor in the table */ - for (k = 0; intel_tlb_table[k].descriptor != desc && \ - intel_tlb_table[k].descriptor != 0; k++) + for (k = 0; intel_tlb_table[k].descriptor != desc && + intel_tlb_table[k].descriptor != 0; k++) ; if (intel_tlb_table[k].tlb_type == 0) -- 1.7.10.4 Regards, Sylvain "ythier" HITIER -- Business is about being busy, not being rich... Lived 777 days in a Debian package => http://en.wikipedia.org/wiki/Apt,_Vaucluse There's THE room for ideals in this mechanical place!