From: <Tudor.Ambarus@microchip.com>
To: <vigneshr@ti.com>, <boris.brezillon@collabora.com>,
<marek.vasut@gmail.com>, <miquel.raynal@bootlin.com>,
<richard@nod.at>, <linux-mtd@lists.infradead.org>
Cc: <dwmw2@infradead.org>, <computersforpeace@gmail.com>,
<joel@jms.id.au>, <andrew@aj.id.au>, <matthias.bgg@gmail.com>,
<vz@mleia.com>, <linux-arm-kernel@lists.infradead.org>,
<linux-aspeed@lists.ozlabs.org>, <linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>,
<Tudor.Ambarus@microchip.com>
Subject: [PATCH 18/23] mtd: spi-nor: Rework macronix_quad_enable()
Date: Tue, 17 Sep 2019 15:55:38 +0000 [thread overview]
Message-ID: <20190917155426.7432-19-tudor.ambarus@microchip.com> (raw)
In-Reply-To: <20190917155426.7432-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Rename method to a generic name: spi_nor_sr1_bit6_quad_enable().
Use spi_nor_write_sr1_and_check(). Now we check the validity of all
the eight bits of the Status Register, not just of the SR1_QUAD_EN_BIT6.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 34 ++++++++++------------------------
include/linux/mtd/spi-nor.h | 2 +-
2 files changed, 11 insertions(+), 25 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 4a513ed13807..2f79923e7db5 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1938,16 +1938,15 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
}
/**
- * macronix_quad_enable() - set QE bit in Status Register.
+ * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status
+ * Register 1.
* @nor: pointer to a 'struct spi_nor'
*
- * Set the Quad Enable (QE) bit in the Status Register.
- *
- * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
+ * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories.
*
* Return: 0 on success, -errno otherwise.
*/
-static int macronix_quad_enable(struct spi_nor *nor)
+static int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)
{
int ret;
@@ -1955,25 +1954,12 @@ static int macronix_quad_enable(struct spi_nor *nor)
if (ret)
return ret;
- if (nor->bouncebuf[0] & SR_QUAD_EN_MX)
+ if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)
return 0;
- nor->bouncebuf[0] |= SR_QUAD_EN_MX;
+ nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6;
- ret = spi_nor_write_sr(nor, &nor->bouncebuf[0], 1);
- if (ret)
- return ret;
-
- ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
- if (ret)
- return ret;
-
- if (!(nor->bouncebuf[0] & SR_QUAD_EN_MX)) {
- dev_err(nor->dev, "Macronix Quad bit not set\n");
- return -EIO;
- }
-
- return 0;
+ return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0], 0xFF);
}
/**
@@ -2277,7 +2263,7 @@ static void gd25q256_default_init(struct spi_nor *nor)
* indicate the quad_enable method for this case, we need
* to set it in the default_init fixup hook.
*/
- nor->flash.quad_enable = macronix_quad_enable;
+ nor->flash.quad_enable = spi_nor_sr1_bit6_quad_enable;
}
static struct spi_nor_fixups gd25q256_fixups = {
@@ -3661,7 +3647,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
case BFPT_DWORD15_QER_SR1_BIT6:
nor->flags &= ~SNOR_F_HAS_16BIT_SR;
- flash->quad_enable = macronix_quad_enable;
+ flash->quad_enable = spi_nor_sr1_bit6_quad_enable;
break;
case BFPT_DWORD15_QER_SR2_BIT7:
@@ -4558,7 +4544,7 @@ static int spi_nor_setup(struct spi_nor *nor,
static void macronix_set_default_init(struct spi_nor *nor)
{
- nor->flash.quad_enable = macronix_quad_enable;
+ nor->flash.quad_enable = spi_nor_sr1_bit6_quad_enable;
nor->flash.set_4byte = macronix_set_4byte;
}
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index fc3a8f5209f0..3a835de90b6a 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -133,7 +133,7 @@
#define SR_E_ERR BIT(5)
#define SR_P_ERR BIT(6)
-#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
+#define SR1_QUAD_EN_BIT6 BIT(6)
/* Enhanced Volatile Configuration Register bits */
#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
--
2.9.5
next prev parent reply other threads:[~2019-09-17 15:55 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 01/23] mtd: spi-nor: hisi-sfc: Drop nor->erase NULL assignment Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 02/23] mtd: spi-nor: Introduce 'struct spi_nor_controller_ops' Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 03/23] mtd: spi-nor: cadence-quadspi: Fix cqspi_command_read() definition Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 04/23] mtd: spi-nor: Rename nor->params to nor->flash Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 05/23] mtd: spi-nor: Rework read_sr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 06/23] mtd: spi-nor: Rework read_fsr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 07/23] mtd: spi-nor: Rework read_cr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 08/23] mtd: spi-nor: Rework write_enable/disable() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 09/23] mtd: spi-nor: Fix retlen handling in sst_write() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 10/23] mtd: spi-nor: Rework write_sr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 11/23] mtd: spi-nor: Rework spi_nor_read/write_sr2() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 12/23] mtd: spi-nor: Report error in spi_nor_xread_sr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 13/23] mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 14/23] mtd: spi-nor: Drop duplicated new line Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 15/23] mtd: spi-nor: Drop spansion_quad_enable() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 16/23] mtd: spi-nor: Fix errno on quad_enable methods Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 17/23] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() Tudor.Ambarus
2019-09-19 14:33 ` Vignesh Raghavendra
2019-09-19 15:54 ` Tudor.Ambarus
2019-09-20 5:23 ` Tudor.Ambarus
2019-09-17 15:55 ` Tudor.Ambarus [this message]
2019-09-17 15:55 ` [PATCH 19/23] mtd: spi-nor: Rework spansion(_no)_read_cr_quad_enable() Tudor.Ambarus
2019-09-19 17:34 ` Vignesh Raghavendra
2019-09-20 4:42 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 20/23] mtd: spi-nor: Update sr2_bit7_quad_enable() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 21/23] mtd: spi-nor: Rework the disabling of block write protection Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 22/23] mtd: spi-nor: Add Global Block Unlock support Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 23/23] mtd: spi-nor: Unlock global block protection on sst26vf064b Tudor.Ambarus
2019-09-19 14:37 ` [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Vignesh Raghavendra
2019-09-19 16:07 ` Tudor.Ambarus
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