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Tue, 17 Sep 2019 15:55:45 +0000 From: To: , , , , , CC: , , , , , , , , , , Subject: [PATCH 20/23] mtd: spi-nor: Update sr2_bit7_quad_enable() Thread-Topic: [PATCH 20/23] mtd: spi-nor: Update sr2_bit7_quad_enable() Thread-Index: AQHVbXBdQKqFCEhfJk6GjF8offODhQ== Date: Tue, 17 Sep 2019 15:55:45 +0000 Message-ID: <20190917155426.7432-21-tudor.ambarus@microchip.com> References: <20190917155426.7432-1-tudor.ambarus@microchip.com> In-Reply-To: <20190917155426.7432-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR0302CA0007.eurprd03.prod.outlook.com (2603:10a6:800:e9::17) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 4ad8ddeb-bd52-4c24-e894-08d73b877fe1 x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(5600167)(711020)(4605104)(1401327)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020);SRVR:MN2PR11MB3725; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 4ad8ddeb-bd52-4c24-e894-08d73b877fe1 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Sep 2019 15:55:45.1458 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: RKSnW3rzr6dbPTQPL8TjCcw2dNo1i6OLXd7VItTfrZmLCBuFkpXatsoG9pNXgL1PMU8HJY5mG04P5c19/SendsaghdkpkOp+cj50fcdgcLU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3725 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus Rename the method to spi_nor_sr2_bit7_quad_enable(). Do the read back test on all the eight bits of the Status Register, not just the QE one. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 8648666fb9bd..a9cdb6dbc25c 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1994,7 +1994,7 @@ static int spi_nor_sr2_bit1_quad_enable(struct spi_no= r *nor) } =20 /** - * sr2_bit7_quad_enable() - set QE bit in Status Register 2. + * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2. * @nor: pointer to a 'struct spi_nor' * * Set the Quad Enable (QE) bit in the Status Register 2. @@ -2005,10 +2005,11 @@ static int spi_nor_sr2_bit1_quad_enable(struct spi_= nor *nor) * * Return: 0 on success, -errno otherwise. */ -static int sr2_bit7_quad_enable(struct spi_nor *nor) +static int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor) { u8 *sr2 =3D nor->bouncebuf; int ret; + u8 sr2_written; =20 /* Check current Quad Enable bit value. */ ret =3D spi_nor_read_sr2(nor, sr2); @@ -2025,13 +2026,15 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor= ) if (ret) return ret; =20 + sr2_written =3D *sr2; + /* Read back and check it. */ ret =3D spi_nor_read_sr2(nor, sr2); if (ret) return ret; =20 - if (!(*sr2 & SR2_QUAD_EN_BIT7)) { - dev_err(nor->dev, "SR2 Quad bit not set\n"); + if (*sr2 !=3D sr2_written) { + dev_err(nor->dev, "Read back test failed\n"); return -EIO; } =20 @@ -3605,7 +3608,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, =20 case BFPT_DWORD15_QER_SR2_BIT7: nor->flags &=3D ~SNOR_F_HAS_16BIT_SR; - flash->quad_enable =3D sr2_bit7_quad_enable; + flash->quad_enable =3D spi_nor_sr2_bit7_quad_enable; break; =20 case BFPT_DWORD15_QER_SR2_BIT1: --=20 2.9.5