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* [PATCH 0/7] clk: meson: axg-audio: add sm1 support
@ 2019-09-24 15:33 Jerome Brunet
  2019-09-24 15:33 ` [PATCH 1/7] dt-bindings: clk: axg-audio: add sm1 bindings Jerome Brunet
                   ` (6 more replies)
  0 siblings, 7 replies; 19+ messages in thread
From: Jerome Brunet @ 2019-09-24 15:33 UTC (permalink / raw)
  To: Neil Armstrong
  Cc: Jerome Brunet, Kevin Hilman, linux-amlogic, linux-clk, linux-kernel

The purpose of this patchset is to add the sm1 support to the amlogic audio
clock controller. The line count is lot higher than what I hoped for. Even
if extremely similar, there is a shift in the register address on the sm1
which makes a bit of a mess.

I could have patched the address on the fly if running on sm1 but the end
result did not save much lines and would have been a pain to maintain and
scale in the future

Instead I choose to re-arrange the driver to share the macros and declare
separate clocks for the clock which have changed.

Jerome Brunet (7):
  dt-bindings: clk: axg-audio: add sm1 bindings
  dt-bindings: clock: meson: add sm1 resets to the axg-audio controller
  clk: meson: axg-audio: remove useless defines
  clk: meson: axg-audio: fix regmap last register
  clk: meson: axg-audio: prepare sm1 addition
  clk: meson: axg-audio: provide clk top signal name
  clk: meson: axg_audio: add sm1 support

 .../bindings/clock/amlogic,axg-audio-clkc.txt |    3 +-
 drivers/clk/meson/axg-audio.c                 | 2021 +++++++++++------
 drivers/clk/meson/axg-audio.h                 |   21 +-
 include/dt-bindings/clock/axg-audio-clkc.h    |   10 +
 .../reset/amlogic,meson-g12a-audio-reset.h    |   15 +
 5 files changed, 1373 insertions(+), 697 deletions(-)

-- 
2.21.0


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH 1/7] dt-bindings: clk: axg-audio: add sm1 bindings
  2019-09-24 15:33 [PATCH 0/7] clk: meson: axg-audio: add sm1 support Jerome Brunet
@ 2019-09-24 15:33 ` Jerome Brunet
  2019-09-27  9:10   ` Neil Armstrong
  2019-09-24 15:33 ` [PATCH 2/7] dt-bindings: clock: meson: add sm1 resets to the axg-audio controller Jerome Brunet
                   ` (5 subsequent siblings)
  6 siblings, 1 reply; 19+ messages in thread
From: Jerome Brunet @ 2019-09-24 15:33 UTC (permalink / raw)
  To: Neil Armstrong
  Cc: Jerome Brunet, Kevin Hilman, linux-amlogic, linux-clk, linux-kernel

Add the compatible and clock ids of the sm1 audio clock controller

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 .../bindings/clock/amlogic,axg-audio-clkc.txt          |  3 ++-
 include/dt-bindings/clock/axg-audio-clkc.h             | 10 ++++++++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
index b3957d10d241..3a8948c04bc9 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
@@ -7,7 +7,8 @@ devices.
 Required Properties:
 
 - compatible	: should be "amlogic,axg-audio-clkc" for the A113X and A113D,
-		  "amlogic,g12a-audio-clkc" for G12A.
+		  "amlogic,g12a-audio-clkc" for G12A,
+		  "amlogic,sm1-audio-clkc" for S905X3.
 - reg		: physical base address of the clock controller and length of
 		  memory mapped region.
 - clocks	: a list of phandle + clock-specifier pairs for the clocks listed
diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h
index 75901c636893..f561f5c5ef8f 100644
--- a/include/dt-bindings/clock/axg-audio-clkc.h
+++ b/include/dt-bindings/clock/axg-audio-clkc.h
@@ -80,5 +80,15 @@
 #define AUD_CLKID_TDM_SCLK_PAD0		160
 #define AUD_CLKID_TDM_SCLK_PAD1		161
 #define AUD_CLKID_TDM_SCLK_PAD2		162
+#define AUD_CLKID_TOP			163
+#define AUD_CLKID_TORAM			164
+#define AUD_CLKID_EQDRC			165
+#define AUD_CLKID_RESAMPLE_B		166
+#define AUD_CLKID_TOVAD			167
+#define AUD_CLKID_LOCKER		168
+#define AUD_CLKID_SPDIFIN_LB		169
+#define AUD_CLKID_FRDDR_D		170
+#define AUD_CLKID_TODDR_D		171
+#define AUD_CLKID_LOOPBACK_B		172
 
 #endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
-- 
2.21.0


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH 2/7] dt-bindings: clock: meson: add sm1 resets to the axg-audio controller
  2019-09-24 15:33 [PATCH 0/7] clk: meson: axg-audio: add sm1 support Jerome Brunet
  2019-09-24 15:33 ` [PATCH 1/7] dt-bindings: clk: axg-audio: add sm1 bindings Jerome Brunet
@ 2019-09-24 15:33 ` Jerome Brunet
  2019-09-27  9:10   ` Neil Armstrong
  2019-09-24 15:33 ` [PATCH 3/7] clk: meson: axg-audio: remove useless defines Jerome Brunet
                   ` (4 subsequent siblings)
  6 siblings, 1 reply; 19+ messages in thread
From: Jerome Brunet @ 2019-09-24 15:33 UTC (permalink / raw)
  To: Neil Armstrong
  Cc: Jerome Brunet, Kevin Hilman, linux-amlogic, linux-clk, linux-kernel

Add the reset id of the sm1 audio clock controller

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 .../reset/amlogic,meson-g12a-audio-reset.h        | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
index 14b78dabed0e..f805129ca7af 100644
--- a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
+++ b/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
@@ -35,4 +35,19 @@
 #define AUD_RESET_TOHDMITX	24
 #define AUD_RESET_CLKTREE	25
 
+/* SM1 added resets */
+#define AUD_RESET_RESAMPLE_B	26
+#define AUD_RESET_TOVAD		27
+#define AUD_RESET_LOCKER	28
+#define AUD_RESET_SPDIFIN_LB	29
+#define AUD_RESET_FRATV		30
+#define AUD_RESET_FRHDMIRX	31
+#define AUD_RESET_FRDDR_D	32
+#define AUD_RESET_TODDR_D	33
+#define AUD_RESET_LOOPBACK_B	34
+#define AUD_RESET_EARCTX	35
+#define AUD_RESET_EARCRX	36
+#define AUD_RESET_FRDDR_E	37
+#define AUD_RESET_TODDR_E	38
+
 #endif
-- 
2.21.0


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH 3/7] clk: meson: axg-audio: remove useless defines
  2019-09-24 15:33 [PATCH 0/7] clk: meson: axg-audio: add sm1 support Jerome Brunet
  2019-09-24 15:33 ` [PATCH 1/7] dt-bindings: clk: axg-audio: add sm1 bindings Jerome Brunet
  2019-09-24 15:33 ` [PATCH 2/7] dt-bindings: clock: meson: add sm1 resets to the axg-audio controller Jerome Brunet
@ 2019-09-24 15:33 ` Jerome Brunet
  2019-09-27  9:10   ` Neil Armstrong
  2019-09-24 15:33 ` [PATCH 4/7] clk: meson: axg-audio: fix regmap last register Jerome Brunet
                   ` (3 subsequent siblings)
  6 siblings, 1 reply; 19+ messages in thread
From: Jerome Brunet @ 2019-09-24 15:33 UTC (permalink / raw)
  To: Neil Armstrong
  Cc: Jerome Brunet, Kevin Hilman, linux-amlogic, linux-clk, linux-kernel

Defining the number of each input type is no longer necessary since
we are not using the clk-input hack anymore

Fixes: 282420eed23f ("clk: meson: axg-audio: migrate to the new parent description method")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/axg-audio.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index 18b23cdf679c..60ac71856e5e 100644
--- a/drivers/clk/meson/axg-audio.c
+++ b/drivers/clk/meson/axg-audio.c
@@ -20,10 +20,6 @@
 #include "clk-phase.h"
 #include "sclk-div.h"
 
-#define AUD_MST_IN_COUNT	8
-#define AUD_SLV_SCLK_COUNT	10
-#define AUD_SLV_LRCLK_COUNT	10
-
 #define AUD_GATE(_name, _reg, _bit, _phws, _iflags)			\
 struct clk_regmap aud_##_name = {					\
 	.data = &(struct clk_regmap_gate_data){				\
-- 
2.21.0


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH 4/7] clk: meson: axg-audio: fix regmap last register
  2019-09-24 15:33 [PATCH 0/7] clk: meson: axg-audio: add sm1 support Jerome Brunet
                   ` (2 preceding siblings ...)
  2019-09-24 15:33 ` [PATCH 3/7] clk: meson: axg-audio: remove useless defines Jerome Brunet
@ 2019-09-24 15:33 ` Jerome Brunet
  2019-09-27  9:11   ` Neil Armstrong
  2019-09-24 15:33 ` [PATCH 5/7] clk: meson: axg-audio: prepare sm1 addition Jerome Brunet
                   ` (2 subsequent siblings)
  6 siblings, 1 reply; 19+ messages in thread
From: Jerome Brunet @ 2019-09-24 15:33 UTC (permalink / raw)
  To: Neil Armstrong
  Cc: Jerome Brunet, Kevin Hilman, linux-amlogic, linux-clk, linux-kernel

Since the addition of the g12a, the last register is
AUDIO_CLK_SPDIFOUT_B_CTRL.

Fixes: 075001385c66 ("clk: meson: axg-audio: add g12a support")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/axg-audio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index 60ac71856e5e..4b34601342bb 100644
--- a/drivers/clk/meson/axg-audio.c
+++ b/drivers/clk/meson/axg-audio.c
@@ -997,7 +997,7 @@ static const struct regmap_config axg_audio_regmap_cfg = {
 	.reg_bits	= 32,
 	.val_bits	= 32,
 	.reg_stride	= 4,
-	.max_register	= AUDIO_CLK_PDMIN_CTRL1,
+	.max_register	= AUDIO_CLK_SPDIFOUT_B_CTRL,
 };
 
 struct audioclk_data {
-- 
2.21.0


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH 5/7] clk: meson: axg-audio: prepare sm1 addition
  2019-09-24 15:33 [PATCH 0/7] clk: meson: axg-audio: add sm1 support Jerome Brunet
                   ` (3 preceding siblings ...)
  2019-09-24 15:33 ` [PATCH 4/7] clk: meson: axg-audio: fix regmap last register Jerome Brunet
@ 2019-09-24 15:33 ` Jerome Brunet
  2019-09-27  9:13   ` Neil Armstrong
  2019-09-24 15:33 ` [PATCH 6/7] clk: meson: axg-audio: provide clk top signal name Jerome Brunet
  2019-09-24 15:33 ` [PATCH 7/7] clk: meson: axg_audio: add sm1 support Jerome Brunet
  6 siblings, 1 reply; 19+ messages in thread
From: Jerome Brunet @ 2019-09-24 15:33 UTC (permalink / raw)
  To: Neil Armstrong
  Cc: Jerome Brunet, Kevin Hilman, linux-amlogic, linux-clk, linux-kernel

Rearrange the macro definition of the clocks of the axg-audio
controller. Also, the sm1 variant will feature tiny modification
of different blocks in this controller. Because of that, we need
to fallback to the old way of defining parent for some of the
clocks, using signal name.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/axg-audio.c | 1467 ++++++++++++++++++---------------
 1 file changed, 782 insertions(+), 685 deletions(-)

diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index 4b34601342bb..ce8836776d1c 100644
--- a/drivers/clk/meson/axg-audio.c
+++ b/drivers/clk/meson/axg-audio.c
@@ -20,8 +20,7 @@
 #include "clk-phase.h"
 #include "sclk-div.h"
 
-#define AUD_GATE(_name, _reg, _bit, _phws, _iflags)			\
-struct clk_regmap aud_##_name = {					\
+#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) {			\
 	.data = &(struct clk_regmap_gate_data){				\
 		.offset = (_reg),					\
 		.bit_idx = (_bit),					\
@@ -29,14 +28,13 @@ struct clk_regmap aud_##_name = {					\
 	.hw.init = &(struct clk_init_data) {				\
 		.name = "aud_"#_name,					\
 		.ops = &clk_regmap_gate_ops,				\
-		.parent_hws = (const struct clk_hw *[]) { &_phws.hw },	\
+		.parent_names = (const char *[]){ #_pname },		\
 		.num_parents = 1,					\
 		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\
 	},								\
 }
 
-#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags)	\
-struct clk_regmap aud_##_name = {					\
+#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) {	\
 	.data = &(struct clk_regmap_mux_data){				\
 		.offset = (_reg),					\
 		.mask = (_mask),					\
@@ -52,8 +50,7 @@ struct clk_regmap aud_##_name = {					\
 	},								\
 }
 
-#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _phws, _iflags)	\
-struct clk_regmap aud_##_name = {					\
+#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \
 	.data = &(struct clk_regmap_div_data){				\
 		.offset = (_reg),					\
 		.shift = (_shift),					\
@@ -63,14 +60,13 @@ struct clk_regmap aud_##_name = {					\
 	.hw.init = &(struct clk_init_data){				\
 		.name = "aud_"#_name,					\
 		.ops = &clk_regmap_divider_ops,				\
-		.parent_hws = (const struct clk_hw *[]) { &_phws.hw },	\
+		.parent_names = (const char *[]){ #_pname },		\
 		.num_parents = 1,					\
 		.flags = (_iflags),					\
 	},								\
 }
 
-#define AUD_PCLK_GATE(_name, _bit)				\
-struct clk_regmap aud_##_name = {					\
+#define AUD_PCLK_GATE(_name, _bit) {					\
 	.data = &(struct clk_regmap_gate_data){				\
 		.offset = (AUDIO_CLK_GATE_EN),				\
 		.bit_idx = (_bit),					\
@@ -84,116 +80,9 @@ struct clk_regmap aud_##_name = {					\
 		.num_parents = 1,					\
 	},								\
 }
-/* Audio peripheral clocks */
-static AUD_PCLK_GATE(ddr_arb,	   0);
-static AUD_PCLK_GATE(pdm,	   1);
-static AUD_PCLK_GATE(tdmin_a,	   2);
-static AUD_PCLK_GATE(tdmin_b,	   3);
-static AUD_PCLK_GATE(tdmin_c,	   4);
-static AUD_PCLK_GATE(tdmin_lb,	   5);
-static AUD_PCLK_GATE(tdmout_a,	   6);
-static AUD_PCLK_GATE(tdmout_b,	   7);
-static AUD_PCLK_GATE(tdmout_c,	   8);
-static AUD_PCLK_GATE(frddr_a,	   9);
-static AUD_PCLK_GATE(frddr_b,	   10);
-static AUD_PCLK_GATE(frddr_c,	   11);
-static AUD_PCLK_GATE(toddr_a,	   12);
-static AUD_PCLK_GATE(toddr_b,	   13);
-static AUD_PCLK_GATE(toddr_c,	   14);
-static AUD_PCLK_GATE(loopback,	   15);
-static AUD_PCLK_GATE(spdifin,	   16);
-static AUD_PCLK_GATE(spdifout,	   17);
-static AUD_PCLK_GATE(resample,	   18);
-static AUD_PCLK_GATE(power_detect, 19);
-static AUD_PCLK_GATE(spdifout_b,   21);
-
-/* Audio Master Clocks */
-static const struct clk_parent_data mst_mux_parent_data[] = {
-	{ .fw_name = "mst_in0", },
-	{ .fw_name = "mst_in1", },
-	{ .fw_name = "mst_in2", },
-	{ .fw_name = "mst_in3", },
-	{ .fw_name = "mst_in4", },
-	{ .fw_name = "mst_in5", },
-	{ .fw_name = "mst_in6", },
-	{ .fw_name = "mst_in7", },
-};
-
-#define AUD_MST_MUX(_name, _reg, _flag)				\
-	AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag,		\
-		mst_mux_parent_data, 0)
-
-#define AUD_MST_MCLK_MUX(_name, _reg)				\
-	AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
-
-#define AUD_MST_SYS_MUX(_name, _reg)				\
-	AUD_MST_MUX(_name, _reg, 0)
-
-static AUD_MST_MCLK_MUX(mst_a_mclk,   AUDIO_MCLK_A_CTRL);
-static AUD_MST_MCLK_MUX(mst_b_mclk,   AUDIO_MCLK_B_CTRL);
-static AUD_MST_MCLK_MUX(mst_c_mclk,   AUDIO_MCLK_C_CTRL);
-static AUD_MST_MCLK_MUX(mst_d_mclk,   AUDIO_MCLK_D_CTRL);
-static AUD_MST_MCLK_MUX(mst_e_mclk,   AUDIO_MCLK_E_CTRL);
-static AUD_MST_MCLK_MUX(mst_f_mclk,   AUDIO_MCLK_F_CTRL);
-static AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
-static AUD_MST_MCLK_MUX(pdm_dclk,     AUDIO_CLK_PDMIN_CTRL0);
-static AUD_MST_SYS_MUX(spdifin_clk,   AUDIO_CLK_SPDIFIN_CTRL);
-static AUD_MST_SYS_MUX(pdm_sysclk,    AUDIO_CLK_PDMIN_CTRL1);
-static AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
-
-#define AUD_MST_DIV(_name, _reg, _flag)				\
-	AUD_DIV(_name##_div, _reg, 0, 16, _flag,		\
-		    aud_##_name##_sel, CLK_SET_RATE_PARENT)	\
-
-#define AUD_MST_MCLK_DIV(_name, _reg)				\
-	AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
-
-#define AUD_MST_SYS_DIV(_name, _reg)				\
-	AUD_MST_DIV(_name, _reg, 0)
-
-static AUD_MST_MCLK_DIV(mst_a_mclk,   AUDIO_MCLK_A_CTRL);
-static AUD_MST_MCLK_DIV(mst_b_mclk,   AUDIO_MCLK_B_CTRL);
-static AUD_MST_MCLK_DIV(mst_c_mclk,   AUDIO_MCLK_C_CTRL);
-static AUD_MST_MCLK_DIV(mst_d_mclk,   AUDIO_MCLK_D_CTRL);
-static AUD_MST_MCLK_DIV(mst_e_mclk,   AUDIO_MCLK_E_CTRL);
-static AUD_MST_MCLK_DIV(mst_f_mclk,   AUDIO_MCLK_F_CTRL);
-static AUD_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
-static AUD_MST_MCLK_DIV(pdm_dclk,     AUDIO_CLK_PDMIN_CTRL0);
-static AUD_MST_SYS_DIV(spdifin_clk,   AUDIO_CLK_SPDIFIN_CTRL);
-static AUD_MST_SYS_DIV(pdm_sysclk,    AUDIO_CLK_PDMIN_CTRL1);
-static AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
-
-#define AUD_MST_MCLK_GATE(_name, _reg)				\
-	AUD_GATE(_name, _reg, 31,  aud_##_name##_div,		\
-		 CLK_SET_RATE_PARENT)
-
-static AUD_MST_MCLK_GATE(mst_a_mclk,   AUDIO_MCLK_A_CTRL);
-static AUD_MST_MCLK_GATE(mst_b_mclk,   AUDIO_MCLK_B_CTRL);
-static AUD_MST_MCLK_GATE(mst_c_mclk,   AUDIO_MCLK_C_CTRL);
-static AUD_MST_MCLK_GATE(mst_d_mclk,   AUDIO_MCLK_D_CTRL);
-static AUD_MST_MCLK_GATE(mst_e_mclk,   AUDIO_MCLK_E_CTRL);
-static AUD_MST_MCLK_GATE(mst_f_mclk,   AUDIO_MCLK_F_CTRL);
-static AUD_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
-static AUD_MST_MCLK_GATE(spdifin_clk,  AUDIO_CLK_SPDIFIN_CTRL);
-static AUD_MST_MCLK_GATE(pdm_dclk,     AUDIO_CLK_PDMIN_CTRL0);
-static AUD_MST_MCLK_GATE(pdm_sysclk,   AUDIO_CLK_PDMIN_CTRL1);
-static AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
-
-/* Sample Clocks */
-#define AUD_MST_SCLK_PRE_EN(_name, _reg)			\
-	AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31,		\
-		 aud_mst_##_name##_mclk, 0)
-
-static AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
-static AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
-static AUD_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0);
-static AUD_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0);
-static AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
-static AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
 
 #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width,		\
-			 _hi_shift, _hi_width, _phws, _iflags)		\
-struct clk_regmap aud_##_name = {					\
+		     _hi_shift, _hi_width, _pname, _iflags) {		\
 	.data = &(struct meson_sclk_div_data) {				\
 		.div = {						\
 			.reg_off = (_reg),				\
@@ -209,38 +98,14 @@ struct clk_regmap aud_##_name = {					\
 	.hw.init = &(struct clk_init_data) {				\
 		.name = "aud_"#_name,					\
 		.ops = &meson_sclk_div_ops,				\
-		.parent_hws = (const struct clk_hw *[]) { &_phws.hw },	\
+		.parent_names = (const char *[]){ #_pname },		\
 		.num_parents = 1,					\
 		.flags = (_iflags),					\
 	},								\
 }
 
-#define AUD_MST_SCLK_DIV(_name, _reg)					\
-	AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0,	\
-		     aud_mst_##_name##_sclk_pre_en,			\
-		     CLK_SET_RATE_PARENT)
-
-static AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
-static AUD_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
-static AUD_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
-static AUD_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
-static AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
-static AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
-
-#define AUD_MST_SCLK_POST_EN(_name, _reg)				\
-	AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30,			\
-		 aud_mst_##_name##_sclk_div, CLK_SET_RATE_PARENT)
-
-static AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
-static AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
-static AUD_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0);
-static AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
-static AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
-static AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
-
 #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2,	\
-			 _phws, _iflags)				\
-struct clk_regmap aud_##_name = {					\
+		     _pname, _iflags) {					\
 	.data = &(struct meson_clk_triphase_data) {			\
 		.ph0 = {						\
 			.reg_off = (_reg),				\
@@ -261,52 +126,91 @@ struct clk_regmap aud_##_name = {					\
 	.hw.init = &(struct clk_init_data) {				\
 		.name = "aud_"#_name,					\
 		.ops = &meson_clk_triphase_ops,				\
-		.parent_hws = (const struct clk_hw *[]) { &_phws.hw },	\
+		.parent_names = (const char *[]){ #_pname },		\
 		.num_parents = 1,					\
 		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\
 	},								\
 }
 
+#define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) {	\
+	.data = &(struct meson_clk_phase_data) {			\
+		.ph = {							\
+			.reg_off = (_reg),				\
+			.shift   = (_shift),				\
+			.width   = (_width),				\
+		},							\
+	},								\
+	.hw.init = &(struct clk_init_data) {				\
+		.name = "aud_"#_name,					\
+		.ops = &meson_clk_phase_ops,				\
+		.parent_names = (const char *[]){ #_pname },		\
+		.num_parents = 1,					\
+		.flags = (_iflags),					\
+	},								\
+}
+
+/* Audio Master Clocks */
+static const struct clk_parent_data mst_mux_parent_data[] = {
+	{ .fw_name = "mst_in0", },
+	{ .fw_name = "mst_in1", },
+	{ .fw_name = "mst_in2", },
+	{ .fw_name = "mst_in3", },
+	{ .fw_name = "mst_in4", },
+	{ .fw_name = "mst_in5", },
+	{ .fw_name = "mst_in6", },
+	{ .fw_name = "mst_in7", },
+};
+
+#define AUD_MST_MUX(_name, _reg, _flag)					\
+	AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag,			\
+		mst_mux_parent_data, 0)
+#define AUD_MST_DIV(_name, _reg, _flag)					\
+	AUD_DIV(_name##_div, _reg, 0, 16, _flag,			\
+		aud_##_name##_sel, CLK_SET_RATE_PARENT)
+#define AUD_MST_MCLK_GATE(_name, _reg)					\
+	AUD_GATE(_name, _reg, 31, aud_##_name##_div,			\
+		 CLK_SET_RATE_PARENT)
+
+#define AUD_MST_MCLK_MUX(_name, _reg)					\
+	AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
+#define AUD_MST_MCLK_DIV(_name, _reg)					\
+	AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
+
+#define AUD_MST_SYS_MUX(_name, _reg)					\
+	AUD_MST_MUX(_name, _reg, 0)
+#define AUD_MST_SYS_DIV(_name, _reg)					\
+	AUD_MST_DIV(_name, _reg, 0)
+
+/* Sample Clocks */
+#define AUD_MST_SCLK_PRE_EN(_name, _reg)				\
+	AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31,			\
+		 aud_mst_##_name##_mclk, 0)
+#define AUD_MST_SCLK_DIV(_name, _reg)					\
+	AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0,	\
+		     aud_mst_##_name##_sclk_pre_en,			\
+		     CLK_SET_RATE_PARENT)
+#define AUD_MST_SCLK_POST_EN(_name, _reg)				\
+	AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30,			\
+		 aud_mst_##_name##_sclk_div, CLK_SET_RATE_PARENT)
 #define AUD_MST_SCLK(_name, _reg)					\
 	AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4,		\
 		     aud_mst_##_name##_sclk_post_en, CLK_SET_RATE_PARENT)
 
-static AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
-static AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
-static AUD_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1);
-static AUD_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1);
-static AUD_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1);
-static AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
-
 #define AUD_MST_LRCLK_DIV(_name, _reg)					\
 	AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10,	\
-		     aud_mst_##_name##_sclk_post_en, 0)			\
-
-static AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
-static AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
-static AUD_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
-static AUD_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
-static AUD_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
-static AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
-
+		     aud_mst_##_name##_sclk_post_en, 0)
 #define AUD_MST_LRCLK(_name, _reg)					\
 	AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5,		\
 		     aud_mst_##_name##_lrclk_div, CLK_SET_RATE_PARENT)
 
-static AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
-static AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
-static AUD_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1);
-static AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
-static AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
-static AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
-
+/* TDM bit clock sources */
 static const struct clk_parent_data tdm_sclk_parent_data[] = {
-	{ .hw = &aud_mst_a_sclk.hw, },
-	{ .hw = &aud_mst_b_sclk.hw, },
-	{ .hw = &aud_mst_c_sclk.hw, },
-	{ .hw = &aud_mst_d_sclk.hw, },
-	{ .hw = &aud_mst_e_sclk.hw, },
-	{ .hw = &aud_mst_f_sclk.hw, },
+	{ .name = "aud_mst_a_sclk", .index = -1, },
+	{ .name = "aud_mst_b_sclk", .index = -1, },
+	{ .name = "aud_mst_c_sclk", .index = -1, },
+	{ .name = "aud_mst_d_sclk", .index = -1, },
+	{ .name = "aud_mst_e_sclk", .index = -1, },
+	{ .name = "aud_mst_f_sclk", .index = -1, },
 	{ .fw_name = "slv_sclk0", },
 	{ .fw_name = "slv_sclk1", },
 	{ .fw_name = "slv_sclk2", },
@@ -319,78 +223,14 @@ static const struct clk_parent_data tdm_sclk_parent_data[] = {
 	{ .fw_name = "slv_sclk9", },
 };
 
-#define AUD_TDM_SCLK_MUX(_name, _reg)				\
-	AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24,		\
-		    CLK_MUX_ROUND_CLOSEST,			\
-		    tdm_sclk_parent_data, 0)
-
-static AUD_TDM_SCLK_MUX(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
-static AUD_TDM_SCLK_MUX(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
-static AUD_TDM_SCLK_MUX(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
-static AUD_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
-static AUD_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
-static AUD_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
-static AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
-
-#define AUD_TDM_SCLK_PRE_EN(_name, _reg)				\
-	AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31,			\
-		 aud_tdm##_name##_sclk_sel, CLK_SET_RATE_PARENT)
-
-static AUD_TDM_SCLK_PRE_EN(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
-static AUD_TDM_SCLK_PRE_EN(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
-static AUD_TDM_SCLK_PRE_EN(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
-static AUD_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
-static AUD_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
-static AUD_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
-static AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
-
-#define AUD_TDM_SCLK_POST_EN(_name, _reg)				\
-	AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30,			\
-		 aud_tdm##_name##_sclk_pre_en, CLK_SET_RATE_PARENT)
-
-static AUD_TDM_SCLK_POST_EN(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
-static AUD_TDM_SCLK_POST_EN(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
-static AUD_TDM_SCLK_POST_EN(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
-static AUD_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
-static AUD_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
-static AUD_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
-static AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
-
-#define AUD_TDM_SCLK(_name, _reg)					\
-	struct clk_regmap aud_tdm##_name##_sclk = {			\
-	.data = &(struct meson_clk_phase_data) {			\
-		.ph = {							\
-			.reg_off = (_reg),				\
-			.shift   = 29,					\
-			.width   = 1,					\
-		},							\
-	},								\
-	.hw.init = &(struct clk_init_data) {				\
-		.name = "aud_tdm"#_name"_sclk",				\
-		.ops = &meson_clk_phase_ops,				\
-		.parent_hws = (const struct clk_hw *[]) {		\
-			&aud_tdm##_name##_sclk_post_en.hw		\
-		},							\
-		.num_parents = 1,					\
-		.flags = CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT,	\
-	},								\
-}
-
-static AUD_TDM_SCLK(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
-static AUD_TDM_SCLK(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
-static AUD_TDM_SCLK(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
-static AUD_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
-static AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
-static AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
-static AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
-
+/* TDM sample clock sources */
 static const struct clk_parent_data tdm_lrclk_parent_data[] = {
-	{ .hw = &aud_mst_a_lrclk.hw, },
-	{ .hw = &aud_mst_b_lrclk.hw, },
-	{ .hw = &aud_mst_c_lrclk.hw, },
-	{ .hw = &aud_mst_d_lrclk.hw, },
-	{ .hw = &aud_mst_e_lrclk.hw, },
-	{ .hw = &aud_mst_f_lrclk.hw, },
+	{ .name = "aud_mst_a_lrclk", .index = -1, },
+	{ .name = "aud_mst_b_lrclk", .index = -1, },
+	{ .name = "aud_mst_c_lrclk", .index = -1, },
+	{ .name = "aud_mst_d_lrclk", .index = -1, },
+	{ .name = "aud_mst_e_lrclk", .index = -1, },
+	{ .name = "aud_mst_f_lrclk", .index = -1, },
 	{ .fw_name = "slv_lrclk0", },
 	{ .fw_name = "slv_lrclk1", },
 	{ .fw_name = "slv_lrclk2", },
@@ -403,69 +243,326 @@ static const struct clk_parent_data tdm_lrclk_parent_data[] = {
 	{ .fw_name = "slv_lrclk9", },
 };
 
-#define AUD_TDM_LRLCK(_name, _reg)			\
-	AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20,	\
-		CLK_MUX_ROUND_CLOSEST,			\
-		tdm_lrclk_parent_data, 0)
-
-static AUD_TDM_LRLCK(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
-static AUD_TDM_LRLCK(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
-static AUD_TDM_LRLCK(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
-static AUD_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
-static AUD_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
-static AUD_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
-static AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
+#define AUD_TDM_SCLK_MUX(_name, _reg)					\
+	AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24,			\
+		CLK_MUX_ROUND_CLOSEST, tdm_sclk_parent_data, 0)
+#define AUD_TDM_SCLK_PRE_EN(_name, _reg)				\
+	AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31,			\
+		 aud_tdm##_name##_sclk_sel, CLK_SET_RATE_PARENT)
+#define AUD_TDM_SCLK_POST_EN(_name, _reg)				\
+	AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30,			\
+		 aud_tdm##_name##_sclk_pre_en, CLK_SET_RATE_PARENT)
+#define AUD_TDM_SCLK(_name, _reg)					\
+	AUD_PHASE(tdm##_name##_sclk, _reg, 1, 29,			\
+		  aud_tdm##_name##_sclk_post_en,			\
+		  CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT)
 
-/* G12a Pad control */
-#define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents)		\
-	AUD_MUX(tdm_##_name, _reg, 0x7, _shift, 0, _parents,	\
-		CLK_SET_RATE_NO_REPARENT)
+#define AUD_TDM_LRLCK(_name, _reg)					\
+	AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20,			\
+		CLK_MUX_ROUND_CLOSEST, tdm_lrclk_parent_data, 0)
 
+/* Pad master clock sources */
 static const struct clk_parent_data mclk_pad_ctrl_parent_data[] = {
-	{ .hw = &aud_mst_a_mclk.hw },
-	{ .hw = &aud_mst_b_mclk.hw },
-	{ .hw = &aud_mst_c_mclk.hw },
-	{ .hw = &aud_mst_d_mclk.hw },
-	{ .hw = &aud_mst_e_mclk.hw },
-	{ .hw = &aud_mst_f_mclk.hw },
+	{ .name = "aud_mst_a_mclk", .index = -1,  },
+	{ .name = "aud_mst_b_mclk", .index = -1,  },
+	{ .name = "aud_mst_c_mclk", .index = -1,  },
+	{ .name = "aud_mst_d_mclk", .index = -1,  },
+	{ .name = "aud_mst_e_mclk", .index = -1,  },
+	{ .name = "aud_mst_f_mclk", .index = -1,  },
 };
 
-static AUD_TDM_PAD_CTRL(mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0,
-			mclk_pad_ctrl_parent_data);
-static AUD_TDM_PAD_CTRL(mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4,
-			mclk_pad_ctrl_parent_data);
+/* Pad bit clock sources */
+static const struct clk_parent_data sclk_pad_ctrl_parent_data[] = {
+	{ .name = "aud_mst_a_sclk", .index = -1, },
+	{ .name = "aud_mst_b_sclk", .index = -1, },
+	{ .name = "aud_mst_c_sclk", .index = -1, },
+	{ .name = "aud_mst_d_sclk", .index = -1, },
+	{ .name = "aud_mst_e_sclk", .index = -1, },
+	{ .name = "aud_mst_f_sclk", .index = -1, },
+};
 
+/* Pad sample clock sources */
 static const struct clk_parent_data lrclk_pad_ctrl_parent_data[] = {
-	{ .hw = &aud_mst_a_lrclk.hw },
-	{ .hw = &aud_mst_b_lrclk.hw },
-	{ .hw = &aud_mst_c_lrclk.hw },
-	{ .hw = &aud_mst_d_lrclk.hw },
-	{ .hw = &aud_mst_e_lrclk.hw },
-	{ .hw = &aud_mst_f_lrclk.hw },
+	{ .name = "aud_mst_a_lrclk", .index = -1, },
+	{ .name = "aud_mst_b_lrclk", .index = -1, },
+	{ .name = "aud_mst_c_lrclk", .index = -1, },
+	{ .name = "aud_mst_d_lrclk", .index = -1, },
+	{ .name = "aud_mst_e_lrclk", .index = -1, },
+	{ .name = "aud_mst_f_lrclk", .index = -1, },
 };
 
-static AUD_TDM_PAD_CTRL(lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16,
-			lrclk_pad_ctrl_parent_data);
-static AUD_TDM_PAD_CTRL(lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20,
-			lrclk_pad_ctrl_parent_data);
-static AUD_TDM_PAD_CTRL(lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24,
-			lrclk_pad_ctrl_parent_data);
-
-static const struct clk_parent_data sclk_pad_ctrl_parent_data[] = {
-	{ .hw = &aud_mst_a_sclk.hw },
-	{ .hw = &aud_mst_b_sclk.hw },
-	{ .hw = &aud_mst_c_sclk.hw },
-	{ .hw = &aud_mst_d_sclk.hw },
-	{ .hw = &aud_mst_e_sclk.hw },
-	{ .hw = &aud_mst_f_sclk.hw },
-};
+#define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents)		\
+	AUD_MUX(tdm_##_name, _reg, 0x7, _shift, 0, _parents,	\
+		CLK_SET_RATE_NO_REPARENT)
 
-static AUD_TDM_PAD_CTRL(sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0,
-			sclk_pad_ctrl_parent_data);
-static AUD_TDM_PAD_CTRL(sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4,
-			sclk_pad_ctrl_parent_data);
-static AUD_TDM_PAD_CTRL(sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8,
-			sclk_pad_ctrl_parent_data);
+/* Common Clocks */
+static struct clk_regmap ddr_arb	= AUD_PCLK_GATE(ddr_arb, 0);
+static struct clk_regmap pdm		= AUD_PCLK_GATE(pdm, 1);
+static struct clk_regmap tdmin_a	= AUD_PCLK_GATE(tdmin_a, 2);
+static struct clk_regmap tdmin_b	= AUD_PCLK_GATE(tdmin_b, 3);
+static struct clk_regmap tdmin_c	= AUD_PCLK_GATE(tdmin_c, 4);
+static struct clk_regmap tdmin_lb	= AUD_PCLK_GATE(tdmin_lb, 5);
+static struct clk_regmap tdmout_a	= AUD_PCLK_GATE(tdmout_a, 6);
+static struct clk_regmap tdmout_b	= AUD_PCLK_GATE(tdmout_b, 7);
+static struct clk_regmap tdmout_c	= AUD_PCLK_GATE(tdmout_c, 8);
+static struct clk_regmap frddr_a	= AUD_PCLK_GATE(frddr_a, 9);
+static struct clk_regmap frddr_b	= AUD_PCLK_GATE(frddr_b, 10);
+static struct clk_regmap frddr_c	= AUD_PCLK_GATE(frddr_c, 11);
+static struct clk_regmap toddr_a	= AUD_PCLK_GATE(toddr_a, 12);
+static struct clk_regmap toddr_b	= AUD_PCLK_GATE(toddr_b, 13);
+static struct clk_regmap toddr_c	= AUD_PCLK_GATE(toddr_c, 14);
+static struct clk_regmap loopback	= AUD_PCLK_GATE(loopback, 15);
+static struct clk_regmap spdifin	= AUD_PCLK_GATE(spdifin, 16);
+static struct clk_regmap spdifout	= AUD_PCLK_GATE(spdifout, 17);
+static struct clk_regmap resample	= AUD_PCLK_GATE(resample, 18);
+static struct clk_regmap power_detect	= AUD_PCLK_GATE(power_detect, 19);
+
+static struct clk_regmap spdifout_clk_sel =
+	AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
+static struct clk_regmap pdm_dclk_sel =
+	AUD_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
+static struct clk_regmap spdifin_clk_sel =
+	AUD_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
+static struct clk_regmap pdm_sysclk_sel =
+	AUD_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
+static struct clk_regmap spdifout_b_clk_sel =
+	AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
+
+static struct clk_regmap spdifout_clk_div =
+	AUD_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
+static struct clk_regmap pdm_dclk_div =
+	AUD_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
+static struct clk_regmap spdifin_clk_div =
+	AUD_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
+static struct clk_regmap pdm_sysclk_div =
+	AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
+static struct clk_regmap spdifout_b_clk_div =
+	AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
+
+static struct clk_regmap spdifout_clk =
+	AUD_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
+static struct clk_regmap spdifin_clk =
+	AUD_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
+static struct clk_regmap pdm_dclk =
+	AUD_MST_MCLK_GATE(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
+static struct clk_regmap pdm_sysclk =
+	AUD_MST_MCLK_GATE(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
+static struct clk_regmap spdifout_b_clk =
+	AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
+
+static struct clk_regmap mst_a_sclk_pre_en =
+	AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
+static struct clk_regmap mst_b_sclk_pre_en =
+	AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
+static struct clk_regmap mst_c_sclk_pre_en =
+	AUD_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0);
+static struct clk_regmap mst_d_sclk_pre_en =
+	AUD_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0);
+static struct clk_regmap mst_e_sclk_pre_en =
+	AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
+static struct clk_regmap mst_f_sclk_pre_en =
+	AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
+
+static struct clk_regmap mst_a_sclk_div =
+	AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
+static struct clk_regmap mst_b_sclk_div =
+	AUD_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
+static struct clk_regmap mst_c_sclk_div =
+	AUD_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
+static struct clk_regmap mst_d_sclk_div =
+	AUD_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
+static struct clk_regmap mst_e_sclk_div =
+	AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
+static struct clk_regmap mst_f_sclk_div =
+	AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
+
+static struct clk_regmap mst_a_sclk_post_en =
+	AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
+static struct clk_regmap mst_b_sclk_post_en =
+	AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
+static struct clk_regmap mst_c_sclk_post_en =
+	AUD_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0);
+static struct clk_regmap mst_d_sclk_post_en =
+	AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
+static struct clk_regmap mst_e_sclk_post_en =
+	AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
+static struct clk_regmap mst_f_sclk_post_en =
+	AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
+
+static struct clk_regmap mst_a_sclk =
+	AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
+static struct clk_regmap mst_b_sclk =
+	AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
+static struct clk_regmap mst_c_sclk =
+	AUD_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1);
+static struct clk_regmap mst_d_sclk =
+	AUD_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1);
+static struct clk_regmap mst_e_sclk =
+	AUD_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1);
+static struct clk_regmap mst_f_sclk =
+	AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
+
+static struct clk_regmap mst_a_lrclk_div =
+	AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
+static struct clk_regmap mst_b_lrclk_div =
+	AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
+static struct clk_regmap mst_c_lrclk_div =
+	AUD_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
+static struct clk_regmap mst_d_lrclk_div =
+	AUD_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
+static struct clk_regmap mst_e_lrclk_div =
+	AUD_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
+static struct clk_regmap mst_f_lrclk_div =
+	AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
+
+static struct clk_regmap mst_a_lrclk =
+	AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
+static struct clk_regmap mst_b_lrclk =
+	AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
+static struct clk_regmap mst_c_lrclk =
+	AUD_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1);
+static struct clk_regmap mst_d_lrclk =
+	AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
+static struct clk_regmap mst_e_lrclk =
+	AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
+static struct clk_regmap mst_f_lrclk =
+	AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
+
+static struct clk_regmap tdmin_a_sclk_sel =
+	AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL);
+static struct clk_regmap tdmin_b_sclk_sel =
+	AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL);
+static struct clk_regmap tdmin_c_sclk_sel =
+	AUD_TDM_SCLK_MUX(in_c, AUDIO_CLK_TDMIN_C_CTRL);
+static struct clk_regmap tdmin_lb_sclk_sel =
+	AUD_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
+static struct clk_regmap tdmout_a_sclk_sel =
+	AUD_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
+static struct clk_regmap tdmout_b_sclk_sel =
+	AUD_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
+static struct clk_regmap tdmout_c_sclk_sel =
+	AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
+
+static struct clk_regmap tdmin_a_sclk_pre_en =
+	AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
+static struct clk_regmap tdmin_b_sclk_pre_en =
+	AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
+static struct clk_regmap tdmin_c_sclk_pre_en =
+	AUD_TDM_SCLK_PRE_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
+static struct clk_regmap tdmin_lb_sclk_pre_en =
+	AUD_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
+static struct clk_regmap tdmout_a_sclk_pre_en =
+	AUD_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
+static struct clk_regmap tdmout_b_sclk_pre_en =
+	AUD_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
+static struct clk_regmap tdmout_c_sclk_pre_en =
+	AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
+
+static struct clk_regmap tdmin_a_sclk_post_en =
+	AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
+static struct clk_regmap tdmin_b_sclk_post_en =
+	AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
+static struct clk_regmap tdmin_c_sclk_post_en =
+	AUD_TDM_SCLK_POST_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
+static struct clk_regmap tdmin_lb_sclk_post_en =
+	AUD_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
+static struct clk_regmap tdmout_a_sclk_post_en =
+	AUD_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
+static struct clk_regmap tdmout_b_sclk_post_en =
+	AUD_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
+static struct clk_regmap tdmout_c_sclk_post_en =
+	AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
+
+static struct clk_regmap tdmin_a_sclk =
+	AUD_TDM_SCLK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
+static struct clk_regmap tdmin_b_sclk =
+	AUD_TDM_SCLK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
+static struct clk_regmap tdmin_c_sclk =
+	AUD_TDM_SCLK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
+static struct clk_regmap tdmin_lb_sclk =
+	AUD_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
+static struct clk_regmap tdmout_a_sclk =
+	AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
+static struct clk_regmap tdmout_b_sclk =
+	AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
+static struct clk_regmap tdmout_c_sclk =
+	AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
+
+static struct clk_regmap tdmin_a_lrclk =
+	AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
+static struct clk_regmap tdmin_b_lrclk =
+	AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
+static struct clk_regmap tdmin_c_lrclk =
+	AUD_TDM_LRLCK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
+static struct clk_regmap tdmin_lb_lrclk =
+	AUD_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
+static struct clk_regmap tdmout_a_lrclk =
+	AUD_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
+static struct clk_regmap tdmout_b_lrclk =
+	AUD_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
+static struct clk_regmap tdmout_c_lrclk =
+	AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
+
+/* AXG/G12A Clocks */
+static struct clk_regmap mst_a_mclk_sel =
+	AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
+static struct clk_regmap mst_b_mclk_sel =
+	AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL);
+static struct clk_regmap mst_c_mclk_sel =
+	AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL);
+static struct clk_regmap mst_d_mclk_sel =
+	AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL);
+static struct clk_regmap mst_e_mclk_sel =
+	AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL);
+static struct clk_regmap mst_f_mclk_sel =
+	AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL);
+
+static struct clk_regmap mst_a_mclk_div =
+	AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL);
+static struct clk_regmap mst_b_mclk_div =
+	AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL);
+static struct clk_regmap mst_c_mclk_div =
+	AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL);
+static struct clk_regmap mst_d_mclk_div =
+	AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL);
+static struct clk_regmap mst_e_mclk_div =
+	AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL);
+static struct clk_regmap mst_f_mclk_div =
+	AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL);
+
+static struct clk_regmap mst_a_mclk =
+	AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);
+static struct clk_regmap mst_b_mclk =
+	AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL);
+static struct clk_regmap mst_c_mclk =
+	AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL);
+static struct clk_regmap mst_d_mclk =
+	AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL);
+static struct clk_regmap mst_e_mclk =
+	AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_MCLK_E_CTRL);
+static struct clk_regmap mst_f_mclk =
+	AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_MCLK_F_CTRL);
+
+/* G12a clocks */
+static struct clk_regmap g12a_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL(
+	mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data);
+static struct clk_regmap g12a_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL(
+	mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data);
+static struct clk_regmap g12a_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL(
+	lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data);
+static struct clk_regmap g12a_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL(
+	lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data);
+static struct clk_regmap g12a_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL(
+	lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data);
+static struct clk_regmap g12a_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL(
+	sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data);
+static struct clk_regmap g12a_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL(
+	sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data);
+static struct clk_regmap g12a_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
+	sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data);
+
+/* G12a/SM1 clocks */
+static struct clk_regmap spdifout_b = AUD_PCLK_GATE(spdifout_b,   21);
 
 /*
  * Array of all clocks provided by this provider
@@ -473,127 +570,127 @@ static AUD_TDM_PAD_CTRL(sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8,
  */
 static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
 	.hws = {
-		[AUD_CLKID_DDR_ARB]		= &aud_ddr_arb.hw,
-		[AUD_CLKID_PDM]			= &aud_pdm.hw,
-		[AUD_CLKID_TDMIN_A]		= &aud_tdmin_a.hw,
-		[AUD_CLKID_TDMIN_B]		= &aud_tdmin_b.hw,
-		[AUD_CLKID_TDMIN_C]		= &aud_tdmin_c.hw,
-		[AUD_CLKID_TDMIN_LB]		= &aud_tdmin_lb.hw,
-		[AUD_CLKID_TDMOUT_A]		= &aud_tdmout_a.hw,
-		[AUD_CLKID_TDMOUT_B]		= &aud_tdmout_b.hw,
-		[AUD_CLKID_TDMOUT_C]		= &aud_tdmout_c.hw,
-		[AUD_CLKID_FRDDR_A]		= &aud_frddr_a.hw,
-		[AUD_CLKID_FRDDR_B]		= &aud_frddr_b.hw,
-		[AUD_CLKID_FRDDR_C]		= &aud_frddr_c.hw,
-		[AUD_CLKID_TODDR_A]		= &aud_toddr_a.hw,
-		[AUD_CLKID_TODDR_B]		= &aud_toddr_b.hw,
-		[AUD_CLKID_TODDR_C]		= &aud_toddr_c.hw,
-		[AUD_CLKID_LOOPBACK]		= &aud_loopback.hw,
-		[AUD_CLKID_SPDIFIN]		= &aud_spdifin.hw,
-		[AUD_CLKID_SPDIFOUT]		= &aud_spdifout.hw,
-		[AUD_CLKID_RESAMPLE]		= &aud_resample.hw,
-		[AUD_CLKID_POWER_DETECT]	= &aud_power_detect.hw,
-		[AUD_CLKID_MST_A_MCLK_SEL]	= &aud_mst_a_mclk_sel.hw,
-		[AUD_CLKID_MST_B_MCLK_SEL]	= &aud_mst_b_mclk_sel.hw,
-		[AUD_CLKID_MST_C_MCLK_SEL]	= &aud_mst_c_mclk_sel.hw,
-		[AUD_CLKID_MST_D_MCLK_SEL]	= &aud_mst_d_mclk_sel.hw,
-		[AUD_CLKID_MST_E_MCLK_SEL]	= &aud_mst_e_mclk_sel.hw,
-		[AUD_CLKID_MST_F_MCLK_SEL]	= &aud_mst_f_mclk_sel.hw,
-		[AUD_CLKID_MST_A_MCLK_DIV]	= &aud_mst_a_mclk_div.hw,
-		[AUD_CLKID_MST_B_MCLK_DIV]	= &aud_mst_b_mclk_div.hw,
-		[AUD_CLKID_MST_C_MCLK_DIV]	= &aud_mst_c_mclk_div.hw,
-		[AUD_CLKID_MST_D_MCLK_DIV]	= &aud_mst_d_mclk_div.hw,
-		[AUD_CLKID_MST_E_MCLK_DIV]	= &aud_mst_e_mclk_div.hw,
-		[AUD_CLKID_MST_F_MCLK_DIV]	= &aud_mst_f_mclk_div.hw,
-		[AUD_CLKID_MST_A_MCLK]		= &aud_mst_a_mclk.hw,
-		[AUD_CLKID_MST_B_MCLK]		= &aud_mst_b_mclk.hw,
-		[AUD_CLKID_MST_C_MCLK]		= &aud_mst_c_mclk.hw,
-		[AUD_CLKID_MST_D_MCLK]		= &aud_mst_d_mclk.hw,
-		[AUD_CLKID_MST_E_MCLK]		= &aud_mst_e_mclk.hw,
-		[AUD_CLKID_MST_F_MCLK]		= &aud_mst_f_mclk.hw,
-		[AUD_CLKID_SPDIFOUT_CLK_SEL]	= &aud_spdifout_clk_sel.hw,
-		[AUD_CLKID_SPDIFOUT_CLK_DIV]	= &aud_spdifout_clk_div.hw,
-		[AUD_CLKID_SPDIFOUT_CLK]	= &aud_spdifout_clk.hw,
-		[AUD_CLKID_SPDIFIN_CLK_SEL]	= &aud_spdifin_clk_sel.hw,
-		[AUD_CLKID_SPDIFIN_CLK_DIV]	= &aud_spdifin_clk_div.hw,
-		[AUD_CLKID_SPDIFIN_CLK]		= &aud_spdifin_clk.hw,
-		[AUD_CLKID_PDM_DCLK_SEL]	= &aud_pdm_dclk_sel.hw,
-		[AUD_CLKID_PDM_DCLK_DIV]	= &aud_pdm_dclk_div.hw,
-		[AUD_CLKID_PDM_DCLK]		= &aud_pdm_dclk.hw,
-		[AUD_CLKID_PDM_SYSCLK_SEL]	= &aud_pdm_sysclk_sel.hw,
-		[AUD_CLKID_PDM_SYSCLK_DIV]	= &aud_pdm_sysclk_div.hw,
-		[AUD_CLKID_PDM_SYSCLK]		= &aud_pdm_sysclk.hw,
-		[AUD_CLKID_MST_A_SCLK_PRE_EN]	= &aud_mst_a_sclk_pre_en.hw,
-		[AUD_CLKID_MST_B_SCLK_PRE_EN]	= &aud_mst_b_sclk_pre_en.hw,
-		[AUD_CLKID_MST_C_SCLK_PRE_EN]	= &aud_mst_c_sclk_pre_en.hw,
-		[AUD_CLKID_MST_D_SCLK_PRE_EN]	= &aud_mst_d_sclk_pre_en.hw,
-		[AUD_CLKID_MST_E_SCLK_PRE_EN]	= &aud_mst_e_sclk_pre_en.hw,
-		[AUD_CLKID_MST_F_SCLK_PRE_EN]	= &aud_mst_f_sclk_pre_en.hw,
-		[AUD_CLKID_MST_A_SCLK_DIV]	= &aud_mst_a_sclk_div.hw,
-		[AUD_CLKID_MST_B_SCLK_DIV]	= &aud_mst_b_sclk_div.hw,
-		[AUD_CLKID_MST_C_SCLK_DIV]	= &aud_mst_c_sclk_div.hw,
-		[AUD_CLKID_MST_D_SCLK_DIV]	= &aud_mst_d_sclk_div.hw,
-		[AUD_CLKID_MST_E_SCLK_DIV]	= &aud_mst_e_sclk_div.hw,
-		[AUD_CLKID_MST_F_SCLK_DIV]	= &aud_mst_f_sclk_div.hw,
-		[AUD_CLKID_MST_A_SCLK_POST_EN]	= &aud_mst_a_sclk_post_en.hw,
-		[AUD_CLKID_MST_B_SCLK_POST_EN]	= &aud_mst_b_sclk_post_en.hw,
-		[AUD_CLKID_MST_C_SCLK_POST_EN]	= &aud_mst_c_sclk_post_en.hw,
-		[AUD_CLKID_MST_D_SCLK_POST_EN]	= &aud_mst_d_sclk_post_en.hw,
-		[AUD_CLKID_MST_E_SCLK_POST_EN]	= &aud_mst_e_sclk_post_en.hw,
-		[AUD_CLKID_MST_F_SCLK_POST_EN]	= &aud_mst_f_sclk_post_en.hw,
-		[AUD_CLKID_MST_A_SCLK]		= &aud_mst_a_sclk.hw,
-		[AUD_CLKID_MST_B_SCLK]		= &aud_mst_b_sclk.hw,
-		[AUD_CLKID_MST_C_SCLK]		= &aud_mst_c_sclk.hw,
-		[AUD_CLKID_MST_D_SCLK]		= &aud_mst_d_sclk.hw,
-		[AUD_CLKID_MST_E_SCLK]		= &aud_mst_e_sclk.hw,
-		[AUD_CLKID_MST_F_SCLK]		= &aud_mst_f_sclk.hw,
-		[AUD_CLKID_MST_A_LRCLK_DIV]	= &aud_mst_a_lrclk_div.hw,
-		[AUD_CLKID_MST_B_LRCLK_DIV]	= &aud_mst_b_lrclk_div.hw,
-		[AUD_CLKID_MST_C_LRCLK_DIV]	= &aud_mst_c_lrclk_div.hw,
-		[AUD_CLKID_MST_D_LRCLK_DIV]	= &aud_mst_d_lrclk_div.hw,
-		[AUD_CLKID_MST_E_LRCLK_DIV]	= &aud_mst_e_lrclk_div.hw,
-		[AUD_CLKID_MST_F_LRCLK_DIV]	= &aud_mst_f_lrclk_div.hw,
-		[AUD_CLKID_MST_A_LRCLK]		= &aud_mst_a_lrclk.hw,
-		[AUD_CLKID_MST_B_LRCLK]		= &aud_mst_b_lrclk.hw,
-		[AUD_CLKID_MST_C_LRCLK]		= &aud_mst_c_lrclk.hw,
-		[AUD_CLKID_MST_D_LRCLK]		= &aud_mst_d_lrclk.hw,
-		[AUD_CLKID_MST_E_LRCLK]		= &aud_mst_e_lrclk.hw,
-		[AUD_CLKID_MST_F_LRCLK]		= &aud_mst_f_lrclk.hw,
-		[AUD_CLKID_TDMIN_A_SCLK_SEL]	= &aud_tdmin_a_sclk_sel.hw,
-		[AUD_CLKID_TDMIN_B_SCLK_SEL]	= &aud_tdmin_b_sclk_sel.hw,
-		[AUD_CLKID_TDMIN_C_SCLK_SEL]	= &aud_tdmin_c_sclk_sel.hw,
-		[AUD_CLKID_TDMIN_LB_SCLK_SEL]	= &aud_tdmin_lb_sclk_sel.hw,
-		[AUD_CLKID_TDMOUT_A_SCLK_SEL]	= &aud_tdmout_a_sclk_sel.hw,
-		[AUD_CLKID_TDMOUT_B_SCLK_SEL]	= &aud_tdmout_b_sclk_sel.hw,
-		[AUD_CLKID_TDMOUT_C_SCLK_SEL]	= &aud_tdmout_c_sclk_sel.hw,
-		[AUD_CLKID_TDMIN_A_SCLK_PRE_EN]	= &aud_tdmin_a_sclk_pre_en.hw,
-		[AUD_CLKID_TDMIN_B_SCLK_PRE_EN]	= &aud_tdmin_b_sclk_pre_en.hw,
-		[AUD_CLKID_TDMIN_C_SCLK_PRE_EN]	= &aud_tdmin_c_sclk_pre_en.hw,
-		[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &aud_tdmin_lb_sclk_pre_en.hw,
-		[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &aud_tdmout_a_sclk_pre_en.hw,
-		[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &aud_tdmout_b_sclk_pre_en.hw,
-		[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &aud_tdmout_c_sclk_pre_en.hw,
-		[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &aud_tdmin_a_sclk_post_en.hw,
-		[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &aud_tdmin_b_sclk_post_en.hw,
-		[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &aud_tdmin_c_sclk_post_en.hw,
-		[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &aud_tdmin_lb_sclk_post_en.hw,
-		[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &aud_tdmout_a_sclk_post_en.hw,
-		[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &aud_tdmout_b_sclk_post_en.hw,
-		[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &aud_tdmout_c_sclk_post_en.hw,
-		[AUD_CLKID_TDMIN_A_SCLK]	= &aud_tdmin_a_sclk.hw,
-		[AUD_CLKID_TDMIN_B_SCLK]	= &aud_tdmin_b_sclk.hw,
-		[AUD_CLKID_TDMIN_C_SCLK]	= &aud_tdmin_c_sclk.hw,
-		[AUD_CLKID_TDMIN_LB_SCLK]	= &aud_tdmin_lb_sclk.hw,
-		[AUD_CLKID_TDMOUT_A_SCLK]	= &aud_tdmout_a_sclk.hw,
-		[AUD_CLKID_TDMOUT_B_SCLK]	= &aud_tdmout_b_sclk.hw,
-		[AUD_CLKID_TDMOUT_C_SCLK]	= &aud_tdmout_c_sclk.hw,
-		[AUD_CLKID_TDMIN_A_LRCLK]	= &aud_tdmin_a_lrclk.hw,
-		[AUD_CLKID_TDMIN_B_LRCLK]	= &aud_tdmin_b_lrclk.hw,
-		[AUD_CLKID_TDMIN_C_LRCLK]	= &aud_tdmin_c_lrclk.hw,
-		[AUD_CLKID_TDMIN_LB_LRCLK]	= &aud_tdmin_lb_lrclk.hw,
-		[AUD_CLKID_TDMOUT_A_LRCLK]	= &aud_tdmout_a_lrclk.hw,
-		[AUD_CLKID_TDMOUT_B_LRCLK]	= &aud_tdmout_b_lrclk.hw,
-		[AUD_CLKID_TDMOUT_C_LRCLK]	= &aud_tdmout_c_lrclk.hw,
+		[AUD_CLKID_DDR_ARB]		= &ddr_arb.hw,
+		[AUD_CLKID_PDM]			= &pdm.hw,
+		[AUD_CLKID_TDMIN_A]		= &tdmin_a.hw,
+		[AUD_CLKID_TDMIN_B]		= &tdmin_b.hw,
+		[AUD_CLKID_TDMIN_C]		= &tdmin_c.hw,
+		[AUD_CLKID_TDMIN_LB]		= &tdmin_lb.hw,
+		[AUD_CLKID_TDMOUT_A]		= &tdmout_a.hw,
+		[AUD_CLKID_TDMOUT_B]		= &tdmout_b.hw,
+		[AUD_CLKID_TDMOUT_C]		= &tdmout_c.hw,
+		[AUD_CLKID_FRDDR_A]		= &frddr_a.hw,
+		[AUD_CLKID_FRDDR_B]		= &frddr_b.hw,
+		[AUD_CLKID_FRDDR_C]		= &frddr_c.hw,
+		[AUD_CLKID_TODDR_A]		= &toddr_a.hw,
+		[AUD_CLKID_TODDR_B]		= &toddr_b.hw,
+		[AUD_CLKID_TODDR_C]		= &toddr_c.hw,
+		[AUD_CLKID_LOOPBACK]		= &loopback.hw,
+		[AUD_CLKID_SPDIFIN]		= &spdifin.hw,
+		[AUD_CLKID_SPDIFOUT]		= &spdifout.hw,
+		[AUD_CLKID_RESAMPLE]		= &resample.hw,
+		[AUD_CLKID_POWER_DETECT]	= &power_detect.hw,
+		[AUD_CLKID_MST_A_MCLK_SEL]	= &mst_a_mclk_sel.hw,
+		[AUD_CLKID_MST_B_MCLK_SEL]	= &mst_b_mclk_sel.hw,
+		[AUD_CLKID_MST_C_MCLK_SEL]	= &mst_c_mclk_sel.hw,
+		[AUD_CLKID_MST_D_MCLK_SEL]	= &mst_d_mclk_sel.hw,
+		[AUD_CLKID_MST_E_MCLK_SEL]	= &mst_e_mclk_sel.hw,
+		[AUD_CLKID_MST_F_MCLK_SEL]	= &mst_f_mclk_sel.hw,
+		[AUD_CLKID_MST_A_MCLK_DIV]	= &mst_a_mclk_div.hw,
+		[AUD_CLKID_MST_B_MCLK_DIV]	= &mst_b_mclk_div.hw,
+		[AUD_CLKID_MST_C_MCLK_DIV]	= &mst_c_mclk_div.hw,
+		[AUD_CLKID_MST_D_MCLK_DIV]	= &mst_d_mclk_div.hw,
+		[AUD_CLKID_MST_E_MCLK_DIV]	= &mst_e_mclk_div.hw,
+		[AUD_CLKID_MST_F_MCLK_DIV]	= &mst_f_mclk_div.hw,
+		[AUD_CLKID_MST_A_MCLK]		= &mst_a_mclk.hw,
+		[AUD_CLKID_MST_B_MCLK]		= &mst_b_mclk.hw,
+		[AUD_CLKID_MST_C_MCLK]		= &mst_c_mclk.hw,
+		[AUD_CLKID_MST_D_MCLK]		= &mst_d_mclk.hw,
+		[AUD_CLKID_MST_E_MCLK]		= &mst_e_mclk.hw,
+		[AUD_CLKID_MST_F_MCLK]		= &mst_f_mclk.hw,
+		[AUD_CLKID_SPDIFOUT_CLK_SEL]	= &spdifout_clk_sel.hw,
+		[AUD_CLKID_SPDIFOUT_CLK_DIV]	= &spdifout_clk_div.hw,
+		[AUD_CLKID_SPDIFOUT_CLK]	= &spdifout_clk.hw,
+		[AUD_CLKID_SPDIFIN_CLK_SEL]	= &spdifin_clk_sel.hw,
+		[AUD_CLKID_SPDIFIN_CLK_DIV]	= &spdifin_clk_div.hw,
+		[AUD_CLKID_SPDIFIN_CLK]		= &spdifin_clk.hw,
+		[AUD_CLKID_PDM_DCLK_SEL]	= &pdm_dclk_sel.hw,
+		[AUD_CLKID_PDM_DCLK_DIV]	= &pdm_dclk_div.hw,
+		[AUD_CLKID_PDM_DCLK]		= &pdm_dclk.hw,
+		[AUD_CLKID_PDM_SYSCLK_SEL]	= &pdm_sysclk_sel.hw,
+		[AUD_CLKID_PDM_SYSCLK_DIV]	= &pdm_sysclk_div.hw,
+		[AUD_CLKID_PDM_SYSCLK]		= &pdm_sysclk.hw,
+		[AUD_CLKID_MST_A_SCLK_PRE_EN]	= &mst_a_sclk_pre_en.hw,
+		[AUD_CLKID_MST_B_SCLK_PRE_EN]	= &mst_b_sclk_pre_en.hw,
+		[AUD_CLKID_MST_C_SCLK_PRE_EN]	= &mst_c_sclk_pre_en.hw,
+		[AUD_CLKID_MST_D_SCLK_PRE_EN]	= &mst_d_sclk_pre_en.hw,
+		[AUD_CLKID_MST_E_SCLK_PRE_EN]	= &mst_e_sclk_pre_en.hw,
+		[AUD_CLKID_MST_F_SCLK_PRE_EN]	= &mst_f_sclk_pre_en.hw,
+		[AUD_CLKID_MST_A_SCLK_DIV]	= &mst_a_sclk_div.hw,
+		[AUD_CLKID_MST_B_SCLK_DIV]	= &mst_b_sclk_div.hw,
+		[AUD_CLKID_MST_C_SCLK_DIV]	= &mst_c_sclk_div.hw,
+		[AUD_CLKID_MST_D_SCLK_DIV]	= &mst_d_sclk_div.hw,
+		[AUD_CLKID_MST_E_SCLK_DIV]	= &mst_e_sclk_div.hw,
+		[AUD_CLKID_MST_F_SCLK_DIV]	= &mst_f_sclk_div.hw,
+		[AUD_CLKID_MST_A_SCLK_POST_EN]	= &mst_a_sclk_post_en.hw,
+		[AUD_CLKID_MST_B_SCLK_POST_EN]	= &mst_b_sclk_post_en.hw,
+		[AUD_CLKID_MST_C_SCLK_POST_EN]	= &mst_c_sclk_post_en.hw,
+		[AUD_CLKID_MST_D_SCLK_POST_EN]	= &mst_d_sclk_post_en.hw,
+		[AUD_CLKID_MST_E_SCLK_POST_EN]	= &mst_e_sclk_post_en.hw,
+		[AUD_CLKID_MST_F_SCLK_POST_EN]	= &mst_f_sclk_post_en.hw,
+		[AUD_CLKID_MST_A_SCLK]		= &mst_a_sclk.hw,
+		[AUD_CLKID_MST_B_SCLK]		= &mst_b_sclk.hw,
+		[AUD_CLKID_MST_C_SCLK]		= &mst_c_sclk.hw,
+		[AUD_CLKID_MST_D_SCLK]		= &mst_d_sclk.hw,
+		[AUD_CLKID_MST_E_SCLK]		= &mst_e_sclk.hw,
+		[AUD_CLKID_MST_F_SCLK]		= &mst_f_sclk.hw,
+		[AUD_CLKID_MST_A_LRCLK_DIV]	= &mst_a_lrclk_div.hw,
+		[AUD_CLKID_MST_B_LRCLK_DIV]	= &mst_b_lrclk_div.hw,
+		[AUD_CLKID_MST_C_LRCLK_DIV]	= &mst_c_lrclk_div.hw,
+		[AUD_CLKID_MST_D_LRCLK_DIV]	= &mst_d_lrclk_div.hw,
+		[AUD_CLKID_MST_E_LRCLK_DIV]	= &mst_e_lrclk_div.hw,
+		[AUD_CLKID_MST_F_LRCLK_DIV]	= &mst_f_lrclk_div.hw,
+		[AUD_CLKID_MST_A_LRCLK]		= &mst_a_lrclk.hw,
+		[AUD_CLKID_MST_B_LRCLK]		= &mst_b_lrclk.hw,
+		[AUD_CLKID_MST_C_LRCLK]		= &mst_c_lrclk.hw,
+		[AUD_CLKID_MST_D_LRCLK]		= &mst_d_lrclk.hw,
+		[AUD_CLKID_MST_E_LRCLK]		= &mst_e_lrclk.hw,
+		[AUD_CLKID_MST_F_LRCLK]		= &mst_f_lrclk.hw,
+		[AUD_CLKID_TDMIN_A_SCLK_SEL]	= &tdmin_a_sclk_sel.hw,
+		[AUD_CLKID_TDMIN_B_SCLK_SEL]	= &tdmin_b_sclk_sel.hw,
+		[AUD_CLKID_TDMIN_C_SCLK_SEL]	= &tdmin_c_sclk_sel.hw,
+		[AUD_CLKID_TDMIN_LB_SCLK_SEL]	= &tdmin_lb_sclk_sel.hw,
+		[AUD_CLKID_TDMOUT_A_SCLK_SEL]	= &tdmout_a_sclk_sel.hw,
+		[AUD_CLKID_TDMOUT_B_SCLK_SEL]	= &tdmout_b_sclk_sel.hw,
+		[AUD_CLKID_TDMOUT_C_SCLK_SEL]	= &tdmout_c_sclk_sel.hw,
+		[AUD_CLKID_TDMIN_A_SCLK_PRE_EN]	= &tdmin_a_sclk_pre_en.hw,
+		[AUD_CLKID_TDMIN_B_SCLK_PRE_EN]	= &tdmin_b_sclk_pre_en.hw,
+		[AUD_CLKID_TDMIN_C_SCLK_PRE_EN]	= &tdmin_c_sclk_pre_en.hw,
+		[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
+		[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
+		[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
+		[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
+		[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
+		[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
+		[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
+		[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
+		[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
+		[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
+		[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
+		[AUD_CLKID_TDMIN_A_SCLK]	= &tdmin_a_sclk.hw,
+		[AUD_CLKID_TDMIN_B_SCLK]	= &tdmin_b_sclk.hw,
+		[AUD_CLKID_TDMIN_C_SCLK]	= &tdmin_c_sclk.hw,
+		[AUD_CLKID_TDMIN_LB_SCLK]	= &tdmin_lb_sclk.hw,
+		[AUD_CLKID_TDMOUT_A_SCLK]	= &tdmout_a_sclk.hw,
+		[AUD_CLKID_TDMOUT_B_SCLK]	= &tdmout_b_sclk.hw,
+		[AUD_CLKID_TDMOUT_C_SCLK]	= &tdmout_c_sclk.hw,
+		[AUD_CLKID_TDMIN_A_LRCLK]	= &tdmin_a_lrclk.hw,
+		[AUD_CLKID_TDMIN_B_LRCLK]	= &tdmin_b_lrclk.hw,
+		[AUD_CLKID_TDMIN_C_LRCLK]	= &tdmin_c_lrclk.hw,
+		[AUD_CLKID_TDMIN_LB_LRCLK]	= &tdmin_lb_lrclk.hw,
+		[AUD_CLKID_TDMOUT_A_LRCLK]	= &tdmout_a_lrclk.hw,
+		[AUD_CLKID_TDMOUT_B_LRCLK]	= &tdmout_b_lrclk.hw,
+		[AUD_CLKID_TDMOUT_C_LRCLK]	= &tdmout_c_lrclk.hw,
 		[NR_CLKS] = NULL,
 	},
 	.num = NR_CLKS,
@@ -605,139 +702,139 @@ static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
  */
 static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
 	.hws = {
-		[AUD_CLKID_DDR_ARB]		= &aud_ddr_arb.hw,
-		[AUD_CLKID_PDM]			= &aud_pdm.hw,
-		[AUD_CLKID_TDMIN_A]		= &aud_tdmin_a.hw,
-		[AUD_CLKID_TDMIN_B]		= &aud_tdmin_b.hw,
-		[AUD_CLKID_TDMIN_C]		= &aud_tdmin_c.hw,
-		[AUD_CLKID_TDMIN_LB]		= &aud_tdmin_lb.hw,
-		[AUD_CLKID_TDMOUT_A]		= &aud_tdmout_a.hw,
-		[AUD_CLKID_TDMOUT_B]		= &aud_tdmout_b.hw,
-		[AUD_CLKID_TDMOUT_C]		= &aud_tdmout_c.hw,
-		[AUD_CLKID_FRDDR_A]		= &aud_frddr_a.hw,
-		[AUD_CLKID_FRDDR_B]		= &aud_frddr_b.hw,
-		[AUD_CLKID_FRDDR_C]		= &aud_frddr_c.hw,
-		[AUD_CLKID_TODDR_A]		= &aud_toddr_a.hw,
-		[AUD_CLKID_TODDR_B]		= &aud_toddr_b.hw,
-		[AUD_CLKID_TODDR_C]		= &aud_toddr_c.hw,
-		[AUD_CLKID_LOOPBACK]		= &aud_loopback.hw,
-		[AUD_CLKID_SPDIFIN]		= &aud_spdifin.hw,
-		[AUD_CLKID_SPDIFOUT]		= &aud_spdifout.hw,
-		[AUD_CLKID_RESAMPLE]		= &aud_resample.hw,
-		[AUD_CLKID_POWER_DETECT]	= &aud_power_detect.hw,
-		[AUD_CLKID_SPDIFOUT_B]		= &aud_spdifout_b.hw,
-		[AUD_CLKID_MST_A_MCLK_SEL]	= &aud_mst_a_mclk_sel.hw,
-		[AUD_CLKID_MST_B_MCLK_SEL]	= &aud_mst_b_mclk_sel.hw,
-		[AUD_CLKID_MST_C_MCLK_SEL]	= &aud_mst_c_mclk_sel.hw,
-		[AUD_CLKID_MST_D_MCLK_SEL]	= &aud_mst_d_mclk_sel.hw,
-		[AUD_CLKID_MST_E_MCLK_SEL]	= &aud_mst_e_mclk_sel.hw,
-		[AUD_CLKID_MST_F_MCLK_SEL]	= &aud_mst_f_mclk_sel.hw,
-		[AUD_CLKID_MST_A_MCLK_DIV]	= &aud_mst_a_mclk_div.hw,
-		[AUD_CLKID_MST_B_MCLK_DIV]	= &aud_mst_b_mclk_div.hw,
-		[AUD_CLKID_MST_C_MCLK_DIV]	= &aud_mst_c_mclk_div.hw,
-		[AUD_CLKID_MST_D_MCLK_DIV]	= &aud_mst_d_mclk_div.hw,
-		[AUD_CLKID_MST_E_MCLK_DIV]	= &aud_mst_e_mclk_div.hw,
-		[AUD_CLKID_MST_F_MCLK_DIV]	= &aud_mst_f_mclk_div.hw,
-		[AUD_CLKID_MST_A_MCLK]		= &aud_mst_a_mclk.hw,
-		[AUD_CLKID_MST_B_MCLK]		= &aud_mst_b_mclk.hw,
-		[AUD_CLKID_MST_C_MCLK]		= &aud_mst_c_mclk.hw,
-		[AUD_CLKID_MST_D_MCLK]		= &aud_mst_d_mclk.hw,
-		[AUD_CLKID_MST_E_MCLK]		= &aud_mst_e_mclk.hw,
-		[AUD_CLKID_MST_F_MCLK]		= &aud_mst_f_mclk.hw,
-		[AUD_CLKID_SPDIFOUT_CLK_SEL]	= &aud_spdifout_clk_sel.hw,
-		[AUD_CLKID_SPDIFOUT_CLK_DIV]	= &aud_spdifout_clk_div.hw,
-		[AUD_CLKID_SPDIFOUT_CLK]	= &aud_spdifout_clk.hw,
-		[AUD_CLKID_SPDIFOUT_B_CLK_SEL]	= &aud_spdifout_b_clk_sel.hw,
-		[AUD_CLKID_SPDIFOUT_B_CLK_DIV]	= &aud_spdifout_b_clk_div.hw,
-		[AUD_CLKID_SPDIFOUT_B_CLK]	= &aud_spdifout_b_clk.hw,
-		[AUD_CLKID_SPDIFIN_CLK_SEL]	= &aud_spdifin_clk_sel.hw,
-		[AUD_CLKID_SPDIFIN_CLK_DIV]	= &aud_spdifin_clk_div.hw,
-		[AUD_CLKID_SPDIFIN_CLK]		= &aud_spdifin_clk.hw,
-		[AUD_CLKID_PDM_DCLK_SEL]	= &aud_pdm_dclk_sel.hw,
-		[AUD_CLKID_PDM_DCLK_DIV]	= &aud_pdm_dclk_div.hw,
-		[AUD_CLKID_PDM_DCLK]		= &aud_pdm_dclk.hw,
-		[AUD_CLKID_PDM_SYSCLK_SEL]	= &aud_pdm_sysclk_sel.hw,
-		[AUD_CLKID_PDM_SYSCLK_DIV]	= &aud_pdm_sysclk_div.hw,
-		[AUD_CLKID_PDM_SYSCLK]		= &aud_pdm_sysclk.hw,
-		[AUD_CLKID_MST_A_SCLK_PRE_EN]	= &aud_mst_a_sclk_pre_en.hw,
-		[AUD_CLKID_MST_B_SCLK_PRE_EN]	= &aud_mst_b_sclk_pre_en.hw,
-		[AUD_CLKID_MST_C_SCLK_PRE_EN]	= &aud_mst_c_sclk_pre_en.hw,
-		[AUD_CLKID_MST_D_SCLK_PRE_EN]	= &aud_mst_d_sclk_pre_en.hw,
-		[AUD_CLKID_MST_E_SCLK_PRE_EN]	= &aud_mst_e_sclk_pre_en.hw,
-		[AUD_CLKID_MST_F_SCLK_PRE_EN]	= &aud_mst_f_sclk_pre_en.hw,
-		[AUD_CLKID_MST_A_SCLK_DIV]	= &aud_mst_a_sclk_div.hw,
-		[AUD_CLKID_MST_B_SCLK_DIV]	= &aud_mst_b_sclk_div.hw,
-		[AUD_CLKID_MST_C_SCLK_DIV]	= &aud_mst_c_sclk_div.hw,
-		[AUD_CLKID_MST_D_SCLK_DIV]	= &aud_mst_d_sclk_div.hw,
-		[AUD_CLKID_MST_E_SCLK_DIV]	= &aud_mst_e_sclk_div.hw,
-		[AUD_CLKID_MST_F_SCLK_DIV]	= &aud_mst_f_sclk_div.hw,
-		[AUD_CLKID_MST_A_SCLK_POST_EN]	= &aud_mst_a_sclk_post_en.hw,
-		[AUD_CLKID_MST_B_SCLK_POST_EN]	= &aud_mst_b_sclk_post_en.hw,
-		[AUD_CLKID_MST_C_SCLK_POST_EN]	= &aud_mst_c_sclk_post_en.hw,
-		[AUD_CLKID_MST_D_SCLK_POST_EN]	= &aud_mst_d_sclk_post_en.hw,
-		[AUD_CLKID_MST_E_SCLK_POST_EN]	= &aud_mst_e_sclk_post_en.hw,
-		[AUD_CLKID_MST_F_SCLK_POST_EN]	= &aud_mst_f_sclk_post_en.hw,
-		[AUD_CLKID_MST_A_SCLK]		= &aud_mst_a_sclk.hw,
-		[AUD_CLKID_MST_B_SCLK]		= &aud_mst_b_sclk.hw,
-		[AUD_CLKID_MST_C_SCLK]		= &aud_mst_c_sclk.hw,
-		[AUD_CLKID_MST_D_SCLK]		= &aud_mst_d_sclk.hw,
-		[AUD_CLKID_MST_E_SCLK]		= &aud_mst_e_sclk.hw,
-		[AUD_CLKID_MST_F_SCLK]		= &aud_mst_f_sclk.hw,
-		[AUD_CLKID_MST_A_LRCLK_DIV]	= &aud_mst_a_lrclk_div.hw,
-		[AUD_CLKID_MST_B_LRCLK_DIV]	= &aud_mst_b_lrclk_div.hw,
-		[AUD_CLKID_MST_C_LRCLK_DIV]	= &aud_mst_c_lrclk_div.hw,
-		[AUD_CLKID_MST_D_LRCLK_DIV]	= &aud_mst_d_lrclk_div.hw,
-		[AUD_CLKID_MST_E_LRCLK_DIV]	= &aud_mst_e_lrclk_div.hw,
-		[AUD_CLKID_MST_F_LRCLK_DIV]	= &aud_mst_f_lrclk_div.hw,
-		[AUD_CLKID_MST_A_LRCLK]		= &aud_mst_a_lrclk.hw,
-		[AUD_CLKID_MST_B_LRCLK]		= &aud_mst_b_lrclk.hw,
-		[AUD_CLKID_MST_C_LRCLK]		= &aud_mst_c_lrclk.hw,
-		[AUD_CLKID_MST_D_LRCLK]		= &aud_mst_d_lrclk.hw,
-		[AUD_CLKID_MST_E_LRCLK]		= &aud_mst_e_lrclk.hw,
-		[AUD_CLKID_MST_F_LRCLK]		= &aud_mst_f_lrclk.hw,
-		[AUD_CLKID_TDMIN_A_SCLK_SEL]	= &aud_tdmin_a_sclk_sel.hw,
-		[AUD_CLKID_TDMIN_B_SCLK_SEL]	= &aud_tdmin_b_sclk_sel.hw,
-		[AUD_CLKID_TDMIN_C_SCLK_SEL]	= &aud_tdmin_c_sclk_sel.hw,
-		[AUD_CLKID_TDMIN_LB_SCLK_SEL]	= &aud_tdmin_lb_sclk_sel.hw,
-		[AUD_CLKID_TDMOUT_A_SCLK_SEL]	= &aud_tdmout_a_sclk_sel.hw,
-		[AUD_CLKID_TDMOUT_B_SCLK_SEL]	= &aud_tdmout_b_sclk_sel.hw,
-		[AUD_CLKID_TDMOUT_C_SCLK_SEL]	= &aud_tdmout_c_sclk_sel.hw,
-		[AUD_CLKID_TDMIN_A_SCLK_PRE_EN]	= &aud_tdmin_a_sclk_pre_en.hw,
-		[AUD_CLKID_TDMIN_B_SCLK_PRE_EN]	= &aud_tdmin_b_sclk_pre_en.hw,
-		[AUD_CLKID_TDMIN_C_SCLK_PRE_EN]	= &aud_tdmin_c_sclk_pre_en.hw,
-		[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &aud_tdmin_lb_sclk_pre_en.hw,
-		[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &aud_tdmout_a_sclk_pre_en.hw,
-		[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &aud_tdmout_b_sclk_pre_en.hw,
-		[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &aud_tdmout_c_sclk_pre_en.hw,
-		[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &aud_tdmin_a_sclk_post_en.hw,
-		[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &aud_tdmin_b_sclk_post_en.hw,
-		[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &aud_tdmin_c_sclk_post_en.hw,
-		[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &aud_tdmin_lb_sclk_post_en.hw,
-		[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &aud_tdmout_a_sclk_post_en.hw,
-		[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &aud_tdmout_b_sclk_post_en.hw,
-		[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &aud_tdmout_c_sclk_post_en.hw,
-		[AUD_CLKID_TDMIN_A_SCLK]	= &aud_tdmin_a_sclk.hw,
-		[AUD_CLKID_TDMIN_B_SCLK]	= &aud_tdmin_b_sclk.hw,
-		[AUD_CLKID_TDMIN_C_SCLK]	= &aud_tdmin_c_sclk.hw,
-		[AUD_CLKID_TDMIN_LB_SCLK]	= &aud_tdmin_lb_sclk.hw,
-		[AUD_CLKID_TDMOUT_A_SCLK]	= &aud_tdmout_a_sclk.hw,
-		[AUD_CLKID_TDMOUT_B_SCLK]	= &aud_tdmout_b_sclk.hw,
-		[AUD_CLKID_TDMOUT_C_SCLK]	= &aud_tdmout_c_sclk.hw,
-		[AUD_CLKID_TDMIN_A_LRCLK]	= &aud_tdmin_a_lrclk.hw,
-		[AUD_CLKID_TDMIN_B_LRCLK]	= &aud_tdmin_b_lrclk.hw,
-		[AUD_CLKID_TDMIN_C_LRCLK]	= &aud_tdmin_c_lrclk.hw,
-		[AUD_CLKID_TDMIN_LB_LRCLK]	= &aud_tdmin_lb_lrclk.hw,
-		[AUD_CLKID_TDMOUT_A_LRCLK]	= &aud_tdmout_a_lrclk.hw,
-		[AUD_CLKID_TDMOUT_B_LRCLK]	= &aud_tdmout_b_lrclk.hw,
-		[AUD_CLKID_TDMOUT_C_LRCLK]	= &aud_tdmout_c_lrclk.hw,
-		[AUD_CLKID_TDM_MCLK_PAD0]	= &aud_tdm_mclk_pad_0.hw,
-		[AUD_CLKID_TDM_MCLK_PAD1]	= &aud_tdm_mclk_pad_1.hw,
-		[AUD_CLKID_TDM_LRCLK_PAD0]	= &aud_tdm_lrclk_pad_0.hw,
-		[AUD_CLKID_TDM_LRCLK_PAD1]	= &aud_tdm_lrclk_pad_1.hw,
-		[AUD_CLKID_TDM_LRCLK_PAD2]	= &aud_tdm_lrclk_pad_2.hw,
-		[AUD_CLKID_TDM_SCLK_PAD0]	= &aud_tdm_sclk_pad_0.hw,
-		[AUD_CLKID_TDM_SCLK_PAD1]	= &aud_tdm_sclk_pad_1.hw,
-		[AUD_CLKID_TDM_SCLK_PAD2]	= &aud_tdm_sclk_pad_2.hw,
+		[AUD_CLKID_DDR_ARB]		= &ddr_arb.hw,
+		[AUD_CLKID_PDM]			= &pdm.hw,
+		[AUD_CLKID_TDMIN_A]		= &tdmin_a.hw,
+		[AUD_CLKID_TDMIN_B]		= &tdmin_b.hw,
+		[AUD_CLKID_TDMIN_C]		= &tdmin_c.hw,
+		[AUD_CLKID_TDMIN_LB]		= &tdmin_lb.hw,
+		[AUD_CLKID_TDMOUT_A]		= &tdmout_a.hw,
+		[AUD_CLKID_TDMOUT_B]		= &tdmout_b.hw,
+		[AUD_CLKID_TDMOUT_C]		= &tdmout_c.hw,
+		[AUD_CLKID_FRDDR_A]		= &frddr_a.hw,
+		[AUD_CLKID_FRDDR_B]		= &frddr_b.hw,
+		[AUD_CLKID_FRDDR_C]		= &frddr_c.hw,
+		[AUD_CLKID_TODDR_A]		= &toddr_a.hw,
+		[AUD_CLKID_TODDR_B]		= &toddr_b.hw,
+		[AUD_CLKID_TODDR_C]		= &toddr_c.hw,
+		[AUD_CLKID_LOOPBACK]		= &loopback.hw,
+		[AUD_CLKID_SPDIFIN]		= &spdifin.hw,
+		[AUD_CLKID_SPDIFOUT]		= &spdifout.hw,
+		[AUD_CLKID_RESAMPLE]		= &resample.hw,
+		[AUD_CLKID_POWER_DETECT]	= &power_detect.hw,
+		[AUD_CLKID_SPDIFOUT_B]		= &spdifout_b.hw,
+		[AUD_CLKID_MST_A_MCLK_SEL]	= &mst_a_mclk_sel.hw,
+		[AUD_CLKID_MST_B_MCLK_SEL]	= &mst_b_mclk_sel.hw,
+		[AUD_CLKID_MST_C_MCLK_SEL]	= &mst_c_mclk_sel.hw,
+		[AUD_CLKID_MST_D_MCLK_SEL]	= &mst_d_mclk_sel.hw,
+		[AUD_CLKID_MST_E_MCLK_SEL]	= &mst_e_mclk_sel.hw,
+		[AUD_CLKID_MST_F_MCLK_SEL]	= &mst_f_mclk_sel.hw,
+		[AUD_CLKID_MST_A_MCLK_DIV]	= &mst_a_mclk_div.hw,
+		[AUD_CLKID_MST_B_MCLK_DIV]	= &mst_b_mclk_div.hw,
+		[AUD_CLKID_MST_C_MCLK_DIV]	= &mst_c_mclk_div.hw,
+		[AUD_CLKID_MST_D_MCLK_DIV]	= &mst_d_mclk_div.hw,
+		[AUD_CLKID_MST_E_MCLK_DIV]	= &mst_e_mclk_div.hw,
+		[AUD_CLKID_MST_F_MCLK_DIV]	= &mst_f_mclk_div.hw,
+		[AUD_CLKID_MST_A_MCLK]		= &mst_a_mclk.hw,
+		[AUD_CLKID_MST_B_MCLK]		= &mst_b_mclk.hw,
+		[AUD_CLKID_MST_C_MCLK]		= &mst_c_mclk.hw,
+		[AUD_CLKID_MST_D_MCLK]		= &mst_d_mclk.hw,
+		[AUD_CLKID_MST_E_MCLK]		= &mst_e_mclk.hw,
+		[AUD_CLKID_MST_F_MCLK]		= &mst_f_mclk.hw,
+		[AUD_CLKID_SPDIFOUT_CLK_SEL]	= &spdifout_clk_sel.hw,
+		[AUD_CLKID_SPDIFOUT_CLK_DIV]	= &spdifout_clk_div.hw,
+		[AUD_CLKID_SPDIFOUT_CLK]	= &spdifout_clk.hw,
+		[AUD_CLKID_SPDIFOUT_B_CLK_SEL]	= &spdifout_b_clk_sel.hw,
+		[AUD_CLKID_SPDIFOUT_B_CLK_DIV]	= &spdifout_b_clk_div.hw,
+		[AUD_CLKID_SPDIFOUT_B_CLK]	= &spdifout_b_clk.hw,
+		[AUD_CLKID_SPDIFIN_CLK_SEL]	= &spdifin_clk_sel.hw,
+		[AUD_CLKID_SPDIFIN_CLK_DIV]	= &spdifin_clk_div.hw,
+		[AUD_CLKID_SPDIFIN_CLK]		= &spdifin_clk.hw,
+		[AUD_CLKID_PDM_DCLK_SEL]	= &pdm_dclk_sel.hw,
+		[AUD_CLKID_PDM_DCLK_DIV]	= &pdm_dclk_div.hw,
+		[AUD_CLKID_PDM_DCLK]		= &pdm_dclk.hw,
+		[AUD_CLKID_PDM_SYSCLK_SEL]	= &pdm_sysclk_sel.hw,
+		[AUD_CLKID_PDM_SYSCLK_DIV]	= &pdm_sysclk_div.hw,
+		[AUD_CLKID_PDM_SYSCLK]		= &pdm_sysclk.hw,
+		[AUD_CLKID_MST_A_SCLK_PRE_EN]	= &mst_a_sclk_pre_en.hw,
+		[AUD_CLKID_MST_B_SCLK_PRE_EN]	= &mst_b_sclk_pre_en.hw,
+		[AUD_CLKID_MST_C_SCLK_PRE_EN]	= &mst_c_sclk_pre_en.hw,
+		[AUD_CLKID_MST_D_SCLK_PRE_EN]	= &mst_d_sclk_pre_en.hw,
+		[AUD_CLKID_MST_E_SCLK_PRE_EN]	= &mst_e_sclk_pre_en.hw,
+		[AUD_CLKID_MST_F_SCLK_PRE_EN]	= &mst_f_sclk_pre_en.hw,
+		[AUD_CLKID_MST_A_SCLK_DIV]	= &mst_a_sclk_div.hw,
+		[AUD_CLKID_MST_B_SCLK_DIV]	= &mst_b_sclk_div.hw,
+		[AUD_CLKID_MST_C_SCLK_DIV]	= &mst_c_sclk_div.hw,
+		[AUD_CLKID_MST_D_SCLK_DIV]	= &mst_d_sclk_div.hw,
+		[AUD_CLKID_MST_E_SCLK_DIV]	= &mst_e_sclk_div.hw,
+		[AUD_CLKID_MST_F_SCLK_DIV]	= &mst_f_sclk_div.hw,
+		[AUD_CLKID_MST_A_SCLK_POST_EN]	= &mst_a_sclk_post_en.hw,
+		[AUD_CLKID_MST_B_SCLK_POST_EN]	= &mst_b_sclk_post_en.hw,
+		[AUD_CLKID_MST_C_SCLK_POST_EN]	= &mst_c_sclk_post_en.hw,
+		[AUD_CLKID_MST_D_SCLK_POST_EN]	= &mst_d_sclk_post_en.hw,
+		[AUD_CLKID_MST_E_SCLK_POST_EN]	= &mst_e_sclk_post_en.hw,
+		[AUD_CLKID_MST_F_SCLK_POST_EN]	= &mst_f_sclk_post_en.hw,
+		[AUD_CLKID_MST_A_SCLK]		= &mst_a_sclk.hw,
+		[AUD_CLKID_MST_B_SCLK]		= &mst_b_sclk.hw,
+		[AUD_CLKID_MST_C_SCLK]		= &mst_c_sclk.hw,
+		[AUD_CLKID_MST_D_SCLK]		= &mst_d_sclk.hw,
+		[AUD_CLKID_MST_E_SCLK]		= &mst_e_sclk.hw,
+		[AUD_CLKID_MST_F_SCLK]		= &mst_f_sclk.hw,
+		[AUD_CLKID_MST_A_LRCLK_DIV]	= &mst_a_lrclk_div.hw,
+		[AUD_CLKID_MST_B_LRCLK_DIV]	= &mst_b_lrclk_div.hw,
+		[AUD_CLKID_MST_C_LRCLK_DIV]	= &mst_c_lrclk_div.hw,
+		[AUD_CLKID_MST_D_LRCLK_DIV]	= &mst_d_lrclk_div.hw,
+		[AUD_CLKID_MST_E_LRCLK_DIV]	= &mst_e_lrclk_div.hw,
+		[AUD_CLKID_MST_F_LRCLK_DIV]	= &mst_f_lrclk_div.hw,
+		[AUD_CLKID_MST_A_LRCLK]		= &mst_a_lrclk.hw,
+		[AUD_CLKID_MST_B_LRCLK]		= &mst_b_lrclk.hw,
+		[AUD_CLKID_MST_C_LRCLK]		= &mst_c_lrclk.hw,
+		[AUD_CLKID_MST_D_LRCLK]		= &mst_d_lrclk.hw,
+		[AUD_CLKID_MST_E_LRCLK]		= &mst_e_lrclk.hw,
+		[AUD_CLKID_MST_F_LRCLK]		= &mst_f_lrclk.hw,
+		[AUD_CLKID_TDMIN_A_SCLK_SEL]	= &tdmin_a_sclk_sel.hw,
+		[AUD_CLKID_TDMIN_B_SCLK_SEL]	= &tdmin_b_sclk_sel.hw,
+		[AUD_CLKID_TDMIN_C_SCLK_SEL]	= &tdmin_c_sclk_sel.hw,
+		[AUD_CLKID_TDMIN_LB_SCLK_SEL]	= &tdmin_lb_sclk_sel.hw,
+		[AUD_CLKID_TDMOUT_A_SCLK_SEL]	= &tdmout_a_sclk_sel.hw,
+		[AUD_CLKID_TDMOUT_B_SCLK_SEL]	= &tdmout_b_sclk_sel.hw,
+		[AUD_CLKID_TDMOUT_C_SCLK_SEL]	= &tdmout_c_sclk_sel.hw,
+		[AUD_CLKID_TDMIN_A_SCLK_PRE_EN]	= &tdmin_a_sclk_pre_en.hw,
+		[AUD_CLKID_TDMIN_B_SCLK_PRE_EN]	= &tdmin_b_sclk_pre_en.hw,
+		[AUD_CLKID_TDMIN_C_SCLK_PRE_EN]	= &tdmin_c_sclk_pre_en.hw,
+		[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
+		[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
+		[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
+		[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
+		[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
+		[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
+		[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
+		[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
+		[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
+		[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
+		[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
+		[AUD_CLKID_TDMIN_A_SCLK]	= &tdmin_a_sclk.hw,
+		[AUD_CLKID_TDMIN_B_SCLK]	= &tdmin_b_sclk.hw,
+		[AUD_CLKID_TDMIN_C_SCLK]	= &tdmin_c_sclk.hw,
+		[AUD_CLKID_TDMIN_LB_SCLK]	= &tdmin_lb_sclk.hw,
+		[AUD_CLKID_TDMOUT_A_SCLK]	= &tdmout_a_sclk.hw,
+		[AUD_CLKID_TDMOUT_B_SCLK]	= &tdmout_b_sclk.hw,
+		[AUD_CLKID_TDMOUT_C_SCLK]	= &tdmout_c_sclk.hw,
+		[AUD_CLKID_TDMIN_A_LRCLK]	= &tdmin_a_lrclk.hw,
+		[AUD_CLKID_TDMIN_B_LRCLK]	= &tdmin_b_lrclk.hw,
+		[AUD_CLKID_TDMIN_C_LRCLK]	= &tdmin_c_lrclk.hw,
+		[AUD_CLKID_TDMIN_LB_LRCLK]	= &tdmin_lb_lrclk.hw,
+		[AUD_CLKID_TDMOUT_A_LRCLK]	= &tdmout_a_lrclk.hw,
+		[AUD_CLKID_TDMOUT_B_LRCLK]	= &tdmout_b_lrclk.hw,
+		[AUD_CLKID_TDMOUT_C_LRCLK]	= &tdmout_c_lrclk.hw,
+		[AUD_CLKID_TDM_MCLK_PAD0]	= &g12a_tdm_mclk_pad_0.hw,
+		[AUD_CLKID_TDM_MCLK_PAD1]	= &g12a_tdm_mclk_pad_1.hw,
+		[AUD_CLKID_TDM_LRCLK_PAD0]	= &g12a_tdm_lrclk_pad_0.hw,
+		[AUD_CLKID_TDM_LRCLK_PAD1]	= &g12a_tdm_lrclk_pad_1.hw,
+		[AUD_CLKID_TDM_LRCLK_PAD2]	= &g12a_tdm_lrclk_pad_2.hw,
+		[AUD_CLKID_TDM_SCLK_PAD0]	= &g12a_tdm_sclk_pad_0.hw,
+		[AUD_CLKID_TDM_SCLK_PAD1]	= &g12a_tdm_sclk_pad_1.hw,
+		[AUD_CLKID_TDM_SCLK_PAD2]	= &g12a_tdm_sclk_pad_2.hw,
 		[NR_CLKS] = NULL,
 	},
 	.num = NR_CLKS,
@@ -750,139 +847,139 @@ static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
  * feel the need to have separate AXG/G12A regmap tables.
  */
 static struct clk_regmap *const aud_clk_regmaps[] = {
-	&aud_ddr_arb,
-	&aud_pdm,
-	&aud_tdmin_a,
-	&aud_tdmin_b,
-	&aud_tdmin_c,
-	&aud_tdmin_lb,
-	&aud_tdmout_a,
-	&aud_tdmout_b,
-	&aud_tdmout_c,
-	&aud_frddr_a,
-	&aud_frddr_b,
-	&aud_frddr_c,
-	&aud_toddr_a,
-	&aud_toddr_b,
-	&aud_toddr_c,
-	&aud_loopback,
-	&aud_spdifin,
-	&aud_spdifout,
-	&aud_resample,
-	&aud_power_detect,
-	&aud_spdifout_b,
-	&aud_mst_a_mclk_sel,
-	&aud_mst_b_mclk_sel,
-	&aud_mst_c_mclk_sel,
-	&aud_mst_d_mclk_sel,
-	&aud_mst_e_mclk_sel,
-	&aud_mst_f_mclk_sel,
-	&aud_mst_a_mclk_div,
-	&aud_mst_b_mclk_div,
-	&aud_mst_c_mclk_div,
-	&aud_mst_d_mclk_div,
-	&aud_mst_e_mclk_div,
-	&aud_mst_f_mclk_div,
-	&aud_mst_a_mclk,
-	&aud_mst_b_mclk,
-	&aud_mst_c_mclk,
-	&aud_mst_d_mclk,
-	&aud_mst_e_mclk,
-	&aud_mst_f_mclk,
-	&aud_spdifout_clk_sel,
-	&aud_spdifout_clk_div,
-	&aud_spdifout_clk,
-	&aud_spdifin_clk_sel,
-	&aud_spdifin_clk_div,
-	&aud_spdifin_clk,
-	&aud_pdm_dclk_sel,
-	&aud_pdm_dclk_div,
-	&aud_pdm_dclk,
-	&aud_pdm_sysclk_sel,
-	&aud_pdm_sysclk_div,
-	&aud_pdm_sysclk,
-	&aud_mst_a_sclk_pre_en,
-	&aud_mst_b_sclk_pre_en,
-	&aud_mst_c_sclk_pre_en,
-	&aud_mst_d_sclk_pre_en,
-	&aud_mst_e_sclk_pre_en,
-	&aud_mst_f_sclk_pre_en,
-	&aud_mst_a_sclk_div,
-	&aud_mst_b_sclk_div,
-	&aud_mst_c_sclk_div,
-	&aud_mst_d_sclk_div,
-	&aud_mst_e_sclk_div,
-	&aud_mst_f_sclk_div,
-	&aud_mst_a_sclk_post_en,
-	&aud_mst_b_sclk_post_en,
-	&aud_mst_c_sclk_post_en,
-	&aud_mst_d_sclk_post_en,
-	&aud_mst_e_sclk_post_en,
-	&aud_mst_f_sclk_post_en,
-	&aud_mst_a_sclk,
-	&aud_mst_b_sclk,
-	&aud_mst_c_sclk,
-	&aud_mst_d_sclk,
-	&aud_mst_e_sclk,
-	&aud_mst_f_sclk,
-	&aud_mst_a_lrclk_div,
-	&aud_mst_b_lrclk_div,
-	&aud_mst_c_lrclk_div,
-	&aud_mst_d_lrclk_div,
-	&aud_mst_e_lrclk_div,
-	&aud_mst_f_lrclk_div,
-	&aud_mst_a_lrclk,
-	&aud_mst_b_lrclk,
-	&aud_mst_c_lrclk,
-	&aud_mst_d_lrclk,
-	&aud_mst_e_lrclk,
-	&aud_mst_f_lrclk,
-	&aud_tdmin_a_sclk_sel,
-	&aud_tdmin_b_sclk_sel,
-	&aud_tdmin_c_sclk_sel,
-	&aud_tdmin_lb_sclk_sel,
-	&aud_tdmout_a_sclk_sel,
-	&aud_tdmout_b_sclk_sel,
-	&aud_tdmout_c_sclk_sel,
-	&aud_tdmin_a_sclk_pre_en,
-	&aud_tdmin_b_sclk_pre_en,
-	&aud_tdmin_c_sclk_pre_en,
-	&aud_tdmin_lb_sclk_pre_en,
-	&aud_tdmout_a_sclk_pre_en,
-	&aud_tdmout_b_sclk_pre_en,
-	&aud_tdmout_c_sclk_pre_en,
-	&aud_tdmin_a_sclk_post_en,
-	&aud_tdmin_b_sclk_post_en,
-	&aud_tdmin_c_sclk_post_en,
-	&aud_tdmin_lb_sclk_post_en,
-	&aud_tdmout_a_sclk_post_en,
-	&aud_tdmout_b_sclk_post_en,
-	&aud_tdmout_c_sclk_post_en,
-	&aud_tdmin_a_sclk,
-	&aud_tdmin_b_sclk,
-	&aud_tdmin_c_sclk,
-	&aud_tdmin_lb_sclk,
-	&aud_tdmout_a_sclk,
-	&aud_tdmout_b_sclk,
-	&aud_tdmout_c_sclk,
-	&aud_tdmin_a_lrclk,
-	&aud_tdmin_b_lrclk,
-	&aud_tdmin_c_lrclk,
-	&aud_tdmin_lb_lrclk,
-	&aud_tdmout_a_lrclk,
-	&aud_tdmout_b_lrclk,
-	&aud_tdmout_c_lrclk,
-	&aud_spdifout_b_clk_sel,
-	&aud_spdifout_b_clk_div,
-	&aud_spdifout_b_clk,
-	&aud_tdm_mclk_pad_0,
-	&aud_tdm_mclk_pad_1,
-	&aud_tdm_lrclk_pad_0,
-	&aud_tdm_lrclk_pad_1,
-	&aud_tdm_lrclk_pad_2,
-	&aud_tdm_sclk_pad_0,
-	&aud_tdm_sclk_pad_1,
-	&aud_tdm_sclk_pad_2,
+	&ddr_arb,
+	&pdm,
+	&tdmin_a,
+	&tdmin_b,
+	&tdmin_c,
+	&tdmin_lb,
+	&tdmout_a,
+	&tdmout_b,
+	&tdmout_c,
+	&frddr_a,
+	&frddr_b,
+	&frddr_c,
+	&toddr_a,
+	&toddr_b,
+	&toddr_c,
+	&loopback,
+	&spdifin,
+	&spdifout,
+	&resample,
+	&power_detect,
+	&spdifout_b,
+	&mst_a_mclk_sel,
+	&mst_b_mclk_sel,
+	&mst_c_mclk_sel,
+	&mst_d_mclk_sel,
+	&mst_e_mclk_sel,
+	&mst_f_mclk_sel,
+	&mst_a_mclk_div,
+	&mst_b_mclk_div,
+	&mst_c_mclk_div,
+	&mst_d_mclk_div,
+	&mst_e_mclk_div,
+	&mst_f_mclk_div,
+	&mst_a_mclk,
+	&mst_b_mclk,
+	&mst_c_mclk,
+	&mst_d_mclk,
+	&mst_e_mclk,
+	&mst_f_mclk,
+	&spdifout_clk_sel,
+	&spdifout_clk_div,
+	&spdifout_clk,
+	&spdifin_clk_sel,
+	&spdifin_clk_div,
+	&spdifin_clk,
+	&pdm_dclk_sel,
+	&pdm_dclk_div,
+	&pdm_dclk,
+	&pdm_sysclk_sel,
+	&pdm_sysclk_div,
+	&pdm_sysclk,
+	&mst_a_sclk_pre_en,
+	&mst_b_sclk_pre_en,
+	&mst_c_sclk_pre_en,
+	&mst_d_sclk_pre_en,
+	&mst_e_sclk_pre_en,
+	&mst_f_sclk_pre_en,
+	&mst_a_sclk_div,
+	&mst_b_sclk_div,
+	&mst_c_sclk_div,
+	&mst_d_sclk_div,
+	&mst_e_sclk_div,
+	&mst_f_sclk_div,
+	&mst_a_sclk_post_en,
+	&mst_b_sclk_post_en,
+	&mst_c_sclk_post_en,
+	&mst_d_sclk_post_en,
+	&mst_e_sclk_post_en,
+	&mst_f_sclk_post_en,
+	&mst_a_sclk,
+	&mst_b_sclk,
+	&mst_c_sclk,
+	&mst_d_sclk,
+	&mst_e_sclk,
+	&mst_f_sclk,
+	&mst_a_lrclk_div,
+	&mst_b_lrclk_div,
+	&mst_c_lrclk_div,
+	&mst_d_lrclk_div,
+	&mst_e_lrclk_div,
+	&mst_f_lrclk_div,
+	&mst_a_lrclk,
+	&mst_b_lrclk,
+	&mst_c_lrclk,
+	&mst_d_lrclk,
+	&mst_e_lrclk,
+	&mst_f_lrclk,
+	&tdmin_a_sclk_sel,
+	&tdmin_b_sclk_sel,
+	&tdmin_c_sclk_sel,
+	&tdmin_lb_sclk_sel,
+	&tdmout_a_sclk_sel,
+	&tdmout_b_sclk_sel,
+	&tdmout_c_sclk_sel,
+	&tdmin_a_sclk_pre_en,
+	&tdmin_b_sclk_pre_en,
+	&tdmin_c_sclk_pre_en,
+	&tdmin_lb_sclk_pre_en,
+	&tdmout_a_sclk_pre_en,
+	&tdmout_b_sclk_pre_en,
+	&tdmout_c_sclk_pre_en,
+	&tdmin_a_sclk_post_en,
+	&tdmin_b_sclk_post_en,
+	&tdmin_c_sclk_post_en,
+	&tdmin_lb_sclk_post_en,
+	&tdmout_a_sclk_post_en,
+	&tdmout_b_sclk_post_en,
+	&tdmout_c_sclk_post_en,
+	&tdmin_a_sclk,
+	&tdmin_b_sclk,
+	&tdmin_c_sclk,
+	&tdmin_lb_sclk,
+	&tdmout_a_sclk,
+	&tdmout_b_sclk,
+	&tdmout_c_sclk,
+	&tdmin_a_lrclk,
+	&tdmin_b_lrclk,
+	&tdmin_c_lrclk,
+	&tdmin_lb_lrclk,
+	&tdmout_a_lrclk,
+	&tdmout_b_lrclk,
+	&tdmout_c_lrclk,
+	&spdifout_b_clk_sel,
+	&spdifout_b_clk_div,
+	&spdifout_b_clk,
+	&g12a_tdm_mclk_pad_0,
+	&g12a_tdm_mclk_pad_1,
+	&g12a_tdm_lrclk_pad_0,
+	&g12a_tdm_lrclk_pad_1,
+	&g12a_tdm_lrclk_pad_2,
+	&g12a_tdm_sclk_pad_0,
+	&g12a_tdm_sclk_pad_1,
+	&g12a_tdm_sclk_pad_2,
 };
 
 static int devm_clk_get_enable(struct device *dev, char *id)
-- 
2.21.0


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH 6/7] clk: meson: axg-audio: provide clk top signal name
  2019-09-24 15:33 [PATCH 0/7] clk: meson: axg-audio: add sm1 support Jerome Brunet
                   ` (4 preceding siblings ...)
  2019-09-24 15:33 ` [PATCH 5/7] clk: meson: axg-audio: prepare sm1 addition Jerome Brunet
@ 2019-09-24 15:33 ` Jerome Brunet
  2019-09-27  9:14   ` Neil Armstrong
  2019-09-24 15:33 ` [PATCH 7/7] clk: meson: axg_audio: add sm1 support Jerome Brunet
  6 siblings, 1 reply; 19+ messages in thread
From: Jerome Brunet @ 2019-09-24 15:33 UTC (permalink / raw)
  To: Neil Armstrong
  Cc: Jerome Brunet, Kevin Hilman, linux-amlogic, linux-clk, linux-kernel

The peripheral clock on the sm1 goes through some muxes
and dividers before reaching the audio gates. To model that,
without repeating our self too much, the "top" clock signal
is introduced and will serve as a the parent of the gates.

On the axg and g12a, the top clock is just a pass-through to
the audio peripheral clock provided by the main controller.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/axg-audio.c | 19 ++++++++++++++++---
 drivers/clk/meson/axg-audio.h |  3 ++-
 2 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index ce8836776d1c..a8ccdbaecae2 100644
--- a/drivers/clk/meson/axg-audio.c
+++ b/drivers/clk/meson/axg-audio.c
@@ -74,9 +74,7 @@
 	.hw.init = &(struct clk_init_data) {				\
 		.name = "aud_"#_name,					\
 		.ops = &clk_regmap_gate_ops,				\
-		.parent_data = &(const struct clk_parent_data) {	\
-			.fw_name = "pclk",				\
-		},							\
+		.parent_names = (const char *[]){ "aud_top" },		\
 		.num_parents = 1,					\
 	},								\
 }
@@ -504,6 +502,19 @@ static struct clk_regmap tdmout_c_lrclk =
 	AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
 
 /* AXG/G12A Clocks */
+
+static struct clk_hw axg_aud_top = {
+	.init = &(struct clk_init_data) {
+		/* Provide aud_top signal name on axg and g12a */
+		.name = "aud_top",
+		.ops = &(const struct clk_ops) {},
+		.parent_data = &(const struct clk_parent_data) {
+			.fw_name = "pclk",
+		},
+		.num_parents = 1,
+	},
+};
+
 static struct clk_regmap mst_a_mclk_sel =
 	AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
 static struct clk_regmap mst_b_mclk_sel =
@@ -691,6 +702,7 @@ static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
 		[AUD_CLKID_TDMOUT_A_LRCLK]	= &tdmout_a_lrclk.hw,
 		[AUD_CLKID_TDMOUT_B_LRCLK]	= &tdmout_b_lrclk.hw,
 		[AUD_CLKID_TDMOUT_C_LRCLK]	= &tdmout_c_lrclk.hw,
+		[AUD_CLKID_TOP]			= &axg_aud_top,
 		[NR_CLKS] = NULL,
 	},
 	.num = NR_CLKS,
@@ -835,6 +847,7 @@ static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
 		[AUD_CLKID_TDM_SCLK_PAD0]	= &g12a_tdm_sclk_pad_0.hw,
 		[AUD_CLKID_TDM_SCLK_PAD1]	= &g12a_tdm_sclk_pad_1.hw,
 		[AUD_CLKID_TDM_SCLK_PAD2]	= &g12a_tdm_sclk_pad_2.hw,
+		[AUD_CLKID_TOP]			= &axg_aud_top,
 		[NR_CLKS] = NULL,
 	},
 	.num = NR_CLKS,
diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h
index c00e28b2e1a9..a4956837f597 100644
--- a/drivers/clk/meson/axg-audio.h
+++ b/drivers/clk/meson/axg-audio.h
@@ -116,9 +116,10 @@
 #define AUD_CLKID_SPDIFOUT_B_CLK_SEL	153
 #define AUD_CLKID_SPDIFOUT_B_CLK_DIV	154
 
+
 /* include the CLKIDs which are part of the DT bindings */
 #include <dt-bindings/clock/axg-audio-clkc.h>
 
-#define NR_CLKS	163
+#define NR_CLKS	164
 
 #endif /*__AXG_AUDIO_CLKC_H */
-- 
2.21.0


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH 7/7] clk: meson: axg_audio: add sm1 support
  2019-09-24 15:33 [PATCH 0/7] clk: meson: axg-audio: add sm1 support Jerome Brunet
                   ` (5 preceding siblings ...)
  2019-09-24 15:33 ` [PATCH 6/7] clk: meson: axg-audio: provide clk top signal name Jerome Brunet
@ 2019-09-24 15:33 ` Jerome Brunet
  2019-09-27  9:36   ` Neil Armstrong
  6 siblings, 1 reply; 19+ messages in thread
From: Jerome Brunet @ 2019-09-24 15:33 UTC (permalink / raw)
  To: Neil Armstrong
  Cc: Jerome Brunet, Kevin Hilman, linux-amlogic, linux-clk, linux-kernel

Add sm1 support the axg audio clock controllers. This new version is
indeed derived from the previous generation, as always, adding a few
new clocks to the mix.

The number of gates now exceeds 32 and do not fit in a single register.
Unfortunately, designers chose to introduce the new gate register
immediately after the original one, at the beginning of the register
space, shifting all the master clock register offsets.

The sm1 also introduce a few mux and divider on the top clock path,
possibly to lower the peripheral clocks of the audio blocks if
necessary.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/axg-audio.c | 583 ++++++++++++++++++++++++++++++++--
 drivers/clk/meson/axg-audio.h |  22 +-
 2 files changed, 574 insertions(+), 31 deletions(-)

diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index a8ccdbaecae2..88046a5e26b7 100644
--- a/drivers/clk/meson/axg-audio.c
+++ b/drivers/clk/meson/axg-audio.c
@@ -66,9 +66,9 @@
 	},								\
 }
 
-#define AUD_PCLK_GATE(_name, _bit) {					\
+#define AUD_PCLK_GATE(_name, _reg, _bit) {				\
 	.data = &(struct clk_regmap_gate_data){				\
-		.offset = (AUDIO_CLK_GATE_EN),				\
+		.offset = (_reg),					\
 		.bit_idx = (_bit),					\
 	},								\
 	.hw.init = &(struct clk_init_data) {				\
@@ -290,30 +290,50 @@ static const struct clk_parent_data lrclk_pad_ctrl_parent_data[] = {
 };
 
 #define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents)		\
-	AUD_MUX(tdm_##_name, _reg, 0x7, _shift, 0, _parents,	\
+	AUD_MUX(_name, _reg, 0x7, _shift, 0, _parents,		\
 		CLK_SET_RATE_NO_REPARENT)
 
 /* Common Clocks */
-static struct clk_regmap ddr_arb	= AUD_PCLK_GATE(ddr_arb, 0);
-static struct clk_regmap pdm		= AUD_PCLK_GATE(pdm, 1);
-static struct clk_regmap tdmin_a	= AUD_PCLK_GATE(tdmin_a, 2);
-static struct clk_regmap tdmin_b	= AUD_PCLK_GATE(tdmin_b, 3);
-static struct clk_regmap tdmin_c	= AUD_PCLK_GATE(tdmin_c, 4);
-static struct clk_regmap tdmin_lb	= AUD_PCLK_GATE(tdmin_lb, 5);
-static struct clk_regmap tdmout_a	= AUD_PCLK_GATE(tdmout_a, 6);
-static struct clk_regmap tdmout_b	= AUD_PCLK_GATE(tdmout_b, 7);
-static struct clk_regmap tdmout_c	= AUD_PCLK_GATE(tdmout_c, 8);
-static struct clk_regmap frddr_a	= AUD_PCLK_GATE(frddr_a, 9);
-static struct clk_regmap frddr_b	= AUD_PCLK_GATE(frddr_b, 10);
-static struct clk_regmap frddr_c	= AUD_PCLK_GATE(frddr_c, 11);
-static struct clk_regmap toddr_a	= AUD_PCLK_GATE(toddr_a, 12);
-static struct clk_regmap toddr_b	= AUD_PCLK_GATE(toddr_b, 13);
-static struct clk_regmap toddr_c	= AUD_PCLK_GATE(toddr_c, 14);
-static struct clk_regmap loopback	= AUD_PCLK_GATE(loopback, 15);
-static struct clk_regmap spdifin	= AUD_PCLK_GATE(spdifin, 16);
-static struct clk_regmap spdifout	= AUD_PCLK_GATE(spdifout, 17);
-static struct clk_regmap resample	= AUD_PCLK_GATE(resample, 18);
-static struct clk_regmap power_detect	= AUD_PCLK_GATE(power_detect, 19);
+static struct clk_regmap ddr_arb =
+	AUD_PCLK_GATE(ddr_arb, AUDIO_CLK_GATE_EN, 0);
+static struct clk_regmap pdm =
+	AUD_PCLK_GATE(pdm, AUDIO_CLK_GATE_EN, 1);
+static struct clk_regmap tdmin_a =
+	AUD_PCLK_GATE(tdmin_a, AUDIO_CLK_GATE_EN, 2);
+static struct clk_regmap tdmin_b =
+	AUD_PCLK_GATE(tdmin_b, AUDIO_CLK_GATE_EN, 3);
+static struct clk_regmap tdmin_c =
+	AUD_PCLK_GATE(tdmin_c, AUDIO_CLK_GATE_EN, 4);
+static struct clk_regmap tdmin_lb =
+	AUD_PCLK_GATE(tdmin_lb, AUDIO_CLK_GATE_EN, 5);
+static struct clk_regmap tdmout_a =
+	AUD_PCLK_GATE(tdmout_a, AUDIO_CLK_GATE_EN, 6);
+static struct clk_regmap tdmout_b =
+	AUD_PCLK_GATE(tdmout_b, AUDIO_CLK_GATE_EN, 7);
+static struct clk_regmap tdmout_c =
+	AUD_PCLK_GATE(tdmout_c, AUDIO_CLK_GATE_EN, 8);
+static struct clk_regmap frddr_a =
+	AUD_PCLK_GATE(frddr_a, AUDIO_CLK_GATE_EN, 9);
+static struct clk_regmap frddr_b =
+	AUD_PCLK_GATE(frddr_b, AUDIO_CLK_GATE_EN, 10);
+static struct clk_regmap frddr_c =
+	AUD_PCLK_GATE(frddr_c, AUDIO_CLK_GATE_EN, 11);
+static struct clk_regmap toddr_a =
+	AUD_PCLK_GATE(toddr_a, AUDIO_CLK_GATE_EN, 12);
+static struct clk_regmap toddr_b =
+	AUD_PCLK_GATE(toddr_b, AUDIO_CLK_GATE_EN, 13);
+static struct clk_regmap toddr_c =
+	AUD_PCLK_GATE(toddr_c, AUDIO_CLK_GATE_EN, 14);
+static struct clk_regmap loopback =
+	AUD_PCLK_GATE(loopback, AUDIO_CLK_GATE_EN, 15);
+static struct clk_regmap spdifin =
+	AUD_PCLK_GATE(spdifin, AUDIO_CLK_GATE_EN, 16);
+static struct clk_regmap spdifout =
+	AUD_PCLK_GATE(spdifout, AUDIO_CLK_GATE_EN, 17);
+static struct clk_regmap resample =
+	AUD_PCLK_GATE(resample, AUDIO_CLK_GATE_EN, 18);
+static struct clk_regmap power_detect =
+	AUD_PCLK_GATE(power_detect, AUDIO_CLK_GATE_EN, 19);
 
 static struct clk_regmap spdifout_clk_sel =
 	AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
@@ -502,7 +522,6 @@ static struct clk_regmap tdmout_c_lrclk =
 	AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
 
 /* AXG/G12A Clocks */
-
 static struct clk_hw axg_aud_top = {
 	.init = &(struct clk_init_data) {
 		/* Provide aud_top signal name on axg and g12a */
@@ -573,7 +592,185 @@ static struct clk_regmap g12a_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
 	sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data);
 
 /* G12a/SM1 clocks */
-static struct clk_regmap spdifout_b = AUD_PCLK_GATE(spdifout_b,   21);
+static struct clk_regmap toram =
+	AUD_PCLK_GATE(toram, AUDIO_CLK_GATE_EN, 20);
+static struct clk_regmap spdifout_b =
+	AUD_PCLK_GATE(spdifout_b, AUDIO_CLK_GATE_EN, 21);
+static struct clk_regmap eqdrc =
+	AUD_PCLK_GATE(eqdrc, AUDIO_CLK_GATE_EN, 22);
+
+/* SM1 Clocks */
+static struct clk_regmap sm1_clk81_en = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = AUDIO_CLK81_EN,
+		.bit_idx = 31,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "aud_clk81_en",
+		.ops = &(const struct clk_ops) {},
+		.parent_data = &(const struct clk_parent_data) {
+			.fw_name = "pclk",
+		},
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap sm1_sysclk_a_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = AUDIO_CLK81_CTRL,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "aud_sysclk_a_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&sm1_clk81_en.hw,
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap sm1_sysclk_a_en = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = AUDIO_CLK81_CTRL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "aud_sysclk_a_en",
+		.ops = &(const struct clk_ops) {},
+		.parent_hws = (const struct clk_hw *[]) {
+			&sm1_sysclk_a_div.hw,
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap sm1_sysclk_b_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = AUDIO_CLK81_CTRL,
+		.shift = 16,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "aud_sysclk_b_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&sm1_clk81_en.hw,
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap sm1_sysclk_b_en = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = AUDIO_CLK81_CTRL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "aud_sysclk_b_en",
+		.ops = &(const struct clk_ops) {},
+		.parent_hws = (const struct clk_hw *[]) {
+			&sm1_sysclk_b_div.hw,
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct clk_hw *sm1_aud_top_parents[] = {
+	&sm1_sysclk_a_en.hw,
+	&sm1_sysclk_b_en.hw,
+};
+
+static struct clk_regmap sm1_aud_top = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = AUDIO_CLK81_CTRL,
+		.mask = 0x1,
+		.shift = 31,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "aud_top",
+		.ops = &clk_regmap_mux_ops,
+		.parent_hws = sm1_aud_top_parents,
+		.num_parents = ARRAY_SIZE(sm1_aud_top_parents),
+		.flags = CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
+static struct clk_regmap resample_b =
+	AUD_PCLK_GATE(resample_b, AUDIO_CLK_GATE_EN, 26);
+static struct clk_regmap tovad =
+	AUD_PCLK_GATE(tovad, AUDIO_CLK_GATE_EN, 27);
+static struct clk_regmap locker =
+	AUD_PCLK_GATE(locker, AUDIO_CLK_GATE_EN, 28);
+static struct clk_regmap spdifin_lb =
+	AUD_PCLK_GATE(spdifin_lb, AUDIO_CLK_GATE_EN, 29);
+static struct clk_regmap frddr_d =
+	AUD_PCLK_GATE(frddr_d, AUDIO_CLK_GATE_EN1, 0);
+static struct clk_regmap toddr_d =
+	AUD_PCLK_GATE(toddr_d, AUDIO_CLK_GATE_EN1, 1);
+static struct clk_regmap loopback_b =
+	AUD_PCLK_GATE(loopback_b, AUDIO_CLK_GATE_EN1, 2);
+
+static struct clk_regmap sm1_mst_a_mclk_sel =
+	AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
+static struct clk_regmap sm1_mst_b_mclk_sel =
+	AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
+static struct clk_regmap sm1_mst_c_mclk_sel =
+	AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
+static struct clk_regmap sm1_mst_d_mclk_sel =
+	AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
+static struct clk_regmap sm1_mst_e_mclk_sel =
+	AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
+static struct clk_regmap sm1_mst_f_mclk_sel =
+	AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
+
+static struct clk_regmap sm1_mst_a_mclk_div =
+	AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
+static struct clk_regmap sm1_mst_b_mclk_div =
+	AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
+static struct clk_regmap sm1_mst_c_mclk_div =
+	AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
+static struct clk_regmap sm1_mst_d_mclk_div =
+	AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
+static struct clk_regmap sm1_mst_e_mclk_div =
+	AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
+static struct clk_regmap sm1_mst_f_mclk_div =
+	AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
+
+static struct clk_regmap sm1_mst_a_mclk =
+	AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
+static struct clk_regmap sm1_mst_b_mclk =
+	AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
+static struct clk_regmap sm1_mst_c_mclk =
+	AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
+static struct clk_regmap sm1_mst_d_mclk =
+	AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
+static struct clk_regmap sm1_mst_e_mclk =
+	AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
+static struct clk_regmap sm1_mst_f_mclk =
+	AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
+
+static struct clk_regmap sm1_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL(
+	tdm_mclk_pad_0, AUDIO_SM1_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data);
+static struct clk_regmap sm1_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL(
+	tdm_mclk_pad_1, AUDIO_SM1_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data);
+static struct clk_regmap sm1_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL(
+	tdm_lrclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data);
+static struct clk_regmap sm1_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL(
+	tdm_lrclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data);
+static struct clk_regmap sm1_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL(
+	tdm_lrclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data);
+static struct clk_regmap sm1_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL(
+	tdm_sclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data);
+static struct clk_regmap sm1_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL(
+	tdm_sclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data);
+static struct clk_regmap sm1_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
+	tdm_sclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data);
 
 /*
  * Array of all clocks provided by this provider
@@ -853,13 +1050,172 @@ static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
 	.num = NR_CLKS,
 };
 
+/*
+ * Array of all SM1 clocks provided by this provider
+ * The input clocks of the controller will be populated at runtime
+ */
+static struct clk_hw_onecell_data sm1_audio_hw_onecell_data = {
+	.hws = {
+		[AUD_CLKID_DDR_ARB]		= &ddr_arb.hw,
+		[AUD_CLKID_PDM]			= &pdm.hw,
+		[AUD_CLKID_TDMIN_A]		= &tdmin_a.hw,
+		[AUD_CLKID_TDMIN_B]		= &tdmin_b.hw,
+		[AUD_CLKID_TDMIN_C]		= &tdmin_c.hw,
+		[AUD_CLKID_TDMIN_LB]		= &tdmin_lb.hw,
+		[AUD_CLKID_TDMOUT_A]		= &tdmout_a.hw,
+		[AUD_CLKID_TDMOUT_B]		= &tdmout_b.hw,
+		[AUD_CLKID_TDMOUT_C]		= &tdmout_c.hw,
+		[AUD_CLKID_FRDDR_A]		= &frddr_a.hw,
+		[AUD_CLKID_FRDDR_B]		= &frddr_b.hw,
+		[AUD_CLKID_FRDDR_C]		= &frddr_c.hw,
+		[AUD_CLKID_TODDR_A]		= &toddr_a.hw,
+		[AUD_CLKID_TODDR_B]		= &toddr_b.hw,
+		[AUD_CLKID_TODDR_C]		= &toddr_c.hw,
+		[AUD_CLKID_LOOPBACK]		= &loopback.hw,
+		[AUD_CLKID_SPDIFIN]		= &spdifin.hw,
+		[AUD_CLKID_SPDIFOUT]		= &spdifout.hw,
+		[AUD_CLKID_RESAMPLE]		= &resample.hw,
+		[AUD_CLKID_SPDIFOUT_B]		= &spdifout_b.hw,
+		[AUD_CLKID_MST_A_MCLK_SEL]	= &sm1_mst_a_mclk_sel.hw,
+		[AUD_CLKID_MST_B_MCLK_SEL]	= &sm1_mst_b_mclk_sel.hw,
+		[AUD_CLKID_MST_C_MCLK_SEL]	= &sm1_mst_c_mclk_sel.hw,
+		[AUD_CLKID_MST_D_MCLK_SEL]	= &sm1_mst_d_mclk_sel.hw,
+		[AUD_CLKID_MST_E_MCLK_SEL]	= &sm1_mst_e_mclk_sel.hw,
+		[AUD_CLKID_MST_F_MCLK_SEL]	= &sm1_mst_f_mclk_sel.hw,
+		[AUD_CLKID_MST_A_MCLK_DIV]	= &sm1_mst_a_mclk_div.hw,
+		[AUD_CLKID_MST_B_MCLK_DIV]	= &sm1_mst_b_mclk_div.hw,
+		[AUD_CLKID_MST_C_MCLK_DIV]	= &sm1_mst_c_mclk_div.hw,
+		[AUD_CLKID_MST_D_MCLK_DIV]	= &sm1_mst_d_mclk_div.hw,
+		[AUD_CLKID_MST_E_MCLK_DIV]	= &sm1_mst_e_mclk_div.hw,
+		[AUD_CLKID_MST_F_MCLK_DIV]	= &sm1_mst_f_mclk_div.hw,
+		[AUD_CLKID_MST_A_MCLK]		= &sm1_mst_a_mclk.hw,
+		[AUD_CLKID_MST_B_MCLK]		= &sm1_mst_b_mclk.hw,
+		[AUD_CLKID_MST_C_MCLK]		= &sm1_mst_c_mclk.hw,
+		[AUD_CLKID_MST_D_MCLK]		= &sm1_mst_d_mclk.hw,
+		[AUD_CLKID_MST_E_MCLK]		= &sm1_mst_e_mclk.hw,
+		[AUD_CLKID_MST_F_MCLK]		= &sm1_mst_f_mclk.hw,
+		[AUD_CLKID_SPDIFOUT_CLK_SEL]	= &spdifout_clk_sel.hw,
+		[AUD_CLKID_SPDIFOUT_CLK_DIV]	= &spdifout_clk_div.hw,
+		[AUD_CLKID_SPDIFOUT_CLK]	= &spdifout_clk.hw,
+		[AUD_CLKID_SPDIFOUT_B_CLK_SEL]	= &spdifout_b_clk_sel.hw,
+		[AUD_CLKID_SPDIFOUT_B_CLK_DIV]	= &spdifout_b_clk_div.hw,
+		[AUD_CLKID_SPDIFOUT_B_CLK]	= &spdifout_b_clk.hw,
+		[AUD_CLKID_SPDIFIN_CLK_SEL]	= &spdifin_clk_sel.hw,
+		[AUD_CLKID_SPDIFIN_CLK_DIV]	= &spdifin_clk_div.hw,
+		[AUD_CLKID_SPDIFIN_CLK]		= &spdifin_clk.hw,
+		[AUD_CLKID_PDM_DCLK_SEL]	= &pdm_dclk_sel.hw,
+		[AUD_CLKID_PDM_DCLK_DIV]	= &pdm_dclk_div.hw,
+		[AUD_CLKID_PDM_DCLK]		= &pdm_dclk.hw,
+		[AUD_CLKID_PDM_SYSCLK_SEL]	= &pdm_sysclk_sel.hw,
+		[AUD_CLKID_PDM_SYSCLK_DIV]	= &pdm_sysclk_div.hw,
+		[AUD_CLKID_PDM_SYSCLK]		= &pdm_sysclk.hw,
+		[AUD_CLKID_MST_A_SCLK_PRE_EN]	= &mst_a_sclk_pre_en.hw,
+		[AUD_CLKID_MST_B_SCLK_PRE_EN]	= &mst_b_sclk_pre_en.hw,
+		[AUD_CLKID_MST_C_SCLK_PRE_EN]	= &mst_c_sclk_pre_en.hw,
+		[AUD_CLKID_MST_D_SCLK_PRE_EN]	= &mst_d_sclk_pre_en.hw,
+		[AUD_CLKID_MST_E_SCLK_PRE_EN]	= &mst_e_sclk_pre_en.hw,
+		[AUD_CLKID_MST_F_SCLK_PRE_EN]	= &mst_f_sclk_pre_en.hw,
+		[AUD_CLKID_MST_A_SCLK_DIV]	= &mst_a_sclk_div.hw,
+		[AUD_CLKID_MST_B_SCLK_DIV]	= &mst_b_sclk_div.hw,
+		[AUD_CLKID_MST_C_SCLK_DIV]	= &mst_c_sclk_div.hw,
+		[AUD_CLKID_MST_D_SCLK_DIV]	= &mst_d_sclk_div.hw,
+		[AUD_CLKID_MST_E_SCLK_DIV]	= &mst_e_sclk_div.hw,
+		[AUD_CLKID_MST_F_SCLK_DIV]	= &mst_f_sclk_div.hw,
+		[AUD_CLKID_MST_A_SCLK_POST_EN]	= &mst_a_sclk_post_en.hw,
+		[AUD_CLKID_MST_B_SCLK_POST_EN]	= &mst_b_sclk_post_en.hw,
+		[AUD_CLKID_MST_C_SCLK_POST_EN]	= &mst_c_sclk_post_en.hw,
+		[AUD_CLKID_MST_D_SCLK_POST_EN]	= &mst_d_sclk_post_en.hw,
+		[AUD_CLKID_MST_E_SCLK_POST_EN]	= &mst_e_sclk_post_en.hw,
+		[AUD_CLKID_MST_F_SCLK_POST_EN]	= &mst_f_sclk_post_en.hw,
+		[AUD_CLKID_MST_A_SCLK]		= &mst_a_sclk.hw,
+		[AUD_CLKID_MST_B_SCLK]		= &mst_b_sclk.hw,
+		[AUD_CLKID_MST_C_SCLK]		= &mst_c_sclk.hw,
+		[AUD_CLKID_MST_D_SCLK]		= &mst_d_sclk.hw,
+		[AUD_CLKID_MST_E_SCLK]		= &mst_e_sclk.hw,
+		[AUD_CLKID_MST_F_SCLK]		= &mst_f_sclk.hw,
+		[AUD_CLKID_MST_A_LRCLK_DIV]	= &mst_a_lrclk_div.hw,
+		[AUD_CLKID_MST_B_LRCLK_DIV]	= &mst_b_lrclk_div.hw,
+		[AUD_CLKID_MST_C_LRCLK_DIV]	= &mst_c_lrclk_div.hw,
+		[AUD_CLKID_MST_D_LRCLK_DIV]	= &mst_d_lrclk_div.hw,
+		[AUD_CLKID_MST_E_LRCLK_DIV]	= &mst_e_lrclk_div.hw,
+		[AUD_CLKID_MST_F_LRCLK_DIV]	= &mst_f_lrclk_div.hw,
+		[AUD_CLKID_MST_A_LRCLK]		= &mst_a_lrclk.hw,
+		[AUD_CLKID_MST_B_LRCLK]		= &mst_b_lrclk.hw,
+		[AUD_CLKID_MST_C_LRCLK]		= &mst_c_lrclk.hw,
+		[AUD_CLKID_MST_D_LRCLK]		= &mst_d_lrclk.hw,
+		[AUD_CLKID_MST_E_LRCLK]		= &mst_e_lrclk.hw,
+		[AUD_CLKID_MST_F_LRCLK]		= &mst_f_lrclk.hw,
+		[AUD_CLKID_TDMIN_A_SCLK_SEL]	= &tdmin_a_sclk_sel.hw,
+		[AUD_CLKID_TDMIN_B_SCLK_SEL]	= &tdmin_b_sclk_sel.hw,
+		[AUD_CLKID_TDMIN_C_SCLK_SEL]	= &tdmin_c_sclk_sel.hw,
+		[AUD_CLKID_TDMIN_LB_SCLK_SEL]	= &tdmin_lb_sclk_sel.hw,
+		[AUD_CLKID_TDMOUT_A_SCLK_SEL]	= &tdmout_a_sclk_sel.hw,
+		[AUD_CLKID_TDMOUT_B_SCLK_SEL]	= &tdmout_b_sclk_sel.hw,
+		[AUD_CLKID_TDMOUT_C_SCLK_SEL]	= &tdmout_c_sclk_sel.hw,
+		[AUD_CLKID_TDMIN_A_SCLK_PRE_EN]	= &tdmin_a_sclk_pre_en.hw,
+		[AUD_CLKID_TDMIN_B_SCLK_PRE_EN]	= &tdmin_b_sclk_pre_en.hw,
+		[AUD_CLKID_TDMIN_C_SCLK_PRE_EN]	= &tdmin_c_sclk_pre_en.hw,
+		[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
+		[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
+		[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
+		[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
+		[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
+		[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
+		[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
+		[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
+		[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
+		[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
+		[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
+		[AUD_CLKID_TDMIN_A_SCLK]	= &tdmin_a_sclk.hw,
+		[AUD_CLKID_TDMIN_B_SCLK]	= &tdmin_b_sclk.hw,
+		[AUD_CLKID_TDMIN_C_SCLK]	= &tdmin_c_sclk.hw,
+		[AUD_CLKID_TDMIN_LB_SCLK]	= &tdmin_lb_sclk.hw,
+		[AUD_CLKID_TDMOUT_A_SCLK]	= &tdmout_a_sclk.hw,
+		[AUD_CLKID_TDMOUT_B_SCLK]	= &tdmout_b_sclk.hw,
+		[AUD_CLKID_TDMOUT_C_SCLK]	= &tdmout_c_sclk.hw,
+		[AUD_CLKID_TDMIN_A_LRCLK]	= &tdmin_a_lrclk.hw,
+		[AUD_CLKID_TDMIN_B_LRCLK]	= &tdmin_b_lrclk.hw,
+		[AUD_CLKID_TDMIN_C_LRCLK]	= &tdmin_c_lrclk.hw,
+		[AUD_CLKID_TDMIN_LB_LRCLK]	= &tdmin_lb_lrclk.hw,
+		[AUD_CLKID_TDMOUT_A_LRCLK]	= &tdmout_a_lrclk.hw,
+		[AUD_CLKID_TDMOUT_B_LRCLK]	= &tdmout_b_lrclk.hw,
+		[AUD_CLKID_TDMOUT_C_LRCLK]	= &tdmout_c_lrclk.hw,
+		[AUD_CLKID_TDM_MCLK_PAD0]	= &sm1_tdm_mclk_pad_0.hw,
+		[AUD_CLKID_TDM_MCLK_PAD1]	= &sm1_tdm_mclk_pad_1.hw,
+		[AUD_CLKID_TDM_LRCLK_PAD0]	= &sm1_tdm_lrclk_pad_0.hw,
+		[AUD_CLKID_TDM_LRCLK_PAD1]	= &sm1_tdm_lrclk_pad_1.hw,
+		[AUD_CLKID_TDM_LRCLK_PAD2]	= &sm1_tdm_lrclk_pad_2.hw,
+		[AUD_CLKID_TDM_SCLK_PAD0]	= &sm1_tdm_sclk_pad_0.hw,
+		[AUD_CLKID_TDM_SCLK_PAD1]	= &sm1_tdm_sclk_pad_1.hw,
+		[AUD_CLKID_TDM_SCLK_PAD2]	= &sm1_tdm_sclk_pad_2.hw,
+		[AUD_CLKID_TOP]			= &sm1_aud_top.hw,
+		[AUD_CLKID_TORAM]		= &toram.hw,
+		[AUD_CLKID_EQDRC]		= &eqdrc.hw,
+		[AUD_CLKID_RESAMPLE_B]		= &resample_b.hw,
+		[AUD_CLKID_TOVAD]		= &tovad.hw,
+		[AUD_CLKID_LOCKER]		= &locker.hw,
+		[AUD_CLKID_SPDIFIN_LB]		= &spdifin_lb.hw,
+		[AUD_CLKID_FRDDR_D]		= &frddr_d.hw,
+		[AUD_CLKID_TODDR_D]		= &toddr_d.hw,
+		[AUD_CLKID_LOOPBACK_B]		= &loopback_b.hw,
+		[AUD_CLKID_CLK81_EN]		= &sm1_clk81_en.hw,
+		[AUD_CLKID_SYSCLK_A_DIV]	= &sm1_sysclk_a_div.hw,
+		[AUD_CLKID_SYSCLK_A_EN]		= &sm1_sysclk_a_en.hw,
+		[AUD_CLKID_SYSCLK_B_DIV]	= &sm1_sysclk_b_div.hw,
+		[AUD_CLKID_SYSCLK_B_EN]		= &sm1_sysclk_b_en.hw,
+		[NR_CLKS] = NULL,
+	},
+	.num = NR_CLKS,
+};
+
+
 /* Convenience table to populate regmap in .probe()
  * Note that this table is shared between both AXG and G12A,
  * with spdifout_b clocks being exclusive to G12A. Since those
  * clocks are not declared within the AXG onecell table, we do not
  * feel the need to have separate AXG/G12A regmap tables.
  */
-static struct clk_regmap *const aud_clk_regmaps[] = {
+static struct clk_regmap *const axg_clk_regmaps[] = {
 	&ddr_arb,
 	&pdm,
 	&tdmin_a,
@@ -993,6 +1349,158 @@ static struct clk_regmap *const aud_clk_regmaps[] = {
 	&g12a_tdm_sclk_pad_0,
 	&g12a_tdm_sclk_pad_1,
 	&g12a_tdm_sclk_pad_2,
+	&toram,
+	&eqdrc,
+};
+
+static struct clk_regmap *const sm1_clk_regmaps[] = {
+	&ddr_arb,
+	&pdm,
+	&tdmin_a,
+	&tdmin_b,
+	&tdmin_c,
+	&tdmin_lb,
+	&tdmout_a,
+	&tdmout_b,
+	&tdmout_c,
+	&frddr_a,
+	&frddr_b,
+	&frddr_c,
+	&toddr_a,
+	&toddr_b,
+	&toddr_c,
+	&loopback,
+	&spdifin,
+	&spdifout,
+	&resample,
+	&spdifout_b,
+	&sm1_mst_a_mclk_sel,
+	&sm1_mst_b_mclk_sel,
+	&sm1_mst_c_mclk_sel,
+	&sm1_mst_d_mclk_sel,
+	&sm1_mst_e_mclk_sel,
+	&sm1_mst_f_mclk_sel,
+	&sm1_mst_a_mclk_div,
+	&sm1_mst_b_mclk_div,
+	&sm1_mst_c_mclk_div,
+	&sm1_mst_d_mclk_div,
+	&sm1_mst_e_mclk_div,
+	&sm1_mst_f_mclk_div,
+	&sm1_mst_a_mclk,
+	&sm1_mst_b_mclk,
+	&sm1_mst_c_mclk,
+	&sm1_mst_d_mclk,
+	&sm1_mst_e_mclk,
+	&sm1_mst_f_mclk,
+	&spdifout_clk_sel,
+	&spdifout_clk_div,
+	&spdifout_clk,
+	&spdifin_clk_sel,
+	&spdifin_clk_div,
+	&spdifin_clk,
+	&pdm_dclk_sel,
+	&pdm_dclk_div,
+	&pdm_dclk,
+	&pdm_sysclk_sel,
+	&pdm_sysclk_div,
+	&pdm_sysclk,
+	&mst_a_sclk_pre_en,
+	&mst_b_sclk_pre_en,
+	&mst_c_sclk_pre_en,
+	&mst_d_sclk_pre_en,
+	&mst_e_sclk_pre_en,
+	&mst_f_sclk_pre_en,
+	&mst_a_sclk_div,
+	&mst_b_sclk_div,
+	&mst_c_sclk_div,
+	&mst_d_sclk_div,
+	&mst_e_sclk_div,
+	&mst_f_sclk_div,
+	&mst_a_sclk_post_en,
+	&mst_b_sclk_post_en,
+	&mst_c_sclk_post_en,
+	&mst_d_sclk_post_en,
+	&mst_e_sclk_post_en,
+	&mst_f_sclk_post_en,
+	&mst_a_sclk,
+	&mst_b_sclk,
+	&mst_c_sclk,
+	&mst_d_sclk,
+	&mst_e_sclk,
+	&mst_f_sclk,
+	&mst_a_lrclk_div,
+	&mst_b_lrclk_div,
+	&mst_c_lrclk_div,
+	&mst_d_lrclk_div,
+	&mst_e_lrclk_div,
+	&mst_f_lrclk_div,
+	&mst_a_lrclk,
+	&mst_b_lrclk,
+	&mst_c_lrclk,
+	&mst_d_lrclk,
+	&mst_e_lrclk,
+	&mst_f_lrclk,
+	&tdmin_a_sclk_sel,
+	&tdmin_b_sclk_sel,
+	&tdmin_c_sclk_sel,
+	&tdmin_lb_sclk_sel,
+	&tdmout_a_sclk_sel,
+	&tdmout_b_sclk_sel,
+	&tdmout_c_sclk_sel,
+	&tdmin_a_sclk_pre_en,
+	&tdmin_b_sclk_pre_en,
+	&tdmin_c_sclk_pre_en,
+	&tdmin_lb_sclk_pre_en,
+	&tdmout_a_sclk_pre_en,
+	&tdmout_b_sclk_pre_en,
+	&tdmout_c_sclk_pre_en,
+	&tdmin_a_sclk_post_en,
+	&tdmin_b_sclk_post_en,
+	&tdmin_c_sclk_post_en,
+	&tdmin_lb_sclk_post_en,
+	&tdmout_a_sclk_post_en,
+	&tdmout_b_sclk_post_en,
+	&tdmout_c_sclk_post_en,
+	&tdmin_a_sclk,
+	&tdmin_b_sclk,
+	&tdmin_c_sclk,
+	&tdmin_lb_sclk,
+	&tdmout_a_sclk,
+	&tdmout_b_sclk,
+	&tdmout_c_sclk,
+	&tdmin_a_lrclk,
+	&tdmin_b_lrclk,
+	&tdmin_c_lrclk,
+	&tdmin_lb_lrclk,
+	&tdmout_a_lrclk,
+	&tdmout_b_lrclk,
+	&tdmout_c_lrclk,
+	&spdifout_b_clk_sel,
+	&spdifout_b_clk_div,
+	&spdifout_b_clk,
+	&sm1_tdm_mclk_pad_0,
+	&sm1_tdm_mclk_pad_1,
+	&sm1_tdm_lrclk_pad_0,
+	&sm1_tdm_lrclk_pad_1,
+	&sm1_tdm_lrclk_pad_2,
+	&sm1_tdm_sclk_pad_0,
+	&sm1_tdm_sclk_pad_1,
+	&sm1_tdm_sclk_pad_2,
+	&sm1_aud_top,
+	&toram,
+	&eqdrc,
+	&resample_b,
+	&tovad,
+	&locker,
+	&spdifin_lb,
+	&frddr_d,
+	&toddr_d,
+	&loopback_b,
+	&sm1_clk81_en,
+	&sm1_sysclk_a_div,
+	&sm1_sysclk_a_en,
+	&sm1_sysclk_b_div,
+	&sm1_sysclk_b_en,
 };
 
 static int devm_clk_get_enable(struct device *dev, char *id)
@@ -1111,6 +1619,8 @@ static const struct regmap_config axg_audio_regmap_cfg = {
 };
 
 struct audioclk_data {
+	struct clk_regmap *const *regmap_clks;
+	unsigned int regmap_clk_num;
 	struct clk_hw_onecell_data *hw_onecell_data;
 	unsigned int reset_offset;
 	unsigned int reset_num;
@@ -1154,8 +1664,8 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
 	}
 
 	/* Populate regmap for the regmap backed clocks */
-	for (i = 0; i < ARRAY_SIZE(aud_clk_regmaps); i++)
-		aud_clk_regmaps[i]->map = map;
+	for (i = 0; i < data->regmap_clk_num; i++)
+		data->regmap_clks[i]->map = map;
 
 	/* Take care to skip the registered input clocks */
 	for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) {
@@ -1199,15 +1709,27 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
 }
 
 static const struct audioclk_data axg_audioclk_data = {
+	.regmap_clks = axg_clk_regmaps,
+	.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
 	.hw_onecell_data = &axg_audio_hw_onecell_data,
 };
 
 static const struct audioclk_data g12a_audioclk_data = {
+	.regmap_clks = axg_clk_regmaps,
+	.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
 	.hw_onecell_data = &g12a_audio_hw_onecell_data,
 	.reset_offset = AUDIO_SW_RESET,
 	.reset_num = 26,
 };
 
+static const struct audioclk_data sm1_audioclk_data = {
+	.regmap_clks = sm1_clk_regmaps,
+	.regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps),
+	.hw_onecell_data = &sm1_audio_hw_onecell_data,
+	.reset_offset = AUDIO_SM1_SW_RESET0,
+	.reset_num = 39,
+};
+
 static const struct of_device_id clkc_match_table[] = {
 	{
 		.compatible = "amlogic,axg-audio-clkc",
@@ -1215,6 +1737,9 @@ static const struct of_device_id clkc_match_table[] = {
 	}, {
 		.compatible = "amlogic,g12a-audio-clkc",
 		.data = &g12a_audioclk_data
+	}, {
+		.compatible = "amlogic,sm1-audio-clkc",
+		.data = &sm1_audioclk_data
 	}, {}
 };
 MODULE_DEVICE_TABLE(of, clkc_match_table);
@@ -1228,6 +1753,6 @@ static struct platform_driver axg_audio_driver = {
 };
 module_platform_driver(axg_audio_driver);
 
-MODULE_DESCRIPTION("Amlogic AXG/G12A Audio Clock driver");
+MODULE_DESCRIPTION("Amlogic AXG/G12A/SM1 Audio Clock driver");
 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h
index a4956837f597..fd65a7d0704b 100644
--- a/drivers/clk/meson/axg-audio.h
+++ b/drivers/clk/meson/axg-audio.h
@@ -50,6 +50,20 @@
 #define AUDIO_CLK_PDMIN_CTRL1	0x0B0
 #define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4
 
+/* SM1 introduce new register and some shifts :( */
+#define AUDIO_CLK_GATE_EN1	0x004
+#define AUDIO_SM1_MCLK_A_CTRL	0x008
+#define AUDIO_SM1_MCLK_B_CTRL	0x00C
+#define AUDIO_SM1_MCLK_C_CTRL	0x010
+#define AUDIO_SM1_MCLK_D_CTRL	0x014
+#define AUDIO_SM1_MCLK_E_CTRL	0x018
+#define AUDIO_SM1_MCLK_F_CTRL	0x01C
+#define AUDIO_SM1_MST_PAD_CTRL0	0x020
+#define AUDIO_SM1_MST_PAD_CTRL1	0x024
+#define AUDIO_SM1_SW_RESET0	0x028
+#define AUDIO_SM1_SW_RESET1	0x02C
+#define AUDIO_CLK81_CTRL	0x030
+#define AUDIO_CLK81_EN		0x034
 /*
  * CLKID index values
  * These indices are entirely contrived and do not map onto the hardware.
@@ -115,11 +129,15 @@
 #define AUD_CLKID_TDMOUT_C_SCLK_POST_EN	150
 #define AUD_CLKID_SPDIFOUT_B_CLK_SEL	153
 #define AUD_CLKID_SPDIFOUT_B_CLK_DIV	154
-
+#define AUD_CLKID_CLK81_EN		173
+#define AUD_CLKID_SYSCLK_A_DIV		174
+#define AUD_CLKID_SYSCLK_B_DIV		175
+#define AUD_CLKID_SYSCLK_A_EN		176
+#define AUD_CLKID_SYSCLK_B_EN		177
 
 /* include the CLKIDs which are part of the DT bindings */
 #include <dt-bindings/clock/axg-audio-clkc.h>
 
-#define NR_CLKS	164
+#define NR_CLKS	178
 
 #endif /*__AXG_AUDIO_CLKC_H */
-- 
2.21.0


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 1/7] dt-bindings: clk: axg-audio: add sm1 bindings
  2019-09-24 15:33 ` [PATCH 1/7] dt-bindings: clk: axg-audio: add sm1 bindings Jerome Brunet
@ 2019-09-27  9:10   ` Neil Armstrong
  0 siblings, 0 replies; 19+ messages in thread
From: Neil Armstrong @ 2019-09-27  9:10 UTC (permalink / raw)
  To: Jerome Brunet; +Cc: Kevin Hilman, linux-amlogic, linux-clk, linux-kernel

On 24/09/2019 17:33, Jerome Brunet wrote:
> Add the compatible and clock ids of the sm1 audio clock controller
> 
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
>  .../bindings/clock/amlogic,axg-audio-clkc.txt          |  3 ++-
>  include/dt-bindings/clock/axg-audio-clkc.h             | 10 ++++++++++
>  2 files changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
> index b3957d10d241..3a8948c04bc9 100644
> --- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
> +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
> @@ -7,7 +7,8 @@ devices.
>  Required Properties:
>  
>  - compatible	: should be "amlogic,axg-audio-clkc" for the A113X and A113D,
> -		  "amlogic,g12a-audio-clkc" for G12A.
> +		  "amlogic,g12a-audio-clkc" for G12A,
> +		  "amlogic,sm1-audio-clkc" for S905X3.
>  - reg		: physical base address of the clock controller and length of
>  		  memory mapped region.
>  - clocks	: a list of phandle + clock-specifier pairs for the clocks listed
> diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h
> index 75901c636893..f561f5c5ef8f 100644
> --- a/include/dt-bindings/clock/axg-audio-clkc.h
> +++ b/include/dt-bindings/clock/axg-audio-clkc.h
> @@ -80,5 +80,15 @@
>  #define AUD_CLKID_TDM_SCLK_PAD0		160
>  #define AUD_CLKID_TDM_SCLK_PAD1		161
>  #define AUD_CLKID_TDM_SCLK_PAD2		162
> +#define AUD_CLKID_TOP			163
> +#define AUD_CLKID_TORAM			164
> +#define AUD_CLKID_EQDRC			165
> +#define AUD_CLKID_RESAMPLE_B		166
> +#define AUD_CLKID_TOVAD			167
> +#define AUD_CLKID_LOCKER		168
> +#define AUD_CLKID_SPDIFIN_LB		169
> +#define AUD_CLKID_FRDDR_D		170
> +#define AUD_CLKID_TODDR_D		171
> +#define AUD_CLKID_LOOPBACK_B		172
>  
>  #endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
> 

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 2/7] dt-bindings: clock: meson: add sm1 resets to the axg-audio controller
  2019-09-24 15:33 ` [PATCH 2/7] dt-bindings: clock: meson: add sm1 resets to the axg-audio controller Jerome Brunet
@ 2019-09-27  9:10   ` Neil Armstrong
  0 siblings, 0 replies; 19+ messages in thread
From: Neil Armstrong @ 2019-09-27  9:10 UTC (permalink / raw)
  To: Jerome Brunet; +Cc: Kevin Hilman, linux-amlogic, linux-clk, linux-kernel

On 24/09/2019 17:33, Jerome Brunet wrote:
> Add the reset id of the sm1 audio clock controller
> 
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
>  .../reset/amlogic,meson-g12a-audio-reset.h        | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
> index 14b78dabed0e..f805129ca7af 100644
> --- a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
> +++ b/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
> @@ -35,4 +35,19 @@
>  #define AUD_RESET_TOHDMITX	24
>  #define AUD_RESET_CLKTREE	25
>  
> +/* SM1 added resets */
> +#define AUD_RESET_RESAMPLE_B	26
> +#define AUD_RESET_TOVAD		27
> +#define AUD_RESET_LOCKER	28
> +#define AUD_RESET_SPDIFIN_LB	29
> +#define AUD_RESET_FRATV		30
> +#define AUD_RESET_FRHDMIRX	31
> +#define AUD_RESET_FRDDR_D	32
> +#define AUD_RESET_TODDR_D	33
> +#define AUD_RESET_LOOPBACK_B	34
> +#define AUD_RESET_EARCTX	35
> +#define AUD_RESET_EARCRX	36
> +#define AUD_RESET_FRDDR_E	37
> +#define AUD_RESET_TODDR_E	38
> +
>  #endif
> 

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 3/7] clk: meson: axg-audio: remove useless defines
  2019-09-24 15:33 ` [PATCH 3/7] clk: meson: axg-audio: remove useless defines Jerome Brunet
@ 2019-09-27  9:10   ` Neil Armstrong
  0 siblings, 0 replies; 19+ messages in thread
From: Neil Armstrong @ 2019-09-27  9:10 UTC (permalink / raw)
  To: Jerome Brunet; +Cc: Kevin Hilman, linux-amlogic, linux-clk, linux-kernel

On 24/09/2019 17:33, Jerome Brunet wrote:
> Defining the number of each input type is no longer necessary since
> we are not using the clk-input hack anymore
> 
> Fixes: 282420eed23f ("clk: meson: axg-audio: migrate to the new parent description method")
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
>  drivers/clk/meson/axg-audio.c | 4 ----
>  1 file changed, 4 deletions(-)
> 
> diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
> index 18b23cdf679c..60ac71856e5e 100644
> --- a/drivers/clk/meson/axg-audio.c
> +++ b/drivers/clk/meson/axg-audio.c
> @@ -20,10 +20,6 @@
>  #include "clk-phase.h"
>  #include "sclk-div.h"
>  
> -#define AUD_MST_IN_COUNT	8
> -#define AUD_SLV_SCLK_COUNT	10
> -#define AUD_SLV_LRCLK_COUNT	10
> -
>  #define AUD_GATE(_name, _reg, _bit, _phws, _iflags)			\
>  struct clk_regmap aud_##_name = {					\
>  	.data = &(struct clk_regmap_gate_data){				\
> 

Acked-by: Neil Armstrong <narmstrong@baylibre.com>

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 4/7] clk: meson: axg-audio: fix regmap last register
  2019-09-24 15:33 ` [PATCH 4/7] clk: meson: axg-audio: fix regmap last register Jerome Brunet
@ 2019-09-27  9:11   ` Neil Armstrong
  0 siblings, 0 replies; 19+ messages in thread
From: Neil Armstrong @ 2019-09-27  9:11 UTC (permalink / raw)
  To: Jerome Brunet; +Cc: Kevin Hilman, linux-amlogic, linux-clk, linux-kernel

On 24/09/2019 17:33, Jerome Brunet wrote:
> Since the addition of the g12a, the last register is
> AUDIO_CLK_SPDIFOUT_B_CTRL.
> 
> Fixes: 075001385c66 ("clk: meson: axg-audio: add g12a support")
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
>  drivers/clk/meson/axg-audio.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
> index 60ac71856e5e..4b34601342bb 100644
> --- a/drivers/clk/meson/axg-audio.c
> +++ b/drivers/clk/meson/axg-audio.c
> @@ -997,7 +997,7 @@ static const struct regmap_config axg_audio_regmap_cfg = {
>  	.reg_bits	= 32,
>  	.val_bits	= 32,
>  	.reg_stride	= 4,
> -	.max_register	= AUDIO_CLK_PDMIN_CTRL1,
> +	.max_register	= AUDIO_CLK_SPDIFOUT_B_CTRL,
>  };
>  
>  struct audioclk_data {
> 

Acked-by: Neil Armstrong <narmstrong@baylibre.com>

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 5/7] clk: meson: axg-audio: prepare sm1 addition
  2019-09-24 15:33 ` [PATCH 5/7] clk: meson: axg-audio: prepare sm1 addition Jerome Brunet
@ 2019-09-27  9:13   ` Neil Armstrong
  0 siblings, 0 replies; 19+ messages in thread
From: Neil Armstrong @ 2019-09-27  9:13 UTC (permalink / raw)
  To: Jerome Brunet; +Cc: Kevin Hilman, linux-amlogic, linux-clk, linux-kernel

On 24/09/2019 17:33, Jerome Brunet wrote:
> Rearrange the macro definition of the clocks of the axg-audio
> controller. Also, the sm1 variant will feature tiny modification
> of different blocks in this controller. Because of that, we need
> to fallback to the old way of defining parent for some of the
> clocks, using signal name.
> 
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
>  drivers/clk/meson/axg-audio.c | 1467 ++++++++++++++++++---------------
>  1 file changed, 782 insertions(+), 685 deletions(-)
> 
> diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
> index 4b34601342bb..ce8836776d1c 100644
> --- a/drivers/clk/meson/axg-audio.c
> +++ b/drivers/clk/meson/axg-audio.c
> @@ -20,8 +20,7 @@
>  #include "clk-phase.h"
>  #include "sclk-div.h"
>  
> -#define AUD_GATE(_name, _reg, _bit, _phws, _iflags)			\
> -struct clk_regmap aud_##_name = {					\
> +#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) {			\
>  	.data = &(struct clk_regmap_gate_data){				\
>  		.offset = (_reg),					\
>  		.bit_idx = (_bit),					\
> @@ -29,14 +28,13 @@ struct clk_regmap aud_##_name = {					\
>  	.hw.init = &(struct clk_init_data) {				\
>  		.name = "aud_"#_name,					\
>  		.ops = &clk_regmap_gate_ops,				\
> -		.parent_hws = (const struct clk_hw *[]) { &_phws.hw },	\
> +		.parent_names = (const char *[]){ #_pname },		\
>  		.num_parents = 1,					\
>  		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\
>  	},								\
>  }
>  
> -#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags)	\
> -struct clk_regmap aud_##_name = {					\
> +#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) {	\
>  	.data = &(struct clk_regmap_mux_data){				\
>  		.offset = (_reg),					\
>  		.mask = (_mask),					\
> @@ -52,8 +50,7 @@ struct clk_regmap aud_##_name = {					\
>  	},								\
>  }
>  
> -#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _phws, _iflags)	\
> -struct clk_regmap aud_##_name = {					\
> +#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \
>  	.data = &(struct clk_regmap_div_data){				\
>  		.offset = (_reg),					\
>  		.shift = (_shift),					\
> @@ -63,14 +60,13 @@ struct clk_regmap aud_##_name = {					\
>  	.hw.init = &(struct clk_init_data){				\
>  		.name = "aud_"#_name,					\
>  		.ops = &clk_regmap_divider_ops,				\
> -		.parent_hws = (const struct clk_hw *[]) { &_phws.hw },	\
> +		.parent_names = (const char *[]){ #_pname },		\
>  		.num_parents = 1,					\
>  		.flags = (_iflags),					\
>  	},								\
>  }
>  
> -#define AUD_PCLK_GATE(_name, _bit)				\
> -struct clk_regmap aud_##_name = {					\
> +#define AUD_PCLK_GATE(_name, _bit) {					\
>  	.data = &(struct clk_regmap_gate_data){				\
>  		.offset = (AUDIO_CLK_GATE_EN),				\
>  		.bit_idx = (_bit),					\
> @@ -84,116 +80,9 @@ struct clk_regmap aud_##_name = {					\
>  		.num_parents = 1,					\
>  	},								\
>  }
> -/* Audio peripheral clocks */
> -static AUD_PCLK_GATE(ddr_arb,	   0);
> -static AUD_PCLK_GATE(pdm,	   1);
> -static AUD_PCLK_GATE(tdmin_a,	   2);
> -static AUD_PCLK_GATE(tdmin_b,	   3);
> -static AUD_PCLK_GATE(tdmin_c,	   4);
> -static AUD_PCLK_GATE(tdmin_lb,	   5);
> -static AUD_PCLK_GATE(tdmout_a,	   6);
> -static AUD_PCLK_GATE(tdmout_b,	   7);
> -static AUD_PCLK_GATE(tdmout_c,	   8);
> -static AUD_PCLK_GATE(frddr_a,	   9);
> -static AUD_PCLK_GATE(frddr_b,	   10);
> -static AUD_PCLK_GATE(frddr_c,	   11);
> -static AUD_PCLK_GATE(toddr_a,	   12);
> -static AUD_PCLK_GATE(toddr_b,	   13);
> -static AUD_PCLK_GATE(toddr_c,	   14);
> -static AUD_PCLK_GATE(loopback,	   15);
> -static AUD_PCLK_GATE(spdifin,	   16);
> -static AUD_PCLK_GATE(spdifout,	   17);
> -static AUD_PCLK_GATE(resample,	   18);
> -static AUD_PCLK_GATE(power_detect, 19);
> -static AUD_PCLK_GATE(spdifout_b,   21);
> -
> -/* Audio Master Clocks */
> -static const struct clk_parent_data mst_mux_parent_data[] = {
> -	{ .fw_name = "mst_in0", },
> -	{ .fw_name = "mst_in1", },
> -	{ .fw_name = "mst_in2", },
> -	{ .fw_name = "mst_in3", },
> -	{ .fw_name = "mst_in4", },
> -	{ .fw_name = "mst_in5", },
> -	{ .fw_name = "mst_in6", },
> -	{ .fw_name = "mst_in7", },
> -};
> -
> -#define AUD_MST_MUX(_name, _reg, _flag)				\
> -	AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag,		\
> -		mst_mux_parent_data, 0)
> -
> -#define AUD_MST_MCLK_MUX(_name, _reg)				\
> -	AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
> -
> -#define AUD_MST_SYS_MUX(_name, _reg)				\
> -	AUD_MST_MUX(_name, _reg, 0)
> -
> -static AUD_MST_MCLK_MUX(mst_a_mclk,   AUDIO_MCLK_A_CTRL);
> -static AUD_MST_MCLK_MUX(mst_b_mclk,   AUDIO_MCLK_B_CTRL);
> -static AUD_MST_MCLK_MUX(mst_c_mclk,   AUDIO_MCLK_C_CTRL);
> -static AUD_MST_MCLK_MUX(mst_d_mclk,   AUDIO_MCLK_D_CTRL);
> -static AUD_MST_MCLK_MUX(mst_e_mclk,   AUDIO_MCLK_E_CTRL);
> -static AUD_MST_MCLK_MUX(mst_f_mclk,   AUDIO_MCLK_F_CTRL);
> -static AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
> -static AUD_MST_MCLK_MUX(pdm_dclk,     AUDIO_CLK_PDMIN_CTRL0);
> -static AUD_MST_SYS_MUX(spdifin_clk,   AUDIO_CLK_SPDIFIN_CTRL);
> -static AUD_MST_SYS_MUX(pdm_sysclk,    AUDIO_CLK_PDMIN_CTRL1);
> -static AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
> -
> -#define AUD_MST_DIV(_name, _reg, _flag)				\
> -	AUD_DIV(_name##_div, _reg, 0, 16, _flag,		\
> -		    aud_##_name##_sel, CLK_SET_RATE_PARENT)	\
> -
> -#define AUD_MST_MCLK_DIV(_name, _reg)				\
> -	AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
> -
> -#define AUD_MST_SYS_DIV(_name, _reg)				\
> -	AUD_MST_DIV(_name, _reg, 0)
> -
> -static AUD_MST_MCLK_DIV(mst_a_mclk,   AUDIO_MCLK_A_CTRL);
> -static AUD_MST_MCLK_DIV(mst_b_mclk,   AUDIO_MCLK_B_CTRL);
> -static AUD_MST_MCLK_DIV(mst_c_mclk,   AUDIO_MCLK_C_CTRL);
> -static AUD_MST_MCLK_DIV(mst_d_mclk,   AUDIO_MCLK_D_CTRL);
> -static AUD_MST_MCLK_DIV(mst_e_mclk,   AUDIO_MCLK_E_CTRL);
> -static AUD_MST_MCLK_DIV(mst_f_mclk,   AUDIO_MCLK_F_CTRL);
> -static AUD_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
> -static AUD_MST_MCLK_DIV(pdm_dclk,     AUDIO_CLK_PDMIN_CTRL0);
> -static AUD_MST_SYS_DIV(spdifin_clk,   AUDIO_CLK_SPDIFIN_CTRL);
> -static AUD_MST_SYS_DIV(pdm_sysclk,    AUDIO_CLK_PDMIN_CTRL1);
> -static AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
> -
> -#define AUD_MST_MCLK_GATE(_name, _reg)				\
> -	AUD_GATE(_name, _reg, 31,  aud_##_name##_div,		\
> -		 CLK_SET_RATE_PARENT)
> -
> -static AUD_MST_MCLK_GATE(mst_a_mclk,   AUDIO_MCLK_A_CTRL);
> -static AUD_MST_MCLK_GATE(mst_b_mclk,   AUDIO_MCLK_B_CTRL);
> -static AUD_MST_MCLK_GATE(mst_c_mclk,   AUDIO_MCLK_C_CTRL);
> -static AUD_MST_MCLK_GATE(mst_d_mclk,   AUDIO_MCLK_D_CTRL);
> -static AUD_MST_MCLK_GATE(mst_e_mclk,   AUDIO_MCLK_E_CTRL);
> -static AUD_MST_MCLK_GATE(mst_f_mclk,   AUDIO_MCLK_F_CTRL);
> -static AUD_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
> -static AUD_MST_MCLK_GATE(spdifin_clk,  AUDIO_CLK_SPDIFIN_CTRL);
> -static AUD_MST_MCLK_GATE(pdm_dclk,     AUDIO_CLK_PDMIN_CTRL0);
> -static AUD_MST_MCLK_GATE(pdm_sysclk,   AUDIO_CLK_PDMIN_CTRL1);
> -static AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
> -
> -/* Sample Clocks */
> -#define AUD_MST_SCLK_PRE_EN(_name, _reg)			\
> -	AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31,		\
> -		 aud_mst_##_name##_mclk, 0)
> -
> -static AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
> -static AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
> -static AUD_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0);
> -static AUD_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0);
> -static AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
> -static AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
>  
>  #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width,		\
> -			 _hi_shift, _hi_width, _phws, _iflags)		\
> -struct clk_regmap aud_##_name = {					\
> +		     _hi_shift, _hi_width, _pname, _iflags) {		\
>  	.data = &(struct meson_sclk_div_data) {				\
>  		.div = {						\
>  			.reg_off = (_reg),				\
> @@ -209,38 +98,14 @@ struct clk_regmap aud_##_name = {					\
>  	.hw.init = &(struct clk_init_data) {				\
>  		.name = "aud_"#_name,					\
>  		.ops = &meson_sclk_div_ops,				\
> -		.parent_hws = (const struct clk_hw *[]) { &_phws.hw },	\
> +		.parent_names = (const char *[]){ #_pname },		\
>  		.num_parents = 1,					\
>  		.flags = (_iflags),					\
>  	},								\
>  }
>  
> -#define AUD_MST_SCLK_DIV(_name, _reg)					\
> -	AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0,	\
> -		     aud_mst_##_name##_sclk_pre_en,			\
> -		     CLK_SET_RATE_PARENT)
> -
> -static AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
> -static AUD_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
> -static AUD_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
> -static AUD_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
> -static AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
> -static AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
> -
> -#define AUD_MST_SCLK_POST_EN(_name, _reg)				\
> -	AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30,			\
> -		 aud_mst_##_name##_sclk_div, CLK_SET_RATE_PARENT)
> -
> -static AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
> -static AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
> -static AUD_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0);
> -static AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
> -static AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
> -static AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
> -
>  #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2,	\
> -			 _phws, _iflags)				\
> -struct clk_regmap aud_##_name = {					\
> +		     _pname, _iflags) {					\
>  	.data = &(struct meson_clk_triphase_data) {			\
>  		.ph0 = {						\
>  			.reg_off = (_reg),				\
> @@ -261,52 +126,91 @@ struct clk_regmap aud_##_name = {					\
>  	.hw.init = &(struct clk_init_data) {				\
>  		.name = "aud_"#_name,					\
>  		.ops = &meson_clk_triphase_ops,				\
> -		.parent_hws = (const struct clk_hw *[]) { &_phws.hw },	\
> +		.parent_names = (const char *[]){ #_pname },		\
>  		.num_parents = 1,					\
>  		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\
>  	},								\
>  }
>  
> +#define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) {	\
> +	.data = &(struct meson_clk_phase_data) {			\
> +		.ph = {							\
> +			.reg_off = (_reg),				\
> +			.shift   = (_shift),				\
> +			.width   = (_width),				\
> +		},							\
> +	},								\
> +	.hw.init = &(struct clk_init_data) {				\
> +		.name = "aud_"#_name,					\
> +		.ops = &meson_clk_phase_ops,				\
> +		.parent_names = (const char *[]){ #_pname },		\
> +		.num_parents = 1,					\
> +		.flags = (_iflags),					\
> +	},								\
> +}
> +
> +/* Audio Master Clocks */
> +static const struct clk_parent_data mst_mux_parent_data[] = {
> +	{ .fw_name = "mst_in0", },
> +	{ .fw_name = "mst_in1", },
> +	{ .fw_name = "mst_in2", },
> +	{ .fw_name = "mst_in3", },
> +	{ .fw_name = "mst_in4", },
> +	{ .fw_name = "mst_in5", },
> +	{ .fw_name = "mst_in6", },
> +	{ .fw_name = "mst_in7", },
> +};
> +
> +#define AUD_MST_MUX(_name, _reg, _flag)					\
> +	AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag,			\
> +		mst_mux_parent_data, 0)
> +#define AUD_MST_DIV(_name, _reg, _flag)					\
> +	AUD_DIV(_name##_div, _reg, 0, 16, _flag,			\
> +		aud_##_name##_sel, CLK_SET_RATE_PARENT)
> +#define AUD_MST_MCLK_GATE(_name, _reg)					\
> +	AUD_GATE(_name, _reg, 31, aud_##_name##_div,			\
> +		 CLK_SET_RATE_PARENT)
> +
> +#define AUD_MST_MCLK_MUX(_name, _reg)					\
> +	AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
> +#define AUD_MST_MCLK_DIV(_name, _reg)					\
> +	AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
> +
> +#define AUD_MST_SYS_MUX(_name, _reg)					\
> +	AUD_MST_MUX(_name, _reg, 0)
> +#define AUD_MST_SYS_DIV(_name, _reg)					\
> +	AUD_MST_DIV(_name, _reg, 0)
> +
> +/* Sample Clocks */
> +#define AUD_MST_SCLK_PRE_EN(_name, _reg)				\
> +	AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31,			\
> +		 aud_mst_##_name##_mclk, 0)
> +#define AUD_MST_SCLK_DIV(_name, _reg)					\
> +	AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0,	\
> +		     aud_mst_##_name##_sclk_pre_en,			\
> +		     CLK_SET_RATE_PARENT)
> +#define AUD_MST_SCLK_POST_EN(_name, _reg)				\
> +	AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30,			\
> +		 aud_mst_##_name##_sclk_div, CLK_SET_RATE_PARENT)
>  #define AUD_MST_SCLK(_name, _reg)					\
>  	AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4,		\
>  		     aud_mst_##_name##_sclk_post_en, CLK_SET_RATE_PARENT)
>  
> -static AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
> -static AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
> -static AUD_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1);
> -static AUD_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1);
> -static AUD_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1);
> -static AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
> -
>  #define AUD_MST_LRCLK_DIV(_name, _reg)					\
>  	AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10,	\
> -		     aud_mst_##_name##_sclk_post_en, 0)			\
> -
> -static AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
> -static AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
> -static AUD_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
> -static AUD_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
> -static AUD_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
> -static AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
> -
> +		     aud_mst_##_name##_sclk_post_en, 0)
>  #define AUD_MST_LRCLK(_name, _reg)					\
>  	AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5,		\
>  		     aud_mst_##_name##_lrclk_div, CLK_SET_RATE_PARENT)
>  
> -static AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
> -static AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
> -static AUD_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1);
> -static AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
> -static AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
> -static AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
> -
> +/* TDM bit clock sources */
>  static const struct clk_parent_data tdm_sclk_parent_data[] = {
> -	{ .hw = &aud_mst_a_sclk.hw, },
> -	{ .hw = &aud_mst_b_sclk.hw, },
> -	{ .hw = &aud_mst_c_sclk.hw, },
> -	{ .hw = &aud_mst_d_sclk.hw, },
> -	{ .hw = &aud_mst_e_sclk.hw, },
> -	{ .hw = &aud_mst_f_sclk.hw, },
> +	{ .name = "aud_mst_a_sclk", .index = -1, },
> +	{ .name = "aud_mst_b_sclk", .index = -1, },
> +	{ .name = "aud_mst_c_sclk", .index = -1, },
> +	{ .name = "aud_mst_d_sclk", .index = -1, },
> +	{ .name = "aud_mst_e_sclk", .index = -1, },
> +	{ .name = "aud_mst_f_sclk", .index = -1, },
>  	{ .fw_name = "slv_sclk0", },
>  	{ .fw_name = "slv_sclk1", },
>  	{ .fw_name = "slv_sclk2", },
> @@ -319,78 +223,14 @@ static const struct clk_parent_data tdm_sclk_parent_data[] = {
>  	{ .fw_name = "slv_sclk9", },
>  };
>  
> -#define AUD_TDM_SCLK_MUX(_name, _reg)				\
> -	AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24,		\
> -		    CLK_MUX_ROUND_CLOSEST,			\
> -		    tdm_sclk_parent_data, 0)
> -
> -static AUD_TDM_SCLK_MUX(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
> -static AUD_TDM_SCLK_MUX(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
> -static AUD_TDM_SCLK_MUX(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
> -static AUD_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
> -static AUD_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
> -static AUD_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
> -static AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
> -
> -#define AUD_TDM_SCLK_PRE_EN(_name, _reg)				\
> -	AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31,			\
> -		 aud_tdm##_name##_sclk_sel, CLK_SET_RATE_PARENT)
> -
> -static AUD_TDM_SCLK_PRE_EN(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
> -static AUD_TDM_SCLK_PRE_EN(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
> -static AUD_TDM_SCLK_PRE_EN(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
> -static AUD_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
> -static AUD_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
> -static AUD_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
> -static AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
> -
> -#define AUD_TDM_SCLK_POST_EN(_name, _reg)				\
> -	AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30,			\
> -		 aud_tdm##_name##_sclk_pre_en, CLK_SET_RATE_PARENT)
> -
> -static AUD_TDM_SCLK_POST_EN(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
> -static AUD_TDM_SCLK_POST_EN(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
> -static AUD_TDM_SCLK_POST_EN(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
> -static AUD_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
> -static AUD_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
> -static AUD_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
> -static AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
> -
> -#define AUD_TDM_SCLK(_name, _reg)					\
> -	struct clk_regmap aud_tdm##_name##_sclk = {			\
> -	.data = &(struct meson_clk_phase_data) {			\
> -		.ph = {							\
> -			.reg_off = (_reg),				\
> -			.shift   = 29,					\
> -			.width   = 1,					\
> -		},							\
> -	},								\
> -	.hw.init = &(struct clk_init_data) {				\
> -		.name = "aud_tdm"#_name"_sclk",				\
> -		.ops = &meson_clk_phase_ops,				\
> -		.parent_hws = (const struct clk_hw *[]) {		\
> -			&aud_tdm##_name##_sclk_post_en.hw		\
> -		},							\
> -		.num_parents = 1,					\
> -		.flags = CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT,	\
> -	},								\
> -}
> -
> -static AUD_TDM_SCLK(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
> -static AUD_TDM_SCLK(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
> -static AUD_TDM_SCLK(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
> -static AUD_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
> -static AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
> -static AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
> -static AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
> -
> +/* TDM sample clock sources */
>  static const struct clk_parent_data tdm_lrclk_parent_data[] = {
> -	{ .hw = &aud_mst_a_lrclk.hw, },
> -	{ .hw = &aud_mst_b_lrclk.hw, },
> -	{ .hw = &aud_mst_c_lrclk.hw, },
> -	{ .hw = &aud_mst_d_lrclk.hw, },
> -	{ .hw = &aud_mst_e_lrclk.hw, },
> -	{ .hw = &aud_mst_f_lrclk.hw, },
> +	{ .name = "aud_mst_a_lrclk", .index = -1, },
> +	{ .name = "aud_mst_b_lrclk", .index = -1, },
> +	{ .name = "aud_mst_c_lrclk", .index = -1, },
> +	{ .name = "aud_mst_d_lrclk", .index = -1, },
> +	{ .name = "aud_mst_e_lrclk", .index = -1, },
> +	{ .name = "aud_mst_f_lrclk", .index = -1, },
>  	{ .fw_name = "slv_lrclk0", },
>  	{ .fw_name = "slv_lrclk1", },
>  	{ .fw_name = "slv_lrclk2", },
> @@ -403,69 +243,326 @@ static const struct clk_parent_data tdm_lrclk_parent_data[] = {
>  	{ .fw_name = "slv_lrclk9", },
>  };
>  
> -#define AUD_TDM_LRLCK(_name, _reg)			\
> -	AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20,	\
> -		CLK_MUX_ROUND_CLOSEST,			\
> -		tdm_lrclk_parent_data, 0)
> -
> -static AUD_TDM_LRLCK(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
> -static AUD_TDM_LRLCK(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
> -static AUD_TDM_LRLCK(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
> -static AUD_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
> -static AUD_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
> -static AUD_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
> -static AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
> +#define AUD_TDM_SCLK_MUX(_name, _reg)					\
> +	AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24,			\
> +		CLK_MUX_ROUND_CLOSEST, tdm_sclk_parent_data, 0)
> +#define AUD_TDM_SCLK_PRE_EN(_name, _reg)				\
> +	AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31,			\
> +		 aud_tdm##_name##_sclk_sel, CLK_SET_RATE_PARENT)
> +#define AUD_TDM_SCLK_POST_EN(_name, _reg)				\
> +	AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30,			\
> +		 aud_tdm##_name##_sclk_pre_en, CLK_SET_RATE_PARENT)
> +#define AUD_TDM_SCLK(_name, _reg)					\
> +	AUD_PHASE(tdm##_name##_sclk, _reg, 1, 29,			\
> +		  aud_tdm##_name##_sclk_post_en,			\
> +		  CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT)
>  
> -/* G12a Pad control */
> -#define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents)		\
> -	AUD_MUX(tdm_##_name, _reg, 0x7, _shift, 0, _parents,	\
> -		CLK_SET_RATE_NO_REPARENT)
> +#define AUD_TDM_LRLCK(_name, _reg)					\
> +	AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20,			\
> +		CLK_MUX_ROUND_CLOSEST, tdm_lrclk_parent_data, 0)
>  
> +/* Pad master clock sources */
>  static const struct clk_parent_data mclk_pad_ctrl_parent_data[] = {
> -	{ .hw = &aud_mst_a_mclk.hw },
> -	{ .hw = &aud_mst_b_mclk.hw },
> -	{ .hw = &aud_mst_c_mclk.hw },
> -	{ .hw = &aud_mst_d_mclk.hw },
> -	{ .hw = &aud_mst_e_mclk.hw },
> -	{ .hw = &aud_mst_f_mclk.hw },
> +	{ .name = "aud_mst_a_mclk", .index = -1,  },
> +	{ .name = "aud_mst_b_mclk", .index = -1,  },
> +	{ .name = "aud_mst_c_mclk", .index = -1,  },
> +	{ .name = "aud_mst_d_mclk", .index = -1,  },
> +	{ .name = "aud_mst_e_mclk", .index = -1,  },
> +	{ .name = "aud_mst_f_mclk", .index = -1,  },
>  };
>  
> -static AUD_TDM_PAD_CTRL(mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0,
> -			mclk_pad_ctrl_parent_data);
> -static AUD_TDM_PAD_CTRL(mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4,
> -			mclk_pad_ctrl_parent_data);
> +/* Pad bit clock sources */
> +static const struct clk_parent_data sclk_pad_ctrl_parent_data[] = {
> +	{ .name = "aud_mst_a_sclk", .index = -1, },
> +	{ .name = "aud_mst_b_sclk", .index = -1, },
> +	{ .name = "aud_mst_c_sclk", .index = -1, },
> +	{ .name = "aud_mst_d_sclk", .index = -1, },
> +	{ .name = "aud_mst_e_sclk", .index = -1, },
> +	{ .name = "aud_mst_f_sclk", .index = -1, },
> +};
>  
> +/* Pad sample clock sources */
>  static const struct clk_parent_data lrclk_pad_ctrl_parent_data[] = {
> -	{ .hw = &aud_mst_a_lrclk.hw },
> -	{ .hw = &aud_mst_b_lrclk.hw },
> -	{ .hw = &aud_mst_c_lrclk.hw },
> -	{ .hw = &aud_mst_d_lrclk.hw },
> -	{ .hw = &aud_mst_e_lrclk.hw },
> -	{ .hw = &aud_mst_f_lrclk.hw },
> +	{ .name = "aud_mst_a_lrclk", .index = -1, },
> +	{ .name = "aud_mst_b_lrclk", .index = -1, },
> +	{ .name = "aud_mst_c_lrclk", .index = -1, },
> +	{ .name = "aud_mst_d_lrclk", .index = -1, },
> +	{ .name = "aud_mst_e_lrclk", .index = -1, },
> +	{ .name = "aud_mst_f_lrclk", .index = -1, },
>  };
>  
> -static AUD_TDM_PAD_CTRL(lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16,
> -			lrclk_pad_ctrl_parent_data);
> -static AUD_TDM_PAD_CTRL(lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20,
> -			lrclk_pad_ctrl_parent_data);
> -static AUD_TDM_PAD_CTRL(lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24,
> -			lrclk_pad_ctrl_parent_data);
> -
> -static const struct clk_parent_data sclk_pad_ctrl_parent_data[] = {
> -	{ .hw = &aud_mst_a_sclk.hw },
> -	{ .hw = &aud_mst_b_sclk.hw },
> -	{ .hw = &aud_mst_c_sclk.hw },
> -	{ .hw = &aud_mst_d_sclk.hw },
> -	{ .hw = &aud_mst_e_sclk.hw },
> -	{ .hw = &aud_mst_f_sclk.hw },
> -};
> +#define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents)		\
> +	AUD_MUX(tdm_##_name, _reg, 0x7, _shift, 0, _parents,	\
> +		CLK_SET_RATE_NO_REPARENT)
>  
> -static AUD_TDM_PAD_CTRL(sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0,
> -			sclk_pad_ctrl_parent_data);
> -static AUD_TDM_PAD_CTRL(sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4,
> -			sclk_pad_ctrl_parent_data);
> -static AUD_TDM_PAD_CTRL(sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8,
> -			sclk_pad_ctrl_parent_data);
> +/* Common Clocks */
> +static struct clk_regmap ddr_arb	= AUD_PCLK_GATE(ddr_arb, 0);
> +static struct clk_regmap pdm		= AUD_PCLK_GATE(pdm, 1);
> +static struct clk_regmap tdmin_a	= AUD_PCLK_GATE(tdmin_a, 2);
> +static struct clk_regmap tdmin_b	= AUD_PCLK_GATE(tdmin_b, 3);
> +static struct clk_regmap tdmin_c	= AUD_PCLK_GATE(tdmin_c, 4);
> +static struct clk_regmap tdmin_lb	= AUD_PCLK_GATE(tdmin_lb, 5);
> +static struct clk_regmap tdmout_a	= AUD_PCLK_GATE(tdmout_a, 6);
> +static struct clk_regmap tdmout_b	= AUD_PCLK_GATE(tdmout_b, 7);
> +static struct clk_regmap tdmout_c	= AUD_PCLK_GATE(tdmout_c, 8);
> +static struct clk_regmap frddr_a	= AUD_PCLK_GATE(frddr_a, 9);
> +static struct clk_regmap frddr_b	= AUD_PCLK_GATE(frddr_b, 10);
> +static struct clk_regmap frddr_c	= AUD_PCLK_GATE(frddr_c, 11);
> +static struct clk_regmap toddr_a	= AUD_PCLK_GATE(toddr_a, 12);
> +static struct clk_regmap toddr_b	= AUD_PCLK_GATE(toddr_b, 13);
> +static struct clk_regmap toddr_c	= AUD_PCLK_GATE(toddr_c, 14);
> +static struct clk_regmap loopback	= AUD_PCLK_GATE(loopback, 15);
> +static struct clk_regmap spdifin	= AUD_PCLK_GATE(spdifin, 16);
> +static struct clk_regmap spdifout	= AUD_PCLK_GATE(spdifout, 17);
> +static struct clk_regmap resample	= AUD_PCLK_GATE(resample, 18);
> +static struct clk_regmap power_detect	= AUD_PCLK_GATE(power_detect, 19);
> +
> +static struct clk_regmap spdifout_clk_sel =
> +	AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
> +static struct clk_regmap pdm_dclk_sel =
> +	AUD_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
> +static struct clk_regmap spdifin_clk_sel =
> +	AUD_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
> +static struct clk_regmap pdm_sysclk_sel =
> +	AUD_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
> +static struct clk_regmap spdifout_b_clk_sel =
> +	AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
> +
> +static struct clk_regmap spdifout_clk_div =
> +	AUD_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
> +static struct clk_regmap pdm_dclk_div =
> +	AUD_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
> +static struct clk_regmap spdifin_clk_div =
> +	AUD_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
> +static struct clk_regmap pdm_sysclk_div =
> +	AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
> +static struct clk_regmap spdifout_b_clk_div =
> +	AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
> +
> +static struct clk_regmap spdifout_clk =
> +	AUD_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
> +static struct clk_regmap spdifin_clk =
> +	AUD_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
> +static struct clk_regmap pdm_dclk =
> +	AUD_MST_MCLK_GATE(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
> +static struct clk_regmap pdm_sysclk =
> +	AUD_MST_MCLK_GATE(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
> +static struct clk_regmap spdifout_b_clk =
> +	AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
> +
> +static struct clk_regmap mst_a_sclk_pre_en =
> +	AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
> +static struct clk_regmap mst_b_sclk_pre_en =
> +	AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
> +static struct clk_regmap mst_c_sclk_pre_en =
> +	AUD_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0);
> +static struct clk_regmap mst_d_sclk_pre_en =
> +	AUD_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0);
> +static struct clk_regmap mst_e_sclk_pre_en =
> +	AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
> +static struct clk_regmap mst_f_sclk_pre_en =
> +	AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
> +
> +static struct clk_regmap mst_a_sclk_div =
> +	AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
> +static struct clk_regmap mst_b_sclk_div =
> +	AUD_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
> +static struct clk_regmap mst_c_sclk_div =
> +	AUD_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
> +static struct clk_regmap mst_d_sclk_div =
> +	AUD_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
> +static struct clk_regmap mst_e_sclk_div =
> +	AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
> +static struct clk_regmap mst_f_sclk_div =
> +	AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
> +
> +static struct clk_regmap mst_a_sclk_post_en =
> +	AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
> +static struct clk_regmap mst_b_sclk_post_en =
> +	AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
> +static struct clk_regmap mst_c_sclk_post_en =
> +	AUD_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0);
> +static struct clk_regmap mst_d_sclk_post_en =
> +	AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
> +static struct clk_regmap mst_e_sclk_post_en =
> +	AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
> +static struct clk_regmap mst_f_sclk_post_en =
> +	AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
> +
> +static struct clk_regmap mst_a_sclk =
> +	AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
> +static struct clk_regmap mst_b_sclk =
> +	AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
> +static struct clk_regmap mst_c_sclk =
> +	AUD_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1);
> +static struct clk_regmap mst_d_sclk =
> +	AUD_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1);
> +static struct clk_regmap mst_e_sclk =
> +	AUD_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1);
> +static struct clk_regmap mst_f_sclk =
> +	AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
> +
> +static struct clk_regmap mst_a_lrclk_div =
> +	AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
> +static struct clk_regmap mst_b_lrclk_div =
> +	AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
> +static struct clk_regmap mst_c_lrclk_div =
> +	AUD_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
> +static struct clk_regmap mst_d_lrclk_div =
> +	AUD_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
> +static struct clk_regmap mst_e_lrclk_div =
> +	AUD_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
> +static struct clk_regmap mst_f_lrclk_div =
> +	AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
> +
> +static struct clk_regmap mst_a_lrclk =
> +	AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
> +static struct clk_regmap mst_b_lrclk =
> +	AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
> +static struct clk_regmap mst_c_lrclk =
> +	AUD_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1);
> +static struct clk_regmap mst_d_lrclk =
> +	AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
> +static struct clk_regmap mst_e_lrclk =
> +	AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
> +static struct clk_regmap mst_f_lrclk =
> +	AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
> +
> +static struct clk_regmap tdmin_a_sclk_sel =
> +	AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL);
> +static struct clk_regmap tdmin_b_sclk_sel =
> +	AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL);
> +static struct clk_regmap tdmin_c_sclk_sel =
> +	AUD_TDM_SCLK_MUX(in_c, AUDIO_CLK_TDMIN_C_CTRL);
> +static struct clk_regmap tdmin_lb_sclk_sel =
> +	AUD_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
> +static struct clk_regmap tdmout_a_sclk_sel =
> +	AUD_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
> +static struct clk_regmap tdmout_b_sclk_sel =
> +	AUD_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
> +static struct clk_regmap tdmout_c_sclk_sel =
> +	AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
> +
> +static struct clk_regmap tdmin_a_sclk_pre_en =
> +	AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
> +static struct clk_regmap tdmin_b_sclk_pre_en =
> +	AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
> +static struct clk_regmap tdmin_c_sclk_pre_en =
> +	AUD_TDM_SCLK_PRE_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
> +static struct clk_regmap tdmin_lb_sclk_pre_en =
> +	AUD_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
> +static struct clk_regmap tdmout_a_sclk_pre_en =
> +	AUD_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
> +static struct clk_regmap tdmout_b_sclk_pre_en =
> +	AUD_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
> +static struct clk_regmap tdmout_c_sclk_pre_en =
> +	AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
> +
> +static struct clk_regmap tdmin_a_sclk_post_en =
> +	AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
> +static struct clk_regmap tdmin_b_sclk_post_en =
> +	AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
> +static struct clk_regmap tdmin_c_sclk_post_en =
> +	AUD_TDM_SCLK_POST_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
> +static struct clk_regmap tdmin_lb_sclk_post_en =
> +	AUD_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
> +static struct clk_regmap tdmout_a_sclk_post_en =
> +	AUD_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
> +static struct clk_regmap tdmout_b_sclk_post_en =
> +	AUD_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
> +static struct clk_regmap tdmout_c_sclk_post_en =
> +	AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
> +
> +static struct clk_regmap tdmin_a_sclk =
> +	AUD_TDM_SCLK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
> +static struct clk_regmap tdmin_b_sclk =
> +	AUD_TDM_SCLK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
> +static struct clk_regmap tdmin_c_sclk =
> +	AUD_TDM_SCLK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
> +static struct clk_regmap tdmin_lb_sclk =
> +	AUD_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
> +static struct clk_regmap tdmout_a_sclk =
> +	AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
> +static struct clk_regmap tdmout_b_sclk =
> +	AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
> +static struct clk_regmap tdmout_c_sclk =
> +	AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
> +
> +static struct clk_regmap tdmin_a_lrclk =
> +	AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
> +static struct clk_regmap tdmin_b_lrclk =
> +	AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
> +static struct clk_regmap tdmin_c_lrclk =
> +	AUD_TDM_LRLCK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
> +static struct clk_regmap tdmin_lb_lrclk =
> +	AUD_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
> +static struct clk_regmap tdmout_a_lrclk =
> +	AUD_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
> +static struct clk_regmap tdmout_b_lrclk =
> +	AUD_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
> +static struct clk_regmap tdmout_c_lrclk =
> +	AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
> +
> +/* AXG/G12A Clocks */
> +static struct clk_regmap mst_a_mclk_sel =
> +	AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
> +static struct clk_regmap mst_b_mclk_sel =
> +	AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL);
> +static struct clk_regmap mst_c_mclk_sel =
> +	AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL);
> +static struct clk_regmap mst_d_mclk_sel =
> +	AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL);
> +static struct clk_regmap mst_e_mclk_sel =
> +	AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL);
> +static struct clk_regmap mst_f_mclk_sel =
> +	AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL);
> +
> +static struct clk_regmap mst_a_mclk_div =
> +	AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL);
> +static struct clk_regmap mst_b_mclk_div =
> +	AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL);
> +static struct clk_regmap mst_c_mclk_div =
> +	AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL);
> +static struct clk_regmap mst_d_mclk_div =
> +	AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL);
> +static struct clk_regmap mst_e_mclk_div =
> +	AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL);
> +static struct clk_regmap mst_f_mclk_div =
> +	AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL);
> +
> +static struct clk_regmap mst_a_mclk =
> +	AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);
> +static struct clk_regmap mst_b_mclk =
> +	AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL);
> +static struct clk_regmap mst_c_mclk =
> +	AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL);
> +static struct clk_regmap mst_d_mclk =
> +	AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL);
> +static struct clk_regmap mst_e_mclk =
> +	AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_MCLK_E_CTRL);
> +static struct clk_regmap mst_f_mclk =
> +	AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_MCLK_F_CTRL);
> +
> +/* G12a clocks */
> +static struct clk_regmap g12a_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL(
> +	mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data);
> +static struct clk_regmap g12a_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL(
> +	mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data);
> +static struct clk_regmap g12a_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL(
> +	lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data);
> +static struct clk_regmap g12a_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL(
> +	lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data);
> +static struct clk_regmap g12a_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL(
> +	lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data);
> +static struct clk_regmap g12a_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL(
> +	sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data);
> +static struct clk_regmap g12a_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL(
> +	sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data);
> +static struct clk_regmap g12a_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
> +	sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data);
> +
> +/* G12a/SM1 clocks */
> +static struct clk_regmap spdifout_b = AUD_PCLK_GATE(spdifout_b,   21);
>  
>  /*
>   * Array of all clocks provided by this provider
> @@ -473,127 +570,127 @@ static AUD_TDM_PAD_CTRL(sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8,
>   */
>  static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
>  	.hws = {
> -		[AUD_CLKID_DDR_ARB]		= &aud_ddr_arb.hw,
> -		[AUD_CLKID_PDM]			= &aud_pdm.hw,
> -		[AUD_CLKID_TDMIN_A]		= &aud_tdmin_a.hw,
> -		[AUD_CLKID_TDMIN_B]		= &aud_tdmin_b.hw,
> -		[AUD_CLKID_TDMIN_C]		= &aud_tdmin_c.hw,
> -		[AUD_CLKID_TDMIN_LB]		= &aud_tdmin_lb.hw,
> -		[AUD_CLKID_TDMOUT_A]		= &aud_tdmout_a.hw,
> -		[AUD_CLKID_TDMOUT_B]		= &aud_tdmout_b.hw,
> -		[AUD_CLKID_TDMOUT_C]		= &aud_tdmout_c.hw,
> -		[AUD_CLKID_FRDDR_A]		= &aud_frddr_a.hw,
> -		[AUD_CLKID_FRDDR_B]		= &aud_frddr_b.hw,
> -		[AUD_CLKID_FRDDR_C]		= &aud_frddr_c.hw,
> -		[AUD_CLKID_TODDR_A]		= &aud_toddr_a.hw,
> -		[AUD_CLKID_TODDR_B]		= &aud_toddr_b.hw,
> -		[AUD_CLKID_TODDR_C]		= &aud_toddr_c.hw,
> -		[AUD_CLKID_LOOPBACK]		= &aud_loopback.hw,
> -		[AUD_CLKID_SPDIFIN]		= &aud_spdifin.hw,
> -		[AUD_CLKID_SPDIFOUT]		= &aud_spdifout.hw,
> -		[AUD_CLKID_RESAMPLE]		= &aud_resample.hw,
> -		[AUD_CLKID_POWER_DETECT]	= &aud_power_detect.hw,
> -		[AUD_CLKID_MST_A_MCLK_SEL]	= &aud_mst_a_mclk_sel.hw,
> -		[AUD_CLKID_MST_B_MCLK_SEL]	= &aud_mst_b_mclk_sel.hw,
> -		[AUD_CLKID_MST_C_MCLK_SEL]	= &aud_mst_c_mclk_sel.hw,
> -		[AUD_CLKID_MST_D_MCLK_SEL]	= &aud_mst_d_mclk_sel.hw,
> -		[AUD_CLKID_MST_E_MCLK_SEL]	= &aud_mst_e_mclk_sel.hw,
> -		[AUD_CLKID_MST_F_MCLK_SEL]	= &aud_mst_f_mclk_sel.hw,
> -		[AUD_CLKID_MST_A_MCLK_DIV]	= &aud_mst_a_mclk_div.hw,
> -		[AUD_CLKID_MST_B_MCLK_DIV]	= &aud_mst_b_mclk_div.hw,
> -		[AUD_CLKID_MST_C_MCLK_DIV]	= &aud_mst_c_mclk_div.hw,
> -		[AUD_CLKID_MST_D_MCLK_DIV]	= &aud_mst_d_mclk_div.hw,
> -		[AUD_CLKID_MST_E_MCLK_DIV]	= &aud_mst_e_mclk_div.hw,
> -		[AUD_CLKID_MST_F_MCLK_DIV]	= &aud_mst_f_mclk_div.hw,
> -		[AUD_CLKID_MST_A_MCLK]		= &aud_mst_a_mclk.hw,
> -		[AUD_CLKID_MST_B_MCLK]		= &aud_mst_b_mclk.hw,
> -		[AUD_CLKID_MST_C_MCLK]		= &aud_mst_c_mclk.hw,
> -		[AUD_CLKID_MST_D_MCLK]		= &aud_mst_d_mclk.hw,
> -		[AUD_CLKID_MST_E_MCLK]		= &aud_mst_e_mclk.hw,
> -		[AUD_CLKID_MST_F_MCLK]		= &aud_mst_f_mclk.hw,
> -		[AUD_CLKID_SPDIFOUT_CLK_SEL]	= &aud_spdifout_clk_sel.hw,
> -		[AUD_CLKID_SPDIFOUT_CLK_DIV]	= &aud_spdifout_clk_div.hw,
> -		[AUD_CLKID_SPDIFOUT_CLK]	= &aud_spdifout_clk.hw,
> -		[AUD_CLKID_SPDIFIN_CLK_SEL]	= &aud_spdifin_clk_sel.hw,
> -		[AUD_CLKID_SPDIFIN_CLK_DIV]	= &aud_spdifin_clk_div.hw,
> -		[AUD_CLKID_SPDIFIN_CLK]		= &aud_spdifin_clk.hw,
> -		[AUD_CLKID_PDM_DCLK_SEL]	= &aud_pdm_dclk_sel.hw,
> -		[AUD_CLKID_PDM_DCLK_DIV]	= &aud_pdm_dclk_div.hw,
> -		[AUD_CLKID_PDM_DCLK]		= &aud_pdm_dclk.hw,
> -		[AUD_CLKID_PDM_SYSCLK_SEL]	= &aud_pdm_sysclk_sel.hw,
> -		[AUD_CLKID_PDM_SYSCLK_DIV]	= &aud_pdm_sysclk_div.hw,
> -		[AUD_CLKID_PDM_SYSCLK]		= &aud_pdm_sysclk.hw,
> -		[AUD_CLKID_MST_A_SCLK_PRE_EN]	= &aud_mst_a_sclk_pre_en.hw,
> -		[AUD_CLKID_MST_B_SCLK_PRE_EN]	= &aud_mst_b_sclk_pre_en.hw,
> -		[AUD_CLKID_MST_C_SCLK_PRE_EN]	= &aud_mst_c_sclk_pre_en.hw,
> -		[AUD_CLKID_MST_D_SCLK_PRE_EN]	= &aud_mst_d_sclk_pre_en.hw,
> -		[AUD_CLKID_MST_E_SCLK_PRE_EN]	= &aud_mst_e_sclk_pre_en.hw,
> -		[AUD_CLKID_MST_F_SCLK_PRE_EN]	= &aud_mst_f_sclk_pre_en.hw,
> -		[AUD_CLKID_MST_A_SCLK_DIV]	= &aud_mst_a_sclk_div.hw,
> -		[AUD_CLKID_MST_B_SCLK_DIV]	= &aud_mst_b_sclk_div.hw,
> -		[AUD_CLKID_MST_C_SCLK_DIV]	= &aud_mst_c_sclk_div.hw,
> -		[AUD_CLKID_MST_D_SCLK_DIV]	= &aud_mst_d_sclk_div.hw,
> -		[AUD_CLKID_MST_E_SCLK_DIV]	= &aud_mst_e_sclk_div.hw,
> -		[AUD_CLKID_MST_F_SCLK_DIV]	= &aud_mst_f_sclk_div.hw,
> -		[AUD_CLKID_MST_A_SCLK_POST_EN]	= &aud_mst_a_sclk_post_en.hw,
> -		[AUD_CLKID_MST_B_SCLK_POST_EN]	= &aud_mst_b_sclk_post_en.hw,
> -		[AUD_CLKID_MST_C_SCLK_POST_EN]	= &aud_mst_c_sclk_post_en.hw,
> -		[AUD_CLKID_MST_D_SCLK_POST_EN]	= &aud_mst_d_sclk_post_en.hw,
> -		[AUD_CLKID_MST_E_SCLK_POST_EN]	= &aud_mst_e_sclk_post_en.hw,
> -		[AUD_CLKID_MST_F_SCLK_POST_EN]	= &aud_mst_f_sclk_post_en.hw,
> -		[AUD_CLKID_MST_A_SCLK]		= &aud_mst_a_sclk.hw,
> -		[AUD_CLKID_MST_B_SCLK]		= &aud_mst_b_sclk.hw,
> -		[AUD_CLKID_MST_C_SCLK]		= &aud_mst_c_sclk.hw,
> -		[AUD_CLKID_MST_D_SCLK]		= &aud_mst_d_sclk.hw,
> -		[AUD_CLKID_MST_E_SCLK]		= &aud_mst_e_sclk.hw,
> -		[AUD_CLKID_MST_F_SCLK]		= &aud_mst_f_sclk.hw,
> -		[AUD_CLKID_MST_A_LRCLK_DIV]	= &aud_mst_a_lrclk_div.hw,
> -		[AUD_CLKID_MST_B_LRCLK_DIV]	= &aud_mst_b_lrclk_div.hw,
> -		[AUD_CLKID_MST_C_LRCLK_DIV]	= &aud_mst_c_lrclk_div.hw,
> -		[AUD_CLKID_MST_D_LRCLK_DIV]	= &aud_mst_d_lrclk_div.hw,
> -		[AUD_CLKID_MST_E_LRCLK_DIV]	= &aud_mst_e_lrclk_div.hw,
> -		[AUD_CLKID_MST_F_LRCLK_DIV]	= &aud_mst_f_lrclk_div.hw,
> -		[AUD_CLKID_MST_A_LRCLK]		= &aud_mst_a_lrclk.hw,
> -		[AUD_CLKID_MST_B_LRCLK]		= &aud_mst_b_lrclk.hw,
> -		[AUD_CLKID_MST_C_LRCLK]		= &aud_mst_c_lrclk.hw,
> -		[AUD_CLKID_MST_D_LRCLK]		= &aud_mst_d_lrclk.hw,
> -		[AUD_CLKID_MST_E_LRCLK]		= &aud_mst_e_lrclk.hw,
> -		[AUD_CLKID_MST_F_LRCLK]		= &aud_mst_f_lrclk.hw,
> -		[AUD_CLKID_TDMIN_A_SCLK_SEL]	= &aud_tdmin_a_sclk_sel.hw,
> -		[AUD_CLKID_TDMIN_B_SCLK_SEL]	= &aud_tdmin_b_sclk_sel.hw,
> -		[AUD_CLKID_TDMIN_C_SCLK_SEL]	= &aud_tdmin_c_sclk_sel.hw,
> -		[AUD_CLKID_TDMIN_LB_SCLK_SEL]	= &aud_tdmin_lb_sclk_sel.hw,
> -		[AUD_CLKID_TDMOUT_A_SCLK_SEL]	= &aud_tdmout_a_sclk_sel.hw,
> -		[AUD_CLKID_TDMOUT_B_SCLK_SEL]	= &aud_tdmout_b_sclk_sel.hw,
> -		[AUD_CLKID_TDMOUT_C_SCLK_SEL]	= &aud_tdmout_c_sclk_sel.hw,
> -		[AUD_CLKID_TDMIN_A_SCLK_PRE_EN]	= &aud_tdmin_a_sclk_pre_en.hw,
> -		[AUD_CLKID_TDMIN_B_SCLK_PRE_EN]	= &aud_tdmin_b_sclk_pre_en.hw,
> -		[AUD_CLKID_TDMIN_C_SCLK_PRE_EN]	= &aud_tdmin_c_sclk_pre_en.hw,
> -		[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &aud_tdmin_lb_sclk_pre_en.hw,
> -		[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &aud_tdmout_a_sclk_pre_en.hw,
> -		[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &aud_tdmout_b_sclk_pre_en.hw,
> -		[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &aud_tdmout_c_sclk_pre_en.hw,
> -		[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &aud_tdmin_a_sclk_post_en.hw,
> -		[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &aud_tdmin_b_sclk_post_en.hw,
> -		[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &aud_tdmin_c_sclk_post_en.hw,
> -		[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &aud_tdmin_lb_sclk_post_en.hw,
> -		[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &aud_tdmout_a_sclk_post_en.hw,
> -		[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &aud_tdmout_b_sclk_post_en.hw,
> -		[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &aud_tdmout_c_sclk_post_en.hw,
> -		[AUD_CLKID_TDMIN_A_SCLK]	= &aud_tdmin_a_sclk.hw,
> -		[AUD_CLKID_TDMIN_B_SCLK]	= &aud_tdmin_b_sclk.hw,
> -		[AUD_CLKID_TDMIN_C_SCLK]	= &aud_tdmin_c_sclk.hw,
> -		[AUD_CLKID_TDMIN_LB_SCLK]	= &aud_tdmin_lb_sclk.hw,
> -		[AUD_CLKID_TDMOUT_A_SCLK]	= &aud_tdmout_a_sclk.hw,
> -		[AUD_CLKID_TDMOUT_B_SCLK]	= &aud_tdmout_b_sclk.hw,
> -		[AUD_CLKID_TDMOUT_C_SCLK]	= &aud_tdmout_c_sclk.hw,
> -		[AUD_CLKID_TDMIN_A_LRCLK]	= &aud_tdmin_a_lrclk.hw,
> -		[AUD_CLKID_TDMIN_B_LRCLK]	= &aud_tdmin_b_lrclk.hw,
> -		[AUD_CLKID_TDMIN_C_LRCLK]	= &aud_tdmin_c_lrclk.hw,
> -		[AUD_CLKID_TDMIN_LB_LRCLK]	= &aud_tdmin_lb_lrclk.hw,
> -		[AUD_CLKID_TDMOUT_A_LRCLK]	= &aud_tdmout_a_lrclk.hw,
> -		[AUD_CLKID_TDMOUT_B_LRCLK]	= &aud_tdmout_b_lrclk.hw,
> -		[AUD_CLKID_TDMOUT_C_LRCLK]	= &aud_tdmout_c_lrclk.hw,
> +		[AUD_CLKID_DDR_ARB]		= &ddr_arb.hw,
> +		[AUD_CLKID_PDM]			= &pdm.hw,
> +		[AUD_CLKID_TDMIN_A]		= &tdmin_a.hw,
> +		[AUD_CLKID_TDMIN_B]		= &tdmin_b.hw,
> +		[AUD_CLKID_TDMIN_C]		= &tdmin_c.hw,
> +		[AUD_CLKID_TDMIN_LB]		= &tdmin_lb.hw,
> +		[AUD_CLKID_TDMOUT_A]		= &tdmout_a.hw,
> +		[AUD_CLKID_TDMOUT_B]		= &tdmout_b.hw,
> +		[AUD_CLKID_TDMOUT_C]		= &tdmout_c.hw,
> +		[AUD_CLKID_FRDDR_A]		= &frddr_a.hw,
> +		[AUD_CLKID_FRDDR_B]		= &frddr_b.hw,
> +		[AUD_CLKID_FRDDR_C]		= &frddr_c.hw,
> +		[AUD_CLKID_TODDR_A]		= &toddr_a.hw,
> +		[AUD_CLKID_TODDR_B]		= &toddr_b.hw,
> +		[AUD_CLKID_TODDR_C]		= &toddr_c.hw,
> +		[AUD_CLKID_LOOPBACK]		= &loopback.hw,
> +		[AUD_CLKID_SPDIFIN]		= &spdifin.hw,
> +		[AUD_CLKID_SPDIFOUT]		= &spdifout.hw,
> +		[AUD_CLKID_RESAMPLE]		= &resample.hw,
> +		[AUD_CLKID_POWER_DETECT]	= &power_detect.hw,
> +		[AUD_CLKID_MST_A_MCLK_SEL]	= &mst_a_mclk_sel.hw,
> +		[AUD_CLKID_MST_B_MCLK_SEL]	= &mst_b_mclk_sel.hw,
> +		[AUD_CLKID_MST_C_MCLK_SEL]	= &mst_c_mclk_sel.hw,
> +		[AUD_CLKID_MST_D_MCLK_SEL]	= &mst_d_mclk_sel.hw,
> +		[AUD_CLKID_MST_E_MCLK_SEL]	= &mst_e_mclk_sel.hw,
> +		[AUD_CLKID_MST_F_MCLK_SEL]	= &mst_f_mclk_sel.hw,
> +		[AUD_CLKID_MST_A_MCLK_DIV]	= &mst_a_mclk_div.hw,
> +		[AUD_CLKID_MST_B_MCLK_DIV]	= &mst_b_mclk_div.hw,
> +		[AUD_CLKID_MST_C_MCLK_DIV]	= &mst_c_mclk_div.hw,
> +		[AUD_CLKID_MST_D_MCLK_DIV]	= &mst_d_mclk_div.hw,
> +		[AUD_CLKID_MST_E_MCLK_DIV]	= &mst_e_mclk_div.hw,
> +		[AUD_CLKID_MST_F_MCLK_DIV]	= &mst_f_mclk_div.hw,
> +		[AUD_CLKID_MST_A_MCLK]		= &mst_a_mclk.hw,
> +		[AUD_CLKID_MST_B_MCLK]		= &mst_b_mclk.hw,
> +		[AUD_CLKID_MST_C_MCLK]		= &mst_c_mclk.hw,
> +		[AUD_CLKID_MST_D_MCLK]		= &mst_d_mclk.hw,
> +		[AUD_CLKID_MST_E_MCLK]		= &mst_e_mclk.hw,
> +		[AUD_CLKID_MST_F_MCLK]		= &mst_f_mclk.hw,
> +		[AUD_CLKID_SPDIFOUT_CLK_SEL]	= &spdifout_clk_sel.hw,
> +		[AUD_CLKID_SPDIFOUT_CLK_DIV]	= &spdifout_clk_div.hw,
> +		[AUD_CLKID_SPDIFOUT_CLK]	= &spdifout_clk.hw,
> +		[AUD_CLKID_SPDIFIN_CLK_SEL]	= &spdifin_clk_sel.hw,
> +		[AUD_CLKID_SPDIFIN_CLK_DIV]	= &spdifin_clk_div.hw,
> +		[AUD_CLKID_SPDIFIN_CLK]		= &spdifin_clk.hw,
> +		[AUD_CLKID_PDM_DCLK_SEL]	= &pdm_dclk_sel.hw,
> +		[AUD_CLKID_PDM_DCLK_DIV]	= &pdm_dclk_div.hw,
> +		[AUD_CLKID_PDM_DCLK]		= &pdm_dclk.hw,
> +		[AUD_CLKID_PDM_SYSCLK_SEL]	= &pdm_sysclk_sel.hw,
> +		[AUD_CLKID_PDM_SYSCLK_DIV]	= &pdm_sysclk_div.hw,
> +		[AUD_CLKID_PDM_SYSCLK]		= &pdm_sysclk.hw,
> +		[AUD_CLKID_MST_A_SCLK_PRE_EN]	= &mst_a_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_B_SCLK_PRE_EN]	= &mst_b_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_C_SCLK_PRE_EN]	= &mst_c_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_D_SCLK_PRE_EN]	= &mst_d_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_E_SCLK_PRE_EN]	= &mst_e_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_F_SCLK_PRE_EN]	= &mst_f_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_A_SCLK_DIV]	= &mst_a_sclk_div.hw,
> +		[AUD_CLKID_MST_B_SCLK_DIV]	= &mst_b_sclk_div.hw,
> +		[AUD_CLKID_MST_C_SCLK_DIV]	= &mst_c_sclk_div.hw,
> +		[AUD_CLKID_MST_D_SCLK_DIV]	= &mst_d_sclk_div.hw,
> +		[AUD_CLKID_MST_E_SCLK_DIV]	= &mst_e_sclk_div.hw,
> +		[AUD_CLKID_MST_F_SCLK_DIV]	= &mst_f_sclk_div.hw,
> +		[AUD_CLKID_MST_A_SCLK_POST_EN]	= &mst_a_sclk_post_en.hw,
> +		[AUD_CLKID_MST_B_SCLK_POST_EN]	= &mst_b_sclk_post_en.hw,
> +		[AUD_CLKID_MST_C_SCLK_POST_EN]	= &mst_c_sclk_post_en.hw,
> +		[AUD_CLKID_MST_D_SCLK_POST_EN]	= &mst_d_sclk_post_en.hw,
> +		[AUD_CLKID_MST_E_SCLK_POST_EN]	= &mst_e_sclk_post_en.hw,
> +		[AUD_CLKID_MST_F_SCLK_POST_EN]	= &mst_f_sclk_post_en.hw,
> +		[AUD_CLKID_MST_A_SCLK]		= &mst_a_sclk.hw,
> +		[AUD_CLKID_MST_B_SCLK]		= &mst_b_sclk.hw,
> +		[AUD_CLKID_MST_C_SCLK]		= &mst_c_sclk.hw,
> +		[AUD_CLKID_MST_D_SCLK]		= &mst_d_sclk.hw,
> +		[AUD_CLKID_MST_E_SCLK]		= &mst_e_sclk.hw,
> +		[AUD_CLKID_MST_F_SCLK]		= &mst_f_sclk.hw,
> +		[AUD_CLKID_MST_A_LRCLK_DIV]	= &mst_a_lrclk_div.hw,
> +		[AUD_CLKID_MST_B_LRCLK_DIV]	= &mst_b_lrclk_div.hw,
> +		[AUD_CLKID_MST_C_LRCLK_DIV]	= &mst_c_lrclk_div.hw,
> +		[AUD_CLKID_MST_D_LRCLK_DIV]	= &mst_d_lrclk_div.hw,
> +		[AUD_CLKID_MST_E_LRCLK_DIV]	= &mst_e_lrclk_div.hw,
> +		[AUD_CLKID_MST_F_LRCLK_DIV]	= &mst_f_lrclk_div.hw,
> +		[AUD_CLKID_MST_A_LRCLK]		= &mst_a_lrclk.hw,
> +		[AUD_CLKID_MST_B_LRCLK]		= &mst_b_lrclk.hw,
> +		[AUD_CLKID_MST_C_LRCLK]		= &mst_c_lrclk.hw,
> +		[AUD_CLKID_MST_D_LRCLK]		= &mst_d_lrclk.hw,
> +		[AUD_CLKID_MST_E_LRCLK]		= &mst_e_lrclk.hw,
> +		[AUD_CLKID_MST_F_LRCLK]		= &mst_f_lrclk.hw,
> +		[AUD_CLKID_TDMIN_A_SCLK_SEL]	= &tdmin_a_sclk_sel.hw,
> +		[AUD_CLKID_TDMIN_B_SCLK_SEL]	= &tdmin_b_sclk_sel.hw,
> +		[AUD_CLKID_TDMIN_C_SCLK_SEL]	= &tdmin_c_sclk_sel.hw,
> +		[AUD_CLKID_TDMIN_LB_SCLK_SEL]	= &tdmin_lb_sclk_sel.hw,
> +		[AUD_CLKID_TDMOUT_A_SCLK_SEL]	= &tdmout_a_sclk_sel.hw,
> +		[AUD_CLKID_TDMOUT_B_SCLK_SEL]	= &tdmout_b_sclk_sel.hw,
> +		[AUD_CLKID_TDMOUT_C_SCLK_SEL]	= &tdmout_c_sclk_sel.hw,
> +		[AUD_CLKID_TDMIN_A_SCLK_PRE_EN]	= &tdmin_a_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMIN_B_SCLK_PRE_EN]	= &tdmin_b_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMIN_C_SCLK_PRE_EN]	= &tdmin_c_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
> +		[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
> +		[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
> +		[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
> +		[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
> +		[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
> +		[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
> +		[AUD_CLKID_TDMIN_A_SCLK]	= &tdmin_a_sclk.hw,
> +		[AUD_CLKID_TDMIN_B_SCLK]	= &tdmin_b_sclk.hw,
> +		[AUD_CLKID_TDMIN_C_SCLK]	= &tdmin_c_sclk.hw,
> +		[AUD_CLKID_TDMIN_LB_SCLK]	= &tdmin_lb_sclk.hw,
> +		[AUD_CLKID_TDMOUT_A_SCLK]	= &tdmout_a_sclk.hw,
> +		[AUD_CLKID_TDMOUT_B_SCLK]	= &tdmout_b_sclk.hw,
> +		[AUD_CLKID_TDMOUT_C_SCLK]	= &tdmout_c_sclk.hw,
> +		[AUD_CLKID_TDMIN_A_LRCLK]	= &tdmin_a_lrclk.hw,
> +		[AUD_CLKID_TDMIN_B_LRCLK]	= &tdmin_b_lrclk.hw,
> +		[AUD_CLKID_TDMIN_C_LRCLK]	= &tdmin_c_lrclk.hw,
> +		[AUD_CLKID_TDMIN_LB_LRCLK]	= &tdmin_lb_lrclk.hw,
> +		[AUD_CLKID_TDMOUT_A_LRCLK]	= &tdmout_a_lrclk.hw,
> +		[AUD_CLKID_TDMOUT_B_LRCLK]	= &tdmout_b_lrclk.hw,
> +		[AUD_CLKID_TDMOUT_C_LRCLK]	= &tdmout_c_lrclk.hw,
>  		[NR_CLKS] = NULL,
>  	},
>  	.num = NR_CLKS,
> @@ -605,139 +702,139 @@ static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
>   */
>  static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
>  	.hws = {
> -		[AUD_CLKID_DDR_ARB]		= &aud_ddr_arb.hw,
> -		[AUD_CLKID_PDM]			= &aud_pdm.hw,
> -		[AUD_CLKID_TDMIN_A]		= &aud_tdmin_a.hw,
> -		[AUD_CLKID_TDMIN_B]		= &aud_tdmin_b.hw,
> -		[AUD_CLKID_TDMIN_C]		= &aud_tdmin_c.hw,
> -		[AUD_CLKID_TDMIN_LB]		= &aud_tdmin_lb.hw,
> -		[AUD_CLKID_TDMOUT_A]		= &aud_tdmout_a.hw,
> -		[AUD_CLKID_TDMOUT_B]		= &aud_tdmout_b.hw,
> -		[AUD_CLKID_TDMOUT_C]		= &aud_tdmout_c.hw,
> -		[AUD_CLKID_FRDDR_A]		= &aud_frddr_a.hw,
> -		[AUD_CLKID_FRDDR_B]		= &aud_frddr_b.hw,
> -		[AUD_CLKID_FRDDR_C]		= &aud_frddr_c.hw,
> -		[AUD_CLKID_TODDR_A]		= &aud_toddr_a.hw,
> -		[AUD_CLKID_TODDR_B]		= &aud_toddr_b.hw,
> -		[AUD_CLKID_TODDR_C]		= &aud_toddr_c.hw,
> -		[AUD_CLKID_LOOPBACK]		= &aud_loopback.hw,
> -		[AUD_CLKID_SPDIFIN]		= &aud_spdifin.hw,
> -		[AUD_CLKID_SPDIFOUT]		= &aud_spdifout.hw,
> -		[AUD_CLKID_RESAMPLE]		= &aud_resample.hw,
> -		[AUD_CLKID_POWER_DETECT]	= &aud_power_detect.hw,
> -		[AUD_CLKID_SPDIFOUT_B]		= &aud_spdifout_b.hw,
> -		[AUD_CLKID_MST_A_MCLK_SEL]	= &aud_mst_a_mclk_sel.hw,
> -		[AUD_CLKID_MST_B_MCLK_SEL]	= &aud_mst_b_mclk_sel.hw,
> -		[AUD_CLKID_MST_C_MCLK_SEL]	= &aud_mst_c_mclk_sel.hw,
> -		[AUD_CLKID_MST_D_MCLK_SEL]	= &aud_mst_d_mclk_sel.hw,
> -		[AUD_CLKID_MST_E_MCLK_SEL]	= &aud_mst_e_mclk_sel.hw,
> -		[AUD_CLKID_MST_F_MCLK_SEL]	= &aud_mst_f_mclk_sel.hw,
> -		[AUD_CLKID_MST_A_MCLK_DIV]	= &aud_mst_a_mclk_div.hw,
> -		[AUD_CLKID_MST_B_MCLK_DIV]	= &aud_mst_b_mclk_div.hw,
> -		[AUD_CLKID_MST_C_MCLK_DIV]	= &aud_mst_c_mclk_div.hw,
> -		[AUD_CLKID_MST_D_MCLK_DIV]	= &aud_mst_d_mclk_div.hw,
> -		[AUD_CLKID_MST_E_MCLK_DIV]	= &aud_mst_e_mclk_div.hw,
> -		[AUD_CLKID_MST_F_MCLK_DIV]	= &aud_mst_f_mclk_div.hw,
> -		[AUD_CLKID_MST_A_MCLK]		= &aud_mst_a_mclk.hw,
> -		[AUD_CLKID_MST_B_MCLK]		= &aud_mst_b_mclk.hw,
> -		[AUD_CLKID_MST_C_MCLK]		= &aud_mst_c_mclk.hw,
> -		[AUD_CLKID_MST_D_MCLK]		= &aud_mst_d_mclk.hw,
> -		[AUD_CLKID_MST_E_MCLK]		= &aud_mst_e_mclk.hw,
> -		[AUD_CLKID_MST_F_MCLK]		= &aud_mst_f_mclk.hw,
> -		[AUD_CLKID_SPDIFOUT_CLK_SEL]	= &aud_spdifout_clk_sel.hw,
> -		[AUD_CLKID_SPDIFOUT_CLK_DIV]	= &aud_spdifout_clk_div.hw,
> -		[AUD_CLKID_SPDIFOUT_CLK]	= &aud_spdifout_clk.hw,
> -		[AUD_CLKID_SPDIFOUT_B_CLK_SEL]	= &aud_spdifout_b_clk_sel.hw,
> -		[AUD_CLKID_SPDIFOUT_B_CLK_DIV]	= &aud_spdifout_b_clk_div.hw,
> -		[AUD_CLKID_SPDIFOUT_B_CLK]	= &aud_spdifout_b_clk.hw,
> -		[AUD_CLKID_SPDIFIN_CLK_SEL]	= &aud_spdifin_clk_sel.hw,
> -		[AUD_CLKID_SPDIFIN_CLK_DIV]	= &aud_spdifin_clk_div.hw,
> -		[AUD_CLKID_SPDIFIN_CLK]		= &aud_spdifin_clk.hw,
> -		[AUD_CLKID_PDM_DCLK_SEL]	= &aud_pdm_dclk_sel.hw,
> -		[AUD_CLKID_PDM_DCLK_DIV]	= &aud_pdm_dclk_div.hw,
> -		[AUD_CLKID_PDM_DCLK]		= &aud_pdm_dclk.hw,
> -		[AUD_CLKID_PDM_SYSCLK_SEL]	= &aud_pdm_sysclk_sel.hw,
> -		[AUD_CLKID_PDM_SYSCLK_DIV]	= &aud_pdm_sysclk_div.hw,
> -		[AUD_CLKID_PDM_SYSCLK]		= &aud_pdm_sysclk.hw,
> -		[AUD_CLKID_MST_A_SCLK_PRE_EN]	= &aud_mst_a_sclk_pre_en.hw,
> -		[AUD_CLKID_MST_B_SCLK_PRE_EN]	= &aud_mst_b_sclk_pre_en.hw,
> -		[AUD_CLKID_MST_C_SCLK_PRE_EN]	= &aud_mst_c_sclk_pre_en.hw,
> -		[AUD_CLKID_MST_D_SCLK_PRE_EN]	= &aud_mst_d_sclk_pre_en.hw,
> -		[AUD_CLKID_MST_E_SCLK_PRE_EN]	= &aud_mst_e_sclk_pre_en.hw,
> -		[AUD_CLKID_MST_F_SCLK_PRE_EN]	= &aud_mst_f_sclk_pre_en.hw,
> -		[AUD_CLKID_MST_A_SCLK_DIV]	= &aud_mst_a_sclk_div.hw,
> -		[AUD_CLKID_MST_B_SCLK_DIV]	= &aud_mst_b_sclk_div.hw,
> -		[AUD_CLKID_MST_C_SCLK_DIV]	= &aud_mst_c_sclk_div.hw,
> -		[AUD_CLKID_MST_D_SCLK_DIV]	= &aud_mst_d_sclk_div.hw,
> -		[AUD_CLKID_MST_E_SCLK_DIV]	= &aud_mst_e_sclk_div.hw,
> -		[AUD_CLKID_MST_F_SCLK_DIV]	= &aud_mst_f_sclk_div.hw,
> -		[AUD_CLKID_MST_A_SCLK_POST_EN]	= &aud_mst_a_sclk_post_en.hw,
> -		[AUD_CLKID_MST_B_SCLK_POST_EN]	= &aud_mst_b_sclk_post_en.hw,
> -		[AUD_CLKID_MST_C_SCLK_POST_EN]	= &aud_mst_c_sclk_post_en.hw,
> -		[AUD_CLKID_MST_D_SCLK_POST_EN]	= &aud_mst_d_sclk_post_en.hw,
> -		[AUD_CLKID_MST_E_SCLK_POST_EN]	= &aud_mst_e_sclk_post_en.hw,
> -		[AUD_CLKID_MST_F_SCLK_POST_EN]	= &aud_mst_f_sclk_post_en.hw,
> -		[AUD_CLKID_MST_A_SCLK]		= &aud_mst_a_sclk.hw,
> -		[AUD_CLKID_MST_B_SCLK]		= &aud_mst_b_sclk.hw,
> -		[AUD_CLKID_MST_C_SCLK]		= &aud_mst_c_sclk.hw,
> -		[AUD_CLKID_MST_D_SCLK]		= &aud_mst_d_sclk.hw,
> -		[AUD_CLKID_MST_E_SCLK]		= &aud_mst_e_sclk.hw,
> -		[AUD_CLKID_MST_F_SCLK]		= &aud_mst_f_sclk.hw,
> -		[AUD_CLKID_MST_A_LRCLK_DIV]	= &aud_mst_a_lrclk_div.hw,
> -		[AUD_CLKID_MST_B_LRCLK_DIV]	= &aud_mst_b_lrclk_div.hw,
> -		[AUD_CLKID_MST_C_LRCLK_DIV]	= &aud_mst_c_lrclk_div.hw,
> -		[AUD_CLKID_MST_D_LRCLK_DIV]	= &aud_mst_d_lrclk_div.hw,
> -		[AUD_CLKID_MST_E_LRCLK_DIV]	= &aud_mst_e_lrclk_div.hw,
> -		[AUD_CLKID_MST_F_LRCLK_DIV]	= &aud_mst_f_lrclk_div.hw,
> -		[AUD_CLKID_MST_A_LRCLK]		= &aud_mst_a_lrclk.hw,
> -		[AUD_CLKID_MST_B_LRCLK]		= &aud_mst_b_lrclk.hw,
> -		[AUD_CLKID_MST_C_LRCLK]		= &aud_mst_c_lrclk.hw,
> -		[AUD_CLKID_MST_D_LRCLK]		= &aud_mst_d_lrclk.hw,
> -		[AUD_CLKID_MST_E_LRCLK]		= &aud_mst_e_lrclk.hw,
> -		[AUD_CLKID_MST_F_LRCLK]		= &aud_mst_f_lrclk.hw,
> -		[AUD_CLKID_TDMIN_A_SCLK_SEL]	= &aud_tdmin_a_sclk_sel.hw,
> -		[AUD_CLKID_TDMIN_B_SCLK_SEL]	= &aud_tdmin_b_sclk_sel.hw,
> -		[AUD_CLKID_TDMIN_C_SCLK_SEL]	= &aud_tdmin_c_sclk_sel.hw,
> -		[AUD_CLKID_TDMIN_LB_SCLK_SEL]	= &aud_tdmin_lb_sclk_sel.hw,
> -		[AUD_CLKID_TDMOUT_A_SCLK_SEL]	= &aud_tdmout_a_sclk_sel.hw,
> -		[AUD_CLKID_TDMOUT_B_SCLK_SEL]	= &aud_tdmout_b_sclk_sel.hw,
> -		[AUD_CLKID_TDMOUT_C_SCLK_SEL]	= &aud_tdmout_c_sclk_sel.hw,
> -		[AUD_CLKID_TDMIN_A_SCLK_PRE_EN]	= &aud_tdmin_a_sclk_pre_en.hw,
> -		[AUD_CLKID_TDMIN_B_SCLK_PRE_EN]	= &aud_tdmin_b_sclk_pre_en.hw,
> -		[AUD_CLKID_TDMIN_C_SCLK_PRE_EN]	= &aud_tdmin_c_sclk_pre_en.hw,
> -		[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &aud_tdmin_lb_sclk_pre_en.hw,
> -		[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &aud_tdmout_a_sclk_pre_en.hw,
> -		[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &aud_tdmout_b_sclk_pre_en.hw,
> -		[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &aud_tdmout_c_sclk_pre_en.hw,
> -		[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &aud_tdmin_a_sclk_post_en.hw,
> -		[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &aud_tdmin_b_sclk_post_en.hw,
> -		[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &aud_tdmin_c_sclk_post_en.hw,
> -		[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &aud_tdmin_lb_sclk_post_en.hw,
> -		[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &aud_tdmout_a_sclk_post_en.hw,
> -		[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &aud_tdmout_b_sclk_post_en.hw,
> -		[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &aud_tdmout_c_sclk_post_en.hw,
> -		[AUD_CLKID_TDMIN_A_SCLK]	= &aud_tdmin_a_sclk.hw,
> -		[AUD_CLKID_TDMIN_B_SCLK]	= &aud_tdmin_b_sclk.hw,
> -		[AUD_CLKID_TDMIN_C_SCLK]	= &aud_tdmin_c_sclk.hw,
> -		[AUD_CLKID_TDMIN_LB_SCLK]	= &aud_tdmin_lb_sclk.hw,
> -		[AUD_CLKID_TDMOUT_A_SCLK]	= &aud_tdmout_a_sclk.hw,
> -		[AUD_CLKID_TDMOUT_B_SCLK]	= &aud_tdmout_b_sclk.hw,
> -		[AUD_CLKID_TDMOUT_C_SCLK]	= &aud_tdmout_c_sclk.hw,
> -		[AUD_CLKID_TDMIN_A_LRCLK]	= &aud_tdmin_a_lrclk.hw,
> -		[AUD_CLKID_TDMIN_B_LRCLK]	= &aud_tdmin_b_lrclk.hw,
> -		[AUD_CLKID_TDMIN_C_LRCLK]	= &aud_tdmin_c_lrclk.hw,
> -		[AUD_CLKID_TDMIN_LB_LRCLK]	= &aud_tdmin_lb_lrclk.hw,
> -		[AUD_CLKID_TDMOUT_A_LRCLK]	= &aud_tdmout_a_lrclk.hw,
> -		[AUD_CLKID_TDMOUT_B_LRCLK]	= &aud_tdmout_b_lrclk.hw,
> -		[AUD_CLKID_TDMOUT_C_LRCLK]	= &aud_tdmout_c_lrclk.hw,
> -		[AUD_CLKID_TDM_MCLK_PAD0]	= &aud_tdm_mclk_pad_0.hw,
> -		[AUD_CLKID_TDM_MCLK_PAD1]	= &aud_tdm_mclk_pad_1.hw,
> -		[AUD_CLKID_TDM_LRCLK_PAD0]	= &aud_tdm_lrclk_pad_0.hw,
> -		[AUD_CLKID_TDM_LRCLK_PAD1]	= &aud_tdm_lrclk_pad_1.hw,
> -		[AUD_CLKID_TDM_LRCLK_PAD2]	= &aud_tdm_lrclk_pad_2.hw,
> -		[AUD_CLKID_TDM_SCLK_PAD0]	= &aud_tdm_sclk_pad_0.hw,
> -		[AUD_CLKID_TDM_SCLK_PAD1]	= &aud_tdm_sclk_pad_1.hw,
> -		[AUD_CLKID_TDM_SCLK_PAD2]	= &aud_tdm_sclk_pad_2.hw,
> +		[AUD_CLKID_DDR_ARB]		= &ddr_arb.hw,
> +		[AUD_CLKID_PDM]			= &pdm.hw,
> +		[AUD_CLKID_TDMIN_A]		= &tdmin_a.hw,
> +		[AUD_CLKID_TDMIN_B]		= &tdmin_b.hw,
> +		[AUD_CLKID_TDMIN_C]		= &tdmin_c.hw,
> +		[AUD_CLKID_TDMIN_LB]		= &tdmin_lb.hw,
> +		[AUD_CLKID_TDMOUT_A]		= &tdmout_a.hw,
> +		[AUD_CLKID_TDMOUT_B]		= &tdmout_b.hw,
> +		[AUD_CLKID_TDMOUT_C]		= &tdmout_c.hw,
> +		[AUD_CLKID_FRDDR_A]		= &frddr_a.hw,
> +		[AUD_CLKID_FRDDR_B]		= &frddr_b.hw,
> +		[AUD_CLKID_FRDDR_C]		= &frddr_c.hw,
> +		[AUD_CLKID_TODDR_A]		= &toddr_a.hw,
> +		[AUD_CLKID_TODDR_B]		= &toddr_b.hw,
> +		[AUD_CLKID_TODDR_C]		= &toddr_c.hw,
> +		[AUD_CLKID_LOOPBACK]		= &loopback.hw,
> +		[AUD_CLKID_SPDIFIN]		= &spdifin.hw,
> +		[AUD_CLKID_SPDIFOUT]		= &spdifout.hw,
> +		[AUD_CLKID_RESAMPLE]		= &resample.hw,
> +		[AUD_CLKID_POWER_DETECT]	= &power_detect.hw,
> +		[AUD_CLKID_SPDIFOUT_B]		= &spdifout_b.hw,
> +		[AUD_CLKID_MST_A_MCLK_SEL]	= &mst_a_mclk_sel.hw,
> +		[AUD_CLKID_MST_B_MCLK_SEL]	= &mst_b_mclk_sel.hw,
> +		[AUD_CLKID_MST_C_MCLK_SEL]	= &mst_c_mclk_sel.hw,
> +		[AUD_CLKID_MST_D_MCLK_SEL]	= &mst_d_mclk_sel.hw,
> +		[AUD_CLKID_MST_E_MCLK_SEL]	= &mst_e_mclk_sel.hw,
> +		[AUD_CLKID_MST_F_MCLK_SEL]	= &mst_f_mclk_sel.hw,
> +		[AUD_CLKID_MST_A_MCLK_DIV]	= &mst_a_mclk_div.hw,
> +		[AUD_CLKID_MST_B_MCLK_DIV]	= &mst_b_mclk_div.hw,
> +		[AUD_CLKID_MST_C_MCLK_DIV]	= &mst_c_mclk_div.hw,
> +		[AUD_CLKID_MST_D_MCLK_DIV]	= &mst_d_mclk_div.hw,
> +		[AUD_CLKID_MST_E_MCLK_DIV]	= &mst_e_mclk_div.hw,
> +		[AUD_CLKID_MST_F_MCLK_DIV]	= &mst_f_mclk_div.hw,
> +		[AUD_CLKID_MST_A_MCLK]		= &mst_a_mclk.hw,
> +		[AUD_CLKID_MST_B_MCLK]		= &mst_b_mclk.hw,
> +		[AUD_CLKID_MST_C_MCLK]		= &mst_c_mclk.hw,
> +		[AUD_CLKID_MST_D_MCLK]		= &mst_d_mclk.hw,
> +		[AUD_CLKID_MST_E_MCLK]		= &mst_e_mclk.hw,
> +		[AUD_CLKID_MST_F_MCLK]		= &mst_f_mclk.hw,
> +		[AUD_CLKID_SPDIFOUT_CLK_SEL]	= &spdifout_clk_sel.hw,
> +		[AUD_CLKID_SPDIFOUT_CLK_DIV]	= &spdifout_clk_div.hw,
> +		[AUD_CLKID_SPDIFOUT_CLK]	= &spdifout_clk.hw,
> +		[AUD_CLKID_SPDIFOUT_B_CLK_SEL]	= &spdifout_b_clk_sel.hw,
> +		[AUD_CLKID_SPDIFOUT_B_CLK_DIV]	= &spdifout_b_clk_div.hw,
> +		[AUD_CLKID_SPDIFOUT_B_CLK]	= &spdifout_b_clk.hw,
> +		[AUD_CLKID_SPDIFIN_CLK_SEL]	= &spdifin_clk_sel.hw,
> +		[AUD_CLKID_SPDIFIN_CLK_DIV]	= &spdifin_clk_div.hw,
> +		[AUD_CLKID_SPDIFIN_CLK]		= &spdifin_clk.hw,
> +		[AUD_CLKID_PDM_DCLK_SEL]	= &pdm_dclk_sel.hw,
> +		[AUD_CLKID_PDM_DCLK_DIV]	= &pdm_dclk_div.hw,
> +		[AUD_CLKID_PDM_DCLK]		= &pdm_dclk.hw,
> +		[AUD_CLKID_PDM_SYSCLK_SEL]	= &pdm_sysclk_sel.hw,
> +		[AUD_CLKID_PDM_SYSCLK_DIV]	= &pdm_sysclk_div.hw,
> +		[AUD_CLKID_PDM_SYSCLK]		= &pdm_sysclk.hw,
> +		[AUD_CLKID_MST_A_SCLK_PRE_EN]	= &mst_a_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_B_SCLK_PRE_EN]	= &mst_b_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_C_SCLK_PRE_EN]	= &mst_c_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_D_SCLK_PRE_EN]	= &mst_d_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_E_SCLK_PRE_EN]	= &mst_e_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_F_SCLK_PRE_EN]	= &mst_f_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_A_SCLK_DIV]	= &mst_a_sclk_div.hw,
> +		[AUD_CLKID_MST_B_SCLK_DIV]	= &mst_b_sclk_div.hw,
> +		[AUD_CLKID_MST_C_SCLK_DIV]	= &mst_c_sclk_div.hw,
> +		[AUD_CLKID_MST_D_SCLK_DIV]	= &mst_d_sclk_div.hw,
> +		[AUD_CLKID_MST_E_SCLK_DIV]	= &mst_e_sclk_div.hw,
> +		[AUD_CLKID_MST_F_SCLK_DIV]	= &mst_f_sclk_div.hw,
> +		[AUD_CLKID_MST_A_SCLK_POST_EN]	= &mst_a_sclk_post_en.hw,
> +		[AUD_CLKID_MST_B_SCLK_POST_EN]	= &mst_b_sclk_post_en.hw,
> +		[AUD_CLKID_MST_C_SCLK_POST_EN]	= &mst_c_sclk_post_en.hw,
> +		[AUD_CLKID_MST_D_SCLK_POST_EN]	= &mst_d_sclk_post_en.hw,
> +		[AUD_CLKID_MST_E_SCLK_POST_EN]	= &mst_e_sclk_post_en.hw,
> +		[AUD_CLKID_MST_F_SCLK_POST_EN]	= &mst_f_sclk_post_en.hw,
> +		[AUD_CLKID_MST_A_SCLK]		= &mst_a_sclk.hw,
> +		[AUD_CLKID_MST_B_SCLK]		= &mst_b_sclk.hw,
> +		[AUD_CLKID_MST_C_SCLK]		= &mst_c_sclk.hw,
> +		[AUD_CLKID_MST_D_SCLK]		= &mst_d_sclk.hw,
> +		[AUD_CLKID_MST_E_SCLK]		= &mst_e_sclk.hw,
> +		[AUD_CLKID_MST_F_SCLK]		= &mst_f_sclk.hw,
> +		[AUD_CLKID_MST_A_LRCLK_DIV]	= &mst_a_lrclk_div.hw,
> +		[AUD_CLKID_MST_B_LRCLK_DIV]	= &mst_b_lrclk_div.hw,
> +		[AUD_CLKID_MST_C_LRCLK_DIV]	= &mst_c_lrclk_div.hw,
> +		[AUD_CLKID_MST_D_LRCLK_DIV]	= &mst_d_lrclk_div.hw,
> +		[AUD_CLKID_MST_E_LRCLK_DIV]	= &mst_e_lrclk_div.hw,
> +		[AUD_CLKID_MST_F_LRCLK_DIV]	= &mst_f_lrclk_div.hw,
> +		[AUD_CLKID_MST_A_LRCLK]		= &mst_a_lrclk.hw,
> +		[AUD_CLKID_MST_B_LRCLK]		= &mst_b_lrclk.hw,
> +		[AUD_CLKID_MST_C_LRCLK]		= &mst_c_lrclk.hw,
> +		[AUD_CLKID_MST_D_LRCLK]		= &mst_d_lrclk.hw,
> +		[AUD_CLKID_MST_E_LRCLK]		= &mst_e_lrclk.hw,
> +		[AUD_CLKID_MST_F_LRCLK]		= &mst_f_lrclk.hw,
> +		[AUD_CLKID_TDMIN_A_SCLK_SEL]	= &tdmin_a_sclk_sel.hw,
> +		[AUD_CLKID_TDMIN_B_SCLK_SEL]	= &tdmin_b_sclk_sel.hw,
> +		[AUD_CLKID_TDMIN_C_SCLK_SEL]	= &tdmin_c_sclk_sel.hw,
> +		[AUD_CLKID_TDMIN_LB_SCLK_SEL]	= &tdmin_lb_sclk_sel.hw,
> +		[AUD_CLKID_TDMOUT_A_SCLK_SEL]	= &tdmout_a_sclk_sel.hw,
> +		[AUD_CLKID_TDMOUT_B_SCLK_SEL]	= &tdmout_b_sclk_sel.hw,
> +		[AUD_CLKID_TDMOUT_C_SCLK_SEL]	= &tdmout_c_sclk_sel.hw,
> +		[AUD_CLKID_TDMIN_A_SCLK_PRE_EN]	= &tdmin_a_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMIN_B_SCLK_PRE_EN]	= &tdmin_b_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMIN_C_SCLK_PRE_EN]	= &tdmin_c_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
> +		[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
> +		[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
> +		[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
> +		[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
> +		[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
> +		[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
> +		[AUD_CLKID_TDMIN_A_SCLK]	= &tdmin_a_sclk.hw,
> +		[AUD_CLKID_TDMIN_B_SCLK]	= &tdmin_b_sclk.hw,
> +		[AUD_CLKID_TDMIN_C_SCLK]	= &tdmin_c_sclk.hw,
> +		[AUD_CLKID_TDMIN_LB_SCLK]	= &tdmin_lb_sclk.hw,
> +		[AUD_CLKID_TDMOUT_A_SCLK]	= &tdmout_a_sclk.hw,
> +		[AUD_CLKID_TDMOUT_B_SCLK]	= &tdmout_b_sclk.hw,
> +		[AUD_CLKID_TDMOUT_C_SCLK]	= &tdmout_c_sclk.hw,
> +		[AUD_CLKID_TDMIN_A_LRCLK]	= &tdmin_a_lrclk.hw,
> +		[AUD_CLKID_TDMIN_B_LRCLK]	= &tdmin_b_lrclk.hw,
> +		[AUD_CLKID_TDMIN_C_LRCLK]	= &tdmin_c_lrclk.hw,
> +		[AUD_CLKID_TDMIN_LB_LRCLK]	= &tdmin_lb_lrclk.hw,
> +		[AUD_CLKID_TDMOUT_A_LRCLK]	= &tdmout_a_lrclk.hw,
> +		[AUD_CLKID_TDMOUT_B_LRCLK]	= &tdmout_b_lrclk.hw,
> +		[AUD_CLKID_TDMOUT_C_LRCLK]	= &tdmout_c_lrclk.hw,
> +		[AUD_CLKID_TDM_MCLK_PAD0]	= &g12a_tdm_mclk_pad_0.hw,
> +		[AUD_CLKID_TDM_MCLK_PAD1]	= &g12a_tdm_mclk_pad_1.hw,
> +		[AUD_CLKID_TDM_LRCLK_PAD0]	= &g12a_tdm_lrclk_pad_0.hw,
> +		[AUD_CLKID_TDM_LRCLK_PAD1]	= &g12a_tdm_lrclk_pad_1.hw,
> +		[AUD_CLKID_TDM_LRCLK_PAD2]	= &g12a_tdm_lrclk_pad_2.hw,
> +		[AUD_CLKID_TDM_SCLK_PAD0]	= &g12a_tdm_sclk_pad_0.hw,
> +		[AUD_CLKID_TDM_SCLK_PAD1]	= &g12a_tdm_sclk_pad_1.hw,
> +		[AUD_CLKID_TDM_SCLK_PAD2]	= &g12a_tdm_sclk_pad_2.hw,
>  		[NR_CLKS] = NULL,
>  	},
>  	.num = NR_CLKS,
> @@ -750,139 +847,139 @@ static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
>   * feel the need to have separate AXG/G12A regmap tables.
>   */
>  static struct clk_regmap *const aud_clk_regmaps[] = {
> -	&aud_ddr_arb,
> -	&aud_pdm,
> -	&aud_tdmin_a,
> -	&aud_tdmin_b,
> -	&aud_tdmin_c,
> -	&aud_tdmin_lb,
> -	&aud_tdmout_a,
> -	&aud_tdmout_b,
> -	&aud_tdmout_c,
> -	&aud_frddr_a,
> -	&aud_frddr_b,
> -	&aud_frddr_c,
> -	&aud_toddr_a,
> -	&aud_toddr_b,
> -	&aud_toddr_c,
> -	&aud_loopback,
> -	&aud_spdifin,
> -	&aud_spdifout,
> -	&aud_resample,
> -	&aud_power_detect,
> -	&aud_spdifout_b,
> -	&aud_mst_a_mclk_sel,
> -	&aud_mst_b_mclk_sel,
> -	&aud_mst_c_mclk_sel,
> -	&aud_mst_d_mclk_sel,
> -	&aud_mst_e_mclk_sel,
> -	&aud_mst_f_mclk_sel,
> -	&aud_mst_a_mclk_div,
> -	&aud_mst_b_mclk_div,
> -	&aud_mst_c_mclk_div,
> -	&aud_mst_d_mclk_div,
> -	&aud_mst_e_mclk_div,
> -	&aud_mst_f_mclk_div,
> -	&aud_mst_a_mclk,
> -	&aud_mst_b_mclk,
> -	&aud_mst_c_mclk,
> -	&aud_mst_d_mclk,
> -	&aud_mst_e_mclk,
> -	&aud_mst_f_mclk,
> -	&aud_spdifout_clk_sel,
> -	&aud_spdifout_clk_div,
> -	&aud_spdifout_clk,
> -	&aud_spdifin_clk_sel,
> -	&aud_spdifin_clk_div,
> -	&aud_spdifin_clk,
> -	&aud_pdm_dclk_sel,
> -	&aud_pdm_dclk_div,
> -	&aud_pdm_dclk,
> -	&aud_pdm_sysclk_sel,
> -	&aud_pdm_sysclk_div,
> -	&aud_pdm_sysclk,
> -	&aud_mst_a_sclk_pre_en,
> -	&aud_mst_b_sclk_pre_en,
> -	&aud_mst_c_sclk_pre_en,
> -	&aud_mst_d_sclk_pre_en,
> -	&aud_mst_e_sclk_pre_en,
> -	&aud_mst_f_sclk_pre_en,
> -	&aud_mst_a_sclk_div,
> -	&aud_mst_b_sclk_div,
> -	&aud_mst_c_sclk_div,
> -	&aud_mst_d_sclk_div,
> -	&aud_mst_e_sclk_div,
> -	&aud_mst_f_sclk_div,
> -	&aud_mst_a_sclk_post_en,
> -	&aud_mst_b_sclk_post_en,
> -	&aud_mst_c_sclk_post_en,
> -	&aud_mst_d_sclk_post_en,
> -	&aud_mst_e_sclk_post_en,
> -	&aud_mst_f_sclk_post_en,
> -	&aud_mst_a_sclk,
> -	&aud_mst_b_sclk,
> -	&aud_mst_c_sclk,
> -	&aud_mst_d_sclk,
> -	&aud_mst_e_sclk,
> -	&aud_mst_f_sclk,
> -	&aud_mst_a_lrclk_div,
> -	&aud_mst_b_lrclk_div,
> -	&aud_mst_c_lrclk_div,
> -	&aud_mst_d_lrclk_div,
> -	&aud_mst_e_lrclk_div,
> -	&aud_mst_f_lrclk_div,
> -	&aud_mst_a_lrclk,
> -	&aud_mst_b_lrclk,
> -	&aud_mst_c_lrclk,
> -	&aud_mst_d_lrclk,
> -	&aud_mst_e_lrclk,
> -	&aud_mst_f_lrclk,
> -	&aud_tdmin_a_sclk_sel,
> -	&aud_tdmin_b_sclk_sel,
> -	&aud_tdmin_c_sclk_sel,
> -	&aud_tdmin_lb_sclk_sel,
> -	&aud_tdmout_a_sclk_sel,
> -	&aud_tdmout_b_sclk_sel,
> -	&aud_tdmout_c_sclk_sel,
> -	&aud_tdmin_a_sclk_pre_en,
> -	&aud_tdmin_b_sclk_pre_en,
> -	&aud_tdmin_c_sclk_pre_en,
> -	&aud_tdmin_lb_sclk_pre_en,
> -	&aud_tdmout_a_sclk_pre_en,
> -	&aud_tdmout_b_sclk_pre_en,
> -	&aud_tdmout_c_sclk_pre_en,
> -	&aud_tdmin_a_sclk_post_en,
> -	&aud_tdmin_b_sclk_post_en,
> -	&aud_tdmin_c_sclk_post_en,
> -	&aud_tdmin_lb_sclk_post_en,
> -	&aud_tdmout_a_sclk_post_en,
> -	&aud_tdmout_b_sclk_post_en,
> -	&aud_tdmout_c_sclk_post_en,
> -	&aud_tdmin_a_sclk,
> -	&aud_tdmin_b_sclk,
> -	&aud_tdmin_c_sclk,
> -	&aud_tdmin_lb_sclk,
> -	&aud_tdmout_a_sclk,
> -	&aud_tdmout_b_sclk,
> -	&aud_tdmout_c_sclk,
> -	&aud_tdmin_a_lrclk,
> -	&aud_tdmin_b_lrclk,
> -	&aud_tdmin_c_lrclk,
> -	&aud_tdmin_lb_lrclk,
> -	&aud_tdmout_a_lrclk,
> -	&aud_tdmout_b_lrclk,
> -	&aud_tdmout_c_lrclk,
> -	&aud_spdifout_b_clk_sel,
> -	&aud_spdifout_b_clk_div,
> -	&aud_spdifout_b_clk,
> -	&aud_tdm_mclk_pad_0,
> -	&aud_tdm_mclk_pad_1,
> -	&aud_tdm_lrclk_pad_0,
> -	&aud_tdm_lrclk_pad_1,
> -	&aud_tdm_lrclk_pad_2,
> -	&aud_tdm_sclk_pad_0,
> -	&aud_tdm_sclk_pad_1,
> -	&aud_tdm_sclk_pad_2,
> +	&ddr_arb,
> +	&pdm,
> +	&tdmin_a,
> +	&tdmin_b,
> +	&tdmin_c,
> +	&tdmin_lb,
> +	&tdmout_a,
> +	&tdmout_b,
> +	&tdmout_c,
> +	&frddr_a,
> +	&frddr_b,
> +	&frddr_c,
> +	&toddr_a,
> +	&toddr_b,
> +	&toddr_c,
> +	&loopback,
> +	&spdifin,
> +	&spdifout,
> +	&resample,
> +	&power_detect,
> +	&spdifout_b,
> +	&mst_a_mclk_sel,
> +	&mst_b_mclk_sel,
> +	&mst_c_mclk_sel,
> +	&mst_d_mclk_sel,
> +	&mst_e_mclk_sel,
> +	&mst_f_mclk_sel,
> +	&mst_a_mclk_div,
> +	&mst_b_mclk_div,
> +	&mst_c_mclk_div,
> +	&mst_d_mclk_div,
> +	&mst_e_mclk_div,
> +	&mst_f_mclk_div,
> +	&mst_a_mclk,
> +	&mst_b_mclk,
> +	&mst_c_mclk,
> +	&mst_d_mclk,
> +	&mst_e_mclk,
> +	&mst_f_mclk,
> +	&spdifout_clk_sel,
> +	&spdifout_clk_div,
> +	&spdifout_clk,
> +	&spdifin_clk_sel,
> +	&spdifin_clk_div,
> +	&spdifin_clk,
> +	&pdm_dclk_sel,
> +	&pdm_dclk_div,
> +	&pdm_dclk,
> +	&pdm_sysclk_sel,
> +	&pdm_sysclk_div,
> +	&pdm_sysclk,
> +	&mst_a_sclk_pre_en,
> +	&mst_b_sclk_pre_en,
> +	&mst_c_sclk_pre_en,
> +	&mst_d_sclk_pre_en,
> +	&mst_e_sclk_pre_en,
> +	&mst_f_sclk_pre_en,
> +	&mst_a_sclk_div,
> +	&mst_b_sclk_div,
> +	&mst_c_sclk_div,
> +	&mst_d_sclk_div,
> +	&mst_e_sclk_div,
> +	&mst_f_sclk_div,
> +	&mst_a_sclk_post_en,
> +	&mst_b_sclk_post_en,
> +	&mst_c_sclk_post_en,
> +	&mst_d_sclk_post_en,
> +	&mst_e_sclk_post_en,
> +	&mst_f_sclk_post_en,
> +	&mst_a_sclk,
> +	&mst_b_sclk,
> +	&mst_c_sclk,
> +	&mst_d_sclk,
> +	&mst_e_sclk,
> +	&mst_f_sclk,
> +	&mst_a_lrclk_div,
> +	&mst_b_lrclk_div,
> +	&mst_c_lrclk_div,
> +	&mst_d_lrclk_div,
> +	&mst_e_lrclk_div,
> +	&mst_f_lrclk_div,
> +	&mst_a_lrclk,
> +	&mst_b_lrclk,
> +	&mst_c_lrclk,
> +	&mst_d_lrclk,
> +	&mst_e_lrclk,
> +	&mst_f_lrclk,
> +	&tdmin_a_sclk_sel,
> +	&tdmin_b_sclk_sel,
> +	&tdmin_c_sclk_sel,
> +	&tdmin_lb_sclk_sel,
> +	&tdmout_a_sclk_sel,
> +	&tdmout_b_sclk_sel,
> +	&tdmout_c_sclk_sel,
> +	&tdmin_a_sclk_pre_en,
> +	&tdmin_b_sclk_pre_en,
> +	&tdmin_c_sclk_pre_en,
> +	&tdmin_lb_sclk_pre_en,
> +	&tdmout_a_sclk_pre_en,
> +	&tdmout_b_sclk_pre_en,
> +	&tdmout_c_sclk_pre_en,
> +	&tdmin_a_sclk_post_en,
> +	&tdmin_b_sclk_post_en,
> +	&tdmin_c_sclk_post_en,
> +	&tdmin_lb_sclk_post_en,
> +	&tdmout_a_sclk_post_en,
> +	&tdmout_b_sclk_post_en,
> +	&tdmout_c_sclk_post_en,
> +	&tdmin_a_sclk,
> +	&tdmin_b_sclk,
> +	&tdmin_c_sclk,
> +	&tdmin_lb_sclk,
> +	&tdmout_a_sclk,
> +	&tdmout_b_sclk,
> +	&tdmout_c_sclk,
> +	&tdmin_a_lrclk,
> +	&tdmin_b_lrclk,
> +	&tdmin_c_lrclk,
> +	&tdmin_lb_lrclk,
> +	&tdmout_a_lrclk,
> +	&tdmout_b_lrclk,
> +	&tdmout_c_lrclk,
> +	&spdifout_b_clk_sel,
> +	&spdifout_b_clk_div,
> +	&spdifout_b_clk,
> +	&g12a_tdm_mclk_pad_0,
> +	&g12a_tdm_mclk_pad_1,
> +	&g12a_tdm_lrclk_pad_0,
> +	&g12a_tdm_lrclk_pad_1,
> +	&g12a_tdm_lrclk_pad_2,
> +	&g12a_tdm_sclk_pad_0,
> +	&g12a_tdm_sclk_pad_1,
> +	&g12a_tdm_sclk_pad_2,
>  };
>  
>  static int devm_clk_get_enable(struct device *dev, char *id)
> 

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 6/7] clk: meson: axg-audio: provide clk top signal name
  2019-09-24 15:33 ` [PATCH 6/7] clk: meson: axg-audio: provide clk top signal name Jerome Brunet
@ 2019-09-27  9:14   ` Neil Armstrong
  2019-09-27  9:37     ` Neil Armstrong
  0 siblings, 1 reply; 19+ messages in thread
From: Neil Armstrong @ 2019-09-27  9:14 UTC (permalink / raw)
  To: Jerome Brunet; +Cc: Kevin Hilman, linux-amlogic, linux-clk, linux-kernel

On 24/09/2019 17:33, Jerome Brunet wrote:
> The peripheral clock on the sm1 goes through some muxes
> and dividers before reaching the audio gates. To model that,
> without repeating our self too much, the "top" clock signal
> is introduced and will serve as a the parent of the gates.
> 
> On the axg and g12a, the top clock is just a pass-through to
> the audio peripheral clock provided by the main controller.
> 
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
>  drivers/clk/meson/axg-audio.c | 19 ++++++++++++++++---
>  drivers/clk/meson/axg-audio.h |  3 ++-
>  2 files changed, 18 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
> index ce8836776d1c..a8ccdbaecae2 100644
> --- a/drivers/clk/meson/axg-audio.c
> +++ b/drivers/clk/meson/axg-audio.c
> @@ -74,9 +74,7 @@
>  	.hw.init = &(struct clk_init_data) {				\
>  		.name = "aud_"#_name,					\
>  		.ops = &clk_regmap_gate_ops,				\
> -		.parent_data = &(const struct clk_parent_data) {	\
> -			.fw_name = "pclk",				\
> -		},							\
> +		.parent_names = (const char *[]){ "aud_top" },		\
>  		.num_parents = 1,					\
>  	},								\
>  }
> @@ -504,6 +502,19 @@ static struct clk_regmap tdmout_c_lrclk =
>  	AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
>  
>  /* AXG/G12A Clocks */
> +
> +static struct clk_hw axg_aud_top = {
> +	.init = &(struct clk_init_data) {
> +		/* Provide aud_top signal name on axg and g12a */
> +		.name = "aud_top",
> +		.ops = &(const struct clk_ops) {},
> +		.parent_data = &(const struct clk_parent_data) {
> +			.fw_name = "pclk",
> +		},
> +		.num_parents = 1,
> +	},
> +};
> +
>  static struct clk_regmap mst_a_mclk_sel =
>  	AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
>  static struct clk_regmap mst_b_mclk_sel =
> @@ -691,6 +702,7 @@ static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
>  		[AUD_CLKID_TDMOUT_A_LRCLK]	= &tdmout_a_lrclk.hw,
>  		[AUD_CLKID_TDMOUT_B_LRCLK]	= &tdmout_b_lrclk.hw,
>  		[AUD_CLKID_TDMOUT_C_LRCLK]	= &tdmout_c_lrclk.hw,
> +		[AUD_CLKID_TOP]			= &axg_aud_top,
>  		[NR_CLKS] = NULL,
>  	},
>  	.num = NR_CLKS,
> @@ -835,6 +847,7 @@ static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
>  		[AUD_CLKID_TDM_SCLK_PAD0]	= &g12a_tdm_sclk_pad_0.hw,
>  		[AUD_CLKID_TDM_SCLK_PAD1]	= &g12a_tdm_sclk_pad_1.hw,
>  		[AUD_CLKID_TDM_SCLK_PAD2]	= &g12a_tdm_sclk_pad_2.hw,
> +		[AUD_CLKID_TOP]			= &axg_aud_top,
>  		[NR_CLKS] = NULL,
>  	},
>  	.num = NR_CLKS,
> diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h
> index c00e28b2e1a9..a4956837f597 100644
> --- a/drivers/clk/meson/axg-audio.h
> +++ b/drivers/clk/meson/axg-audio.h
> @@ -116,9 +116,10 @@
>  #define AUD_CLKID_SPDIFOUT_B_CLK_SEL	153
>  #define AUD_CLKID_SPDIFOUT_B_CLK_DIV	154
>  
> +

AUD_CLKID_TOP seems to be missing here


>  /* include the CLKIDs which are part of the DT bindings */
>  #include <dt-bindings/clock/axg-audio-clkc.h>
>  
> -#define NR_CLKS	163
> +#define NR_CLKS	164
>  
>  #endif /*__AXG_AUDIO_CLKC_H */
> 


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 7/7] clk: meson: axg_audio: add sm1 support
  2019-09-24 15:33 ` [PATCH 7/7] clk: meson: axg_audio: add sm1 support Jerome Brunet
@ 2019-09-27  9:36   ` Neil Armstrong
  2019-09-27 14:01     ` Jerome Brunet
  0 siblings, 1 reply; 19+ messages in thread
From: Neil Armstrong @ 2019-09-27  9:36 UTC (permalink / raw)
  To: Jerome Brunet; +Cc: Kevin Hilman, linux-amlogic, linux-clk, linux-kernel

On 24/09/2019 17:33, Jerome Brunet wrote:
> Add sm1 support the axg audio clock controllers. This new version is
> indeed derived from the previous generation, as always, adding a few
> new clocks to the mix.
> 
> The number of gates now exceeds 32 and do not fit in a single register.
> Unfortunately, designers chose to introduce the new gate register
> immediately after the original one, at the beginning of the register
> space, shifting all the master clock register offsets.
> 
> The sm1 also introduce a few mux and divider on the top clock path,
> possibly to lower the peripheral clocks of the audio blocks if
> necessary.
> 
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
>  drivers/clk/meson/axg-audio.c | 583 ++++++++++++++++++++++++++++++++--
>  drivers/clk/meson/axg-audio.h |  22 +-
>  2 files changed, 574 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
> index a8ccdbaecae2..88046a5e26b7 100644
> --- a/drivers/clk/meson/axg-audio.c
> +++ b/drivers/clk/meson/axg-audio.c
> @@ -66,9 +66,9 @@
>  	},								\
>  }
>  
> -#define AUD_PCLK_GATE(_name, _bit) {					\
> +#define AUD_PCLK_GATE(_name, _reg, _bit) {				\
>  	.data = &(struct clk_regmap_gate_data){				\
> -		.offset = (AUDIO_CLK_GATE_EN),				\
> +		.offset = (_reg),					\
>  		.bit_idx = (_bit),					\
>  	},								\
>  	.hw.init = &(struct clk_init_data) {				\
> @@ -290,30 +290,50 @@ static const struct clk_parent_data lrclk_pad_ctrl_parent_data[] = {
>  };
>  
>  #define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents)		\
> -	AUD_MUX(tdm_##_name, _reg, 0x7, _shift, 0, _parents,	\
> +	AUD_MUX(_name, _reg, 0x7, _shift, 0, _parents,		\
>  		CLK_SET_RATE_NO_REPARENT)
>  
>  /* Common Clocks */
> -static struct clk_regmap ddr_arb	= AUD_PCLK_GATE(ddr_arb, 0);
> -static struct clk_regmap pdm		= AUD_PCLK_GATE(pdm, 1);
> -static struct clk_regmap tdmin_a	= AUD_PCLK_GATE(tdmin_a, 2);
> -static struct clk_regmap tdmin_b	= AUD_PCLK_GATE(tdmin_b, 3);
> -static struct clk_regmap tdmin_c	= AUD_PCLK_GATE(tdmin_c, 4);
> -static struct clk_regmap tdmin_lb	= AUD_PCLK_GATE(tdmin_lb, 5);
> -static struct clk_regmap tdmout_a	= AUD_PCLK_GATE(tdmout_a, 6);
> -static struct clk_regmap tdmout_b	= AUD_PCLK_GATE(tdmout_b, 7);
> -static struct clk_regmap tdmout_c	= AUD_PCLK_GATE(tdmout_c, 8);
> -static struct clk_regmap frddr_a	= AUD_PCLK_GATE(frddr_a, 9);
> -static struct clk_regmap frddr_b	= AUD_PCLK_GATE(frddr_b, 10);
> -static struct clk_regmap frddr_c	= AUD_PCLK_GATE(frddr_c, 11);
> -static struct clk_regmap toddr_a	= AUD_PCLK_GATE(toddr_a, 12);
> -static struct clk_regmap toddr_b	= AUD_PCLK_GATE(toddr_b, 13);
> -static struct clk_regmap toddr_c	= AUD_PCLK_GATE(toddr_c, 14);
> -static struct clk_regmap loopback	= AUD_PCLK_GATE(loopback, 15);
> -static struct clk_regmap spdifin	= AUD_PCLK_GATE(spdifin, 16);
> -static struct clk_regmap spdifout	= AUD_PCLK_GATE(spdifout, 17);
> -static struct clk_regmap resample	= AUD_PCLK_GATE(resample, 18);
> -static struct clk_regmap power_detect	= AUD_PCLK_GATE(power_detect, 19);
> +static struct clk_regmap ddr_arb =
> +	AUD_PCLK_GATE(ddr_arb, AUDIO_CLK_GATE_EN, 0);
> +static struct clk_regmap pdm =
> +	AUD_PCLK_GATE(pdm, AUDIO_CLK_GATE_EN, 1);
> +static struct clk_regmap tdmin_a =
> +	AUD_PCLK_GATE(tdmin_a, AUDIO_CLK_GATE_EN, 2);
> +static struct clk_regmap tdmin_b =
> +	AUD_PCLK_GATE(tdmin_b, AUDIO_CLK_GATE_EN, 3);
> +static struct clk_regmap tdmin_c =
> +	AUD_PCLK_GATE(tdmin_c, AUDIO_CLK_GATE_EN, 4);
> +static struct clk_regmap tdmin_lb =
> +	AUD_PCLK_GATE(tdmin_lb, AUDIO_CLK_GATE_EN, 5);
> +static struct clk_regmap tdmout_a =
> +	AUD_PCLK_GATE(tdmout_a, AUDIO_CLK_GATE_EN, 6);
> +static struct clk_regmap tdmout_b =
> +	AUD_PCLK_GATE(tdmout_b, AUDIO_CLK_GATE_EN, 7);
> +static struct clk_regmap tdmout_c =
> +	AUD_PCLK_GATE(tdmout_c, AUDIO_CLK_GATE_EN, 8);
> +static struct clk_regmap frddr_a =
> +	AUD_PCLK_GATE(frddr_a, AUDIO_CLK_GATE_EN, 9);
> +static struct clk_regmap frddr_b =
> +	AUD_PCLK_GATE(frddr_b, AUDIO_CLK_GATE_EN, 10);
> +static struct clk_regmap frddr_c =
> +	AUD_PCLK_GATE(frddr_c, AUDIO_CLK_GATE_EN, 11);
> +static struct clk_regmap toddr_a =
> +	AUD_PCLK_GATE(toddr_a, AUDIO_CLK_GATE_EN, 12);
> +static struct clk_regmap toddr_b =
> +	AUD_PCLK_GATE(toddr_b, AUDIO_CLK_GATE_EN, 13);
> +static struct clk_regmap toddr_c =
> +	AUD_PCLK_GATE(toddr_c, AUDIO_CLK_GATE_EN, 14);
> +static struct clk_regmap loopback =
> +	AUD_PCLK_GATE(loopback, AUDIO_CLK_GATE_EN, 15);
> +static struct clk_regmap spdifin =
> +	AUD_PCLK_GATE(spdifin, AUDIO_CLK_GATE_EN, 16);
> +static struct clk_regmap spdifout =
> +	AUD_PCLK_GATE(spdifout, AUDIO_CLK_GATE_EN, 17);
> +static struct clk_regmap resample =
> +	AUD_PCLK_GATE(resample, AUDIO_CLK_GATE_EN, 18);
> +static struct clk_regmap power_detect =
> +	AUD_PCLK_GATE(power_detect, AUDIO_CLK_GATE_EN, 19);
>  
>  static struct clk_regmap spdifout_clk_sel =
>  	AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
> @@ -502,7 +522,6 @@ static struct clk_regmap tdmout_c_lrclk =
>  	AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
>  
>  /* AXG/G12A Clocks */
> -

Spurious line remove

>  static struct clk_hw axg_aud_top = {
>  	.init = &(struct clk_init_data) {
>  		/* Provide aud_top signal name on axg and g12a */
> @@ -573,7 +592,185 @@ static struct clk_regmap g12a_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
>  	sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data);
>  
>  /* G12a/SM1 clocks */
> -static struct clk_regmap spdifout_b = AUD_PCLK_GATE(spdifout_b,   21);
> +static struct clk_regmap toram =
> +	AUD_PCLK_GATE(toram, AUDIO_CLK_GATE_EN, 20);
> +static struct clk_regmap spdifout_b =
> +	AUD_PCLK_GATE(spdifout_b, AUDIO_CLK_GATE_EN, 21);
> +static struct clk_regmap eqdrc =
> +	AUD_PCLK_GATE(eqdrc, AUDIO_CLK_GATE_EN, 22);
> +
> +/* SM1 Clocks */
> +static struct clk_regmap sm1_clk81_en = {
> +	.data = &(struct clk_regmap_gate_data){
> +		.offset = AUDIO_CLK81_EN,
> +		.bit_idx = 31,
> +	},
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "aud_clk81_en",
> +		.ops = &(const struct clk_ops) {},
> +		.parent_data = &(const struct clk_parent_data) {
> +			.fw_name = "pclk",
> +		},
> +		.num_parents = 1,
> +	},
> +};
> +
> +static struct clk_regmap sm1_sysclk_a_div = {
> +	.data = &(struct clk_regmap_div_data){
> +		.offset = AUDIO_CLK81_CTRL,
> +		.shift = 0,
> +		.width = 8,
> +	},
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "aud_sysclk_a_div",
> +		.ops = &clk_regmap_divider_ops,
> +		.parent_hws = (const struct clk_hw *[]) {
> +			&sm1_clk81_en.hw,
> +		},
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static struct clk_regmap sm1_sysclk_a_en = {
> +	.data = &(struct clk_regmap_gate_data){
> +		.offset = AUDIO_CLK81_CTRL,
> +		.bit_idx = 8,
> +	},
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "aud_sysclk_a_en",
> +		.ops = &(const struct clk_ops) {},
> +		.parent_hws = (const struct clk_hw *[]) {
> +			&sm1_sysclk_a_div.hw,
> +		},
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static struct clk_regmap sm1_sysclk_b_div = {
> +	.data = &(struct clk_regmap_div_data){
> +		.offset = AUDIO_CLK81_CTRL,
> +		.shift = 16,
> +		.width = 8,
> +	},
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "aud_sysclk_b_div",
> +		.ops = &clk_regmap_divider_ops,
> +		.parent_hws = (const struct clk_hw *[]) {
> +			&sm1_clk81_en.hw,
> +		},
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static struct clk_regmap sm1_sysclk_b_en = {
> +	.data = &(struct clk_regmap_gate_data){
> +		.offset = AUDIO_CLK81_CTRL,
> +		.bit_idx = 24,
> +	},
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "aud_sysclk_b_en",
> +		.ops = &(const struct clk_ops) {},
> +		.parent_hws = (const struct clk_hw *[]) {
> +			&sm1_sysclk_b_div.hw,
> +		},
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static const struct clk_hw *sm1_aud_top_parents[] = {
> +	&sm1_sysclk_a_en.hw,
> +	&sm1_sysclk_b_en.hw,
> +};
> +
> +static struct clk_regmap sm1_aud_top = {
> +	.data = &(struct clk_regmap_mux_data){
> +		.offset = AUDIO_CLK81_CTRL,
> +		.mask = 0x1,
> +		.shift = 31,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "aud_top",
> +		.ops = &clk_regmap_mux_ops,
> +		.parent_hws = sm1_aud_top_parents,
> +		.num_parents = ARRAY_SIZE(sm1_aud_top_parents),
> +		.flags = CLK_SET_RATE_NO_REPARENT,
> +	},
> +};
> +
> +static struct clk_regmap resample_b =
> +	AUD_PCLK_GATE(resample_b, AUDIO_CLK_GATE_EN, 26);
> +static struct clk_regmap tovad =
> +	AUD_PCLK_GATE(tovad, AUDIO_CLK_GATE_EN, 27);
> +static struct clk_regmap locker =
> +	AUD_PCLK_GATE(locker, AUDIO_CLK_GATE_EN, 28);
> +static struct clk_regmap spdifin_lb =
> +	AUD_PCLK_GATE(spdifin_lb, AUDIO_CLK_GATE_EN, 29);
> +static struct clk_regmap frddr_d =
> +	AUD_PCLK_GATE(frddr_d, AUDIO_CLK_GATE_EN1, 0);
> +static struct clk_regmap toddr_d =
> +	AUD_PCLK_GATE(toddr_d, AUDIO_CLK_GATE_EN1, 1);
> +static struct clk_regmap loopback_b =
> +	AUD_PCLK_GATE(loopback_b, AUDIO_CLK_GATE_EN1, 2);
> +
> +static struct clk_regmap sm1_mst_a_mclk_sel =
> +	AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
> +static struct clk_regmap sm1_mst_b_mclk_sel =
> +	AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
> +static struct clk_regmap sm1_mst_c_mclk_sel =
> +	AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
> +static struct clk_regmap sm1_mst_d_mclk_sel =
> +	AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
> +static struct clk_regmap sm1_mst_e_mclk_sel =
> +	AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
> +static struct clk_regmap sm1_mst_f_mclk_sel =
> +	AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
> +
> +static struct clk_regmap sm1_mst_a_mclk_div =
> +	AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
> +static struct clk_regmap sm1_mst_b_mclk_div =
> +	AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
> +static struct clk_regmap sm1_mst_c_mclk_div =
> +	AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
> +static struct clk_regmap sm1_mst_d_mclk_div =
> +	AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
> +static struct clk_regmap sm1_mst_e_mclk_div =
> +	AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
> +static struct clk_regmap sm1_mst_f_mclk_div =
> +	AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
> +
> +static struct clk_regmap sm1_mst_a_mclk =
> +	AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
> +static struct clk_regmap sm1_mst_b_mclk =
> +	AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
> +static struct clk_regmap sm1_mst_c_mclk =
> +	AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
> +static struct clk_regmap sm1_mst_d_mclk =
> +	AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
> +static struct clk_regmap sm1_mst_e_mclk =
> +	AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
> +static struct clk_regmap sm1_mst_f_mclk =
> +	AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
> +
> +static struct clk_regmap sm1_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL(
> +	tdm_mclk_pad_0, AUDIO_SM1_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data);
> +static struct clk_regmap sm1_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL(
> +	tdm_mclk_pad_1, AUDIO_SM1_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data);
> +static struct clk_regmap sm1_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL(
> +	tdm_lrclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data);
> +static struct clk_regmap sm1_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL(
> +	tdm_lrclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data);
> +static struct clk_regmap sm1_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL(
> +	tdm_lrclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data);
> +static struct clk_regmap sm1_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL(
> +	tdm_sclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data);
> +static struct clk_regmap sm1_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL(
> +	tdm_sclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data);
> +static struct clk_regmap sm1_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
> +	tdm_sclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data);
>  
>  /*
>   * Array of all clocks provided by this provider
> @@ -853,13 +1050,172 @@ static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
>  	.num = NR_CLKS,
>  };
>  
> +/*
> + * Array of all SM1 clocks provided by this provider
> + * The input clocks of the controller will be populated at runtime
> + */
> +static struct clk_hw_onecell_data sm1_audio_hw_onecell_data = {
> +	.hws = {
> +		[AUD_CLKID_DDR_ARB]		= &ddr_arb.hw,
> +		[AUD_CLKID_PDM]			= &pdm.hw,
> +		[AUD_CLKID_TDMIN_A]		= &tdmin_a.hw,
> +		[AUD_CLKID_TDMIN_B]		= &tdmin_b.hw,
> +		[AUD_CLKID_TDMIN_C]		= &tdmin_c.hw,
> +		[AUD_CLKID_TDMIN_LB]		= &tdmin_lb.hw,
> +		[AUD_CLKID_TDMOUT_A]		= &tdmout_a.hw,
> +		[AUD_CLKID_TDMOUT_B]		= &tdmout_b.hw,
> +		[AUD_CLKID_TDMOUT_C]		= &tdmout_c.hw,
> +		[AUD_CLKID_FRDDR_A]		= &frddr_a.hw,
> +		[AUD_CLKID_FRDDR_B]		= &frddr_b.hw,
> +		[AUD_CLKID_FRDDR_C]		= &frddr_c.hw,
> +		[AUD_CLKID_TODDR_A]		= &toddr_a.hw,
> +		[AUD_CLKID_TODDR_B]		= &toddr_b.hw,
> +		[AUD_CLKID_TODDR_C]		= &toddr_c.hw,
> +		[AUD_CLKID_LOOPBACK]		= &loopback.hw,
> +		[AUD_CLKID_SPDIFIN]		= &spdifin.hw,
> +		[AUD_CLKID_SPDIFOUT]		= &spdifout.hw,
> +		[AUD_CLKID_RESAMPLE]		= &resample.hw,
> +		[AUD_CLKID_SPDIFOUT_B]		= &spdifout_b.hw,
> +		[AUD_CLKID_MST_A_MCLK_SEL]	= &sm1_mst_a_mclk_sel.hw,
> +		[AUD_CLKID_MST_B_MCLK_SEL]	= &sm1_mst_b_mclk_sel.hw,
> +		[AUD_CLKID_MST_C_MCLK_SEL]	= &sm1_mst_c_mclk_sel.hw,
> +		[AUD_CLKID_MST_D_MCLK_SEL]	= &sm1_mst_d_mclk_sel.hw,
> +		[AUD_CLKID_MST_E_MCLK_SEL]	= &sm1_mst_e_mclk_sel.hw,
> +		[AUD_CLKID_MST_F_MCLK_SEL]	= &sm1_mst_f_mclk_sel.hw,
> +		[AUD_CLKID_MST_A_MCLK_DIV]	= &sm1_mst_a_mclk_div.hw,
> +		[AUD_CLKID_MST_B_MCLK_DIV]	= &sm1_mst_b_mclk_div.hw,
> +		[AUD_CLKID_MST_C_MCLK_DIV]	= &sm1_mst_c_mclk_div.hw,
> +		[AUD_CLKID_MST_D_MCLK_DIV]	= &sm1_mst_d_mclk_div.hw,
> +		[AUD_CLKID_MST_E_MCLK_DIV]	= &sm1_mst_e_mclk_div.hw,
> +		[AUD_CLKID_MST_F_MCLK_DIV]	= &sm1_mst_f_mclk_div.hw,
> +		[AUD_CLKID_MST_A_MCLK]		= &sm1_mst_a_mclk.hw,
> +		[AUD_CLKID_MST_B_MCLK]		= &sm1_mst_b_mclk.hw,
> +		[AUD_CLKID_MST_C_MCLK]		= &sm1_mst_c_mclk.hw,
> +		[AUD_CLKID_MST_D_MCLK]		= &sm1_mst_d_mclk.hw,
> +		[AUD_CLKID_MST_E_MCLK]		= &sm1_mst_e_mclk.hw,
> +		[AUD_CLKID_MST_F_MCLK]		= &sm1_mst_f_mclk.hw,
> +		[AUD_CLKID_SPDIFOUT_CLK_SEL]	= &spdifout_clk_sel.hw,
> +		[AUD_CLKID_SPDIFOUT_CLK_DIV]	= &spdifout_clk_div.hw,
> +		[AUD_CLKID_SPDIFOUT_CLK]	= &spdifout_clk.hw,
> +		[AUD_CLKID_SPDIFOUT_B_CLK_SEL]	= &spdifout_b_clk_sel.hw,
> +		[AUD_CLKID_SPDIFOUT_B_CLK_DIV]	= &spdifout_b_clk_div.hw,
> +		[AUD_CLKID_SPDIFOUT_B_CLK]	= &spdifout_b_clk.hw,
> +		[AUD_CLKID_SPDIFIN_CLK_SEL]	= &spdifin_clk_sel.hw,
> +		[AUD_CLKID_SPDIFIN_CLK_DIV]	= &spdifin_clk_div.hw,
> +		[AUD_CLKID_SPDIFIN_CLK]		= &spdifin_clk.hw,
> +		[AUD_CLKID_PDM_DCLK_SEL]	= &pdm_dclk_sel.hw,
> +		[AUD_CLKID_PDM_DCLK_DIV]	= &pdm_dclk_div.hw,
> +		[AUD_CLKID_PDM_DCLK]		= &pdm_dclk.hw,
> +		[AUD_CLKID_PDM_SYSCLK_SEL]	= &pdm_sysclk_sel.hw,
> +		[AUD_CLKID_PDM_SYSCLK_DIV]	= &pdm_sysclk_div.hw,
> +		[AUD_CLKID_PDM_SYSCLK]		= &pdm_sysclk.hw,
> +		[AUD_CLKID_MST_A_SCLK_PRE_EN]	= &mst_a_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_B_SCLK_PRE_EN]	= &mst_b_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_C_SCLK_PRE_EN]	= &mst_c_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_D_SCLK_PRE_EN]	= &mst_d_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_E_SCLK_PRE_EN]	= &mst_e_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_F_SCLK_PRE_EN]	= &mst_f_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_A_SCLK_DIV]	= &mst_a_sclk_div.hw,
> +		[AUD_CLKID_MST_B_SCLK_DIV]	= &mst_b_sclk_div.hw,
> +		[AUD_CLKID_MST_C_SCLK_DIV]	= &mst_c_sclk_div.hw,
> +		[AUD_CLKID_MST_D_SCLK_DIV]	= &mst_d_sclk_div.hw,
> +		[AUD_CLKID_MST_E_SCLK_DIV]	= &mst_e_sclk_div.hw,
> +		[AUD_CLKID_MST_F_SCLK_DIV]	= &mst_f_sclk_div.hw,
> +		[AUD_CLKID_MST_A_SCLK_POST_EN]	= &mst_a_sclk_post_en.hw,
> +		[AUD_CLKID_MST_B_SCLK_POST_EN]	= &mst_b_sclk_post_en.hw,
> +		[AUD_CLKID_MST_C_SCLK_POST_EN]	= &mst_c_sclk_post_en.hw,
> +		[AUD_CLKID_MST_D_SCLK_POST_EN]	= &mst_d_sclk_post_en.hw,
> +		[AUD_CLKID_MST_E_SCLK_POST_EN]	= &mst_e_sclk_post_en.hw,
> +		[AUD_CLKID_MST_F_SCLK_POST_EN]	= &mst_f_sclk_post_en.hw,
> +		[AUD_CLKID_MST_A_SCLK]		= &mst_a_sclk.hw,
> +		[AUD_CLKID_MST_B_SCLK]		= &mst_b_sclk.hw,
> +		[AUD_CLKID_MST_C_SCLK]		= &mst_c_sclk.hw,
> +		[AUD_CLKID_MST_D_SCLK]		= &mst_d_sclk.hw,
> +		[AUD_CLKID_MST_E_SCLK]		= &mst_e_sclk.hw,
> +		[AUD_CLKID_MST_F_SCLK]		= &mst_f_sclk.hw,
> +		[AUD_CLKID_MST_A_LRCLK_DIV]	= &mst_a_lrclk_div.hw,
> +		[AUD_CLKID_MST_B_LRCLK_DIV]	= &mst_b_lrclk_div.hw,
> +		[AUD_CLKID_MST_C_LRCLK_DIV]	= &mst_c_lrclk_div.hw,
> +		[AUD_CLKID_MST_D_LRCLK_DIV]	= &mst_d_lrclk_div.hw,
> +		[AUD_CLKID_MST_E_LRCLK_DIV]	= &mst_e_lrclk_div.hw,
> +		[AUD_CLKID_MST_F_LRCLK_DIV]	= &mst_f_lrclk_div.hw,
> +		[AUD_CLKID_MST_A_LRCLK]		= &mst_a_lrclk.hw,
> +		[AUD_CLKID_MST_B_LRCLK]		= &mst_b_lrclk.hw,
> +		[AUD_CLKID_MST_C_LRCLK]		= &mst_c_lrclk.hw,
> +		[AUD_CLKID_MST_D_LRCLK]		= &mst_d_lrclk.hw,
> +		[AUD_CLKID_MST_E_LRCLK]		= &mst_e_lrclk.hw,
> +		[AUD_CLKID_MST_F_LRCLK]		= &mst_f_lrclk.hw,
> +		[AUD_CLKID_TDMIN_A_SCLK_SEL]	= &tdmin_a_sclk_sel.hw,
> +		[AUD_CLKID_TDMIN_B_SCLK_SEL]	= &tdmin_b_sclk_sel.hw,
> +		[AUD_CLKID_TDMIN_C_SCLK_SEL]	= &tdmin_c_sclk_sel.hw,
> +		[AUD_CLKID_TDMIN_LB_SCLK_SEL]	= &tdmin_lb_sclk_sel.hw,
> +		[AUD_CLKID_TDMOUT_A_SCLK_SEL]	= &tdmout_a_sclk_sel.hw,
> +		[AUD_CLKID_TDMOUT_B_SCLK_SEL]	= &tdmout_b_sclk_sel.hw,
> +		[AUD_CLKID_TDMOUT_C_SCLK_SEL]	= &tdmout_c_sclk_sel.hw,
> +		[AUD_CLKID_TDMIN_A_SCLK_PRE_EN]	= &tdmin_a_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMIN_B_SCLK_PRE_EN]	= &tdmin_b_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMIN_C_SCLK_PRE_EN]	= &tdmin_c_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
> +		[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
> +		[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
> +		[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
> +		[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
> +		[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
> +		[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
> +		[AUD_CLKID_TDMIN_A_SCLK]	= &tdmin_a_sclk.hw,
> +		[AUD_CLKID_TDMIN_B_SCLK]	= &tdmin_b_sclk.hw,
> +		[AUD_CLKID_TDMIN_C_SCLK]	= &tdmin_c_sclk.hw,
> +		[AUD_CLKID_TDMIN_LB_SCLK]	= &tdmin_lb_sclk.hw,
> +		[AUD_CLKID_TDMOUT_A_SCLK]	= &tdmout_a_sclk.hw,
> +		[AUD_CLKID_TDMOUT_B_SCLK]	= &tdmout_b_sclk.hw,
> +		[AUD_CLKID_TDMOUT_C_SCLK]	= &tdmout_c_sclk.hw,
> +		[AUD_CLKID_TDMIN_A_LRCLK]	= &tdmin_a_lrclk.hw,
> +		[AUD_CLKID_TDMIN_B_LRCLK]	= &tdmin_b_lrclk.hw,
> +		[AUD_CLKID_TDMIN_C_LRCLK]	= &tdmin_c_lrclk.hw,
> +		[AUD_CLKID_TDMIN_LB_LRCLK]	= &tdmin_lb_lrclk.hw,
> +		[AUD_CLKID_TDMOUT_A_LRCLK]	= &tdmout_a_lrclk.hw,
> +		[AUD_CLKID_TDMOUT_B_LRCLK]	= &tdmout_b_lrclk.hw,
> +		[AUD_CLKID_TDMOUT_C_LRCLK]	= &tdmout_c_lrclk.hw,
> +		[AUD_CLKID_TDM_MCLK_PAD0]	= &sm1_tdm_mclk_pad_0.hw,
> +		[AUD_CLKID_TDM_MCLK_PAD1]	= &sm1_tdm_mclk_pad_1.hw,
> +		[AUD_CLKID_TDM_LRCLK_PAD0]	= &sm1_tdm_lrclk_pad_0.hw,
> +		[AUD_CLKID_TDM_LRCLK_PAD1]	= &sm1_tdm_lrclk_pad_1.hw,
> +		[AUD_CLKID_TDM_LRCLK_PAD2]	= &sm1_tdm_lrclk_pad_2.hw,
> +		[AUD_CLKID_TDM_SCLK_PAD0]	= &sm1_tdm_sclk_pad_0.hw,
> +		[AUD_CLKID_TDM_SCLK_PAD1]	= &sm1_tdm_sclk_pad_1.hw,
> +		[AUD_CLKID_TDM_SCLK_PAD2]	= &sm1_tdm_sclk_pad_2.hw,
> +		[AUD_CLKID_TOP]			= &sm1_aud_top.hw,
> +		[AUD_CLKID_TORAM]		= &toram.hw,
> +		[AUD_CLKID_EQDRC]		= &eqdrc.hw,
> +		[AUD_CLKID_RESAMPLE_B]		= &resample_b.hw,
> +		[AUD_CLKID_TOVAD]		= &tovad.hw,
> +		[AUD_CLKID_LOCKER]		= &locker.hw,
> +		[AUD_CLKID_SPDIFIN_LB]		= &spdifin_lb.hw,
> +		[AUD_CLKID_FRDDR_D]		= &frddr_d.hw,
> +		[AUD_CLKID_TODDR_D]		= &toddr_d.hw,
> +		[AUD_CLKID_LOOPBACK_B]		= &loopback_b.hw,
> +		[AUD_CLKID_CLK81_EN]		= &sm1_clk81_en.hw,
> +		[AUD_CLKID_SYSCLK_A_DIV]	= &sm1_sysclk_a_div.hw,
> +		[AUD_CLKID_SYSCLK_A_EN]		= &sm1_sysclk_a_en.hw,
> +		[AUD_CLKID_SYSCLK_B_DIV]	= &sm1_sysclk_b_div.hw,
> +		[AUD_CLKID_SYSCLK_B_EN]		= &sm1_sysclk_b_en.hw,
> +		[NR_CLKS] = NULL,
> +	},
> +	.num = NR_CLKS,
> +};
> +
> +
>  /* Convenience table to populate regmap in .probe()
>   * Note that this table is shared between both AXG and G12A,
>   * with spdifout_b clocks being exclusive to G12A. Since those
>   * clocks are not declared within the AXG onecell table, we do not
>   * feel the need to have separate AXG/G12A regmap tables.
>   */
> -static struct clk_regmap *const aud_clk_regmaps[] = {
> +static struct clk_regmap *const axg_clk_regmaps[] = {
>  	&ddr_arb,
>  	&pdm,
>  	&tdmin_a,
> @@ -993,6 +1349,158 @@ static struct clk_regmap *const aud_clk_regmaps[] = {
>  	&g12a_tdm_sclk_pad_0,
>  	&g12a_tdm_sclk_pad_1,
>  	&g12a_tdm_sclk_pad_2,
> +	&toram,
> +	&eqdrc,
> +};
> +
> +static struct clk_regmap *const sm1_clk_regmaps[] = {
> +	&ddr_arb,
> +	&pdm,
> +	&tdmin_a,
> +	&tdmin_b,
> +	&tdmin_c,
> +	&tdmin_lb,
> +	&tdmout_a,
> +	&tdmout_b,
> +	&tdmout_c,
> +	&frddr_a,
> +	&frddr_b,
> +	&frddr_c,
> +	&toddr_a,
> +	&toddr_b,
> +	&toddr_c,
> +	&loopback,
> +	&spdifin,
> +	&spdifout,
> +	&resample,
> +	&spdifout_b,
> +	&sm1_mst_a_mclk_sel,
> +	&sm1_mst_b_mclk_sel,
> +	&sm1_mst_c_mclk_sel,
> +	&sm1_mst_d_mclk_sel,
> +	&sm1_mst_e_mclk_sel,
> +	&sm1_mst_f_mclk_sel,
> +	&sm1_mst_a_mclk_div,
> +	&sm1_mst_b_mclk_div,
> +	&sm1_mst_c_mclk_div,
> +	&sm1_mst_d_mclk_div,
> +	&sm1_mst_e_mclk_div,
> +	&sm1_mst_f_mclk_div,
> +	&sm1_mst_a_mclk,
> +	&sm1_mst_b_mclk,
> +	&sm1_mst_c_mclk,
> +	&sm1_mst_d_mclk,
> +	&sm1_mst_e_mclk,
> +	&sm1_mst_f_mclk,
> +	&spdifout_clk_sel,
> +	&spdifout_clk_div,
> +	&spdifout_clk,
> +	&spdifin_clk_sel,
> +	&spdifin_clk_div,
> +	&spdifin_clk,
> +	&pdm_dclk_sel,
> +	&pdm_dclk_div,
> +	&pdm_dclk,
> +	&pdm_sysclk_sel,
> +	&pdm_sysclk_div,
> +	&pdm_sysclk,
> +	&mst_a_sclk_pre_en,
> +	&mst_b_sclk_pre_en,
> +	&mst_c_sclk_pre_en,
> +	&mst_d_sclk_pre_en,
> +	&mst_e_sclk_pre_en,
> +	&mst_f_sclk_pre_en,
> +	&mst_a_sclk_div,
> +	&mst_b_sclk_div,
> +	&mst_c_sclk_div,
> +	&mst_d_sclk_div,
> +	&mst_e_sclk_div,
> +	&mst_f_sclk_div,
> +	&mst_a_sclk_post_en,
> +	&mst_b_sclk_post_en,
> +	&mst_c_sclk_post_en,
> +	&mst_d_sclk_post_en,
> +	&mst_e_sclk_post_en,
> +	&mst_f_sclk_post_en,
> +	&mst_a_sclk,
> +	&mst_b_sclk,
> +	&mst_c_sclk,
> +	&mst_d_sclk,
> +	&mst_e_sclk,
> +	&mst_f_sclk,
> +	&mst_a_lrclk_div,
> +	&mst_b_lrclk_div,
> +	&mst_c_lrclk_div,
> +	&mst_d_lrclk_div,
> +	&mst_e_lrclk_div,
> +	&mst_f_lrclk_div,
> +	&mst_a_lrclk,
> +	&mst_b_lrclk,
> +	&mst_c_lrclk,
> +	&mst_d_lrclk,
> +	&mst_e_lrclk,
> +	&mst_f_lrclk,
> +	&tdmin_a_sclk_sel,
> +	&tdmin_b_sclk_sel,
> +	&tdmin_c_sclk_sel,
> +	&tdmin_lb_sclk_sel,
> +	&tdmout_a_sclk_sel,
> +	&tdmout_b_sclk_sel,
> +	&tdmout_c_sclk_sel,
> +	&tdmin_a_sclk_pre_en,
> +	&tdmin_b_sclk_pre_en,
> +	&tdmin_c_sclk_pre_en,
> +	&tdmin_lb_sclk_pre_en,
> +	&tdmout_a_sclk_pre_en,
> +	&tdmout_b_sclk_pre_en,
> +	&tdmout_c_sclk_pre_en,
> +	&tdmin_a_sclk_post_en,
> +	&tdmin_b_sclk_post_en,
> +	&tdmin_c_sclk_post_en,
> +	&tdmin_lb_sclk_post_en,
> +	&tdmout_a_sclk_post_en,
> +	&tdmout_b_sclk_post_en,
> +	&tdmout_c_sclk_post_en,
> +	&tdmin_a_sclk,
> +	&tdmin_b_sclk,
> +	&tdmin_c_sclk,
> +	&tdmin_lb_sclk,
> +	&tdmout_a_sclk,
> +	&tdmout_b_sclk,
> +	&tdmout_c_sclk,
> +	&tdmin_a_lrclk,
> +	&tdmin_b_lrclk,
> +	&tdmin_c_lrclk,
> +	&tdmin_lb_lrclk,
> +	&tdmout_a_lrclk,
> +	&tdmout_b_lrclk,
> +	&tdmout_c_lrclk,
> +	&spdifout_b_clk_sel,
> +	&spdifout_b_clk_div,
> +	&spdifout_b_clk,
> +	&sm1_tdm_mclk_pad_0,
> +	&sm1_tdm_mclk_pad_1,
> +	&sm1_tdm_lrclk_pad_0,
> +	&sm1_tdm_lrclk_pad_1,
> +	&sm1_tdm_lrclk_pad_2,
> +	&sm1_tdm_sclk_pad_0,
> +	&sm1_tdm_sclk_pad_1,
> +	&sm1_tdm_sclk_pad_2,
> +	&sm1_aud_top,
> +	&toram,
> +	&eqdrc,
> +	&resample_b,
> +	&tovad,
> +	&locker,
> +	&spdifin_lb,
> +	&frddr_d,
> +	&toddr_d,
> +	&loopback_b,
> +	&sm1_clk81_en,
> +	&sm1_sysclk_a_div,
> +	&sm1_sysclk_a_en,
> +	&sm1_sysclk_b_div,
> +	&sm1_sysclk_b_en,
>  };
>  
>  static int devm_clk_get_enable(struct device *dev, char *id)
> @@ -1111,6 +1619,8 @@ static const struct regmap_config axg_audio_regmap_cfg = {
>  };
>  
>  struct audioclk_data {
> +	struct clk_regmap *const *regmap_clks;
> +	unsigned int regmap_clk_num;
>  	struct clk_hw_onecell_data *hw_onecell_data;
>  	unsigned int reset_offset;
>  	unsigned int reset_num;
> @@ -1154,8 +1664,8 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
>  	}
>  
>  	/* Populate regmap for the regmap backed clocks */
> -	for (i = 0; i < ARRAY_SIZE(aud_clk_regmaps); i++)
> -		aud_clk_regmaps[i]->map = map;
> +	for (i = 0; i < data->regmap_clk_num; i++)
> +		data->regmap_clks[i]->map = map;
>  
>  	/* Take care to skip the registered input clocks */
>  	for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) {
> @@ -1199,15 +1709,27 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
>  }
>  
>  static const struct audioclk_data axg_audioclk_data = {
> +	.regmap_clks = axg_clk_regmaps,
> +	.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
>  	.hw_onecell_data = &axg_audio_hw_onecell_data,
>  };
>  
>  static const struct audioclk_data g12a_audioclk_data = {
> +	.regmap_clks = axg_clk_regmaps,
> +	.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
>  	.hw_onecell_data = &g12a_audio_hw_onecell_data,
>  	.reset_offset = AUDIO_SW_RESET,
>  	.reset_num = 26,
>  };
>  
> +static const struct audioclk_data sm1_audioclk_data = {
> +	.regmap_clks = sm1_clk_regmaps,
> +	.regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps),
> +	.hw_onecell_data = &sm1_audio_hw_onecell_data,
> +	.reset_offset = AUDIO_SM1_SW_RESET0,
> +	.reset_num = 39,
> +};
> +
>  static const struct of_device_id clkc_match_table[] = {
>  	{
>  		.compatible = "amlogic,axg-audio-clkc",
> @@ -1215,6 +1737,9 @@ static const struct of_device_id clkc_match_table[] = {
>  	}, {
>  		.compatible = "amlogic,g12a-audio-clkc",
>  		.data = &g12a_audioclk_data
> +	}, {
> +		.compatible = "amlogic,sm1-audio-clkc",
> +		.data = &sm1_audioclk_data
>  	}, {}
>  };
>  MODULE_DEVICE_TABLE(of, clkc_match_table);
> @@ -1228,6 +1753,6 @@ static struct platform_driver axg_audio_driver = {
>  };
>  module_platform_driver(axg_audio_driver);
>  
> -MODULE_DESCRIPTION("Amlogic AXG/G12A Audio Clock driver");
> +MODULE_DESCRIPTION("Amlogic AXG/G12A/SM1 Audio Clock driver");
>  MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
>  MODULE_LICENSE("GPL v2");
> diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h
> index a4956837f597..fd65a7d0704b 100644
> --- a/drivers/clk/meson/axg-audio.h
> +++ b/drivers/clk/meson/axg-audio.h
> @@ -50,6 +50,20 @@
>  #define AUDIO_CLK_PDMIN_CTRL1	0x0B0
>  #define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4
>  
> +/* SM1 introduce new register and some shifts :( */
> +#define AUDIO_CLK_GATE_EN1	0x004
> +#define AUDIO_SM1_MCLK_A_CTRL	0x008
> +#define AUDIO_SM1_MCLK_B_CTRL	0x00C
> +#define AUDIO_SM1_MCLK_C_CTRL	0x010
> +#define AUDIO_SM1_MCLK_D_CTRL	0x014
> +#define AUDIO_SM1_MCLK_E_CTRL	0x018
> +#define AUDIO_SM1_MCLK_F_CTRL	0x01C
> +#define AUDIO_SM1_MST_PAD_CTRL0	0x020
> +#define AUDIO_SM1_MST_PAD_CTRL1	0x024
> +#define AUDIO_SM1_SW_RESET0	0x028
> +#define AUDIO_SM1_SW_RESET1	0x02C
> +#define AUDIO_CLK81_CTRL	0x030
> +#define AUDIO_CLK81_EN		0x034
>  /*
>   * CLKID index values
>   * These indices are entirely contrived and do not map onto the hardware.
> @@ -115,11 +129,15 @@
>  #define AUD_CLKID_TDMOUT_C_SCLK_POST_EN	150
>  #define AUD_CLKID_SPDIFOUT_B_CLK_SEL	153
>  #define AUD_CLKID_SPDIFOUT_B_CLK_DIV	154
> -
> +#define AUD_CLKID_CLK81_EN		173
> +#define AUD_CLKID_SYSCLK_A_DIV		174
> +#define AUD_CLKID_SYSCLK_B_DIV		175
> +#define AUD_CLKID_SYSCLK_A_EN		176
> +#define AUD_CLKID_SYSCLK_B_EN		177
>  
>  /* include the CLKIDs which are part of the DT bindings */
>  #include <dt-bindings/clock/axg-audio-clkc.h>
>  
> -#define NR_CLKS	164
> +#define NR_CLKS	178
>  
>  #endif /*__AXG_AUDIO_CLKC_H */
> 

Small nit, but:
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 6/7] clk: meson: axg-audio: provide clk top signal name
  2019-09-27  9:14   ` Neil Armstrong
@ 2019-09-27  9:37     ` Neil Armstrong
  2019-09-27 13:58       ` Jerome Brunet
  0 siblings, 1 reply; 19+ messages in thread
From: Neil Armstrong @ 2019-09-27  9:37 UTC (permalink / raw)
  To: Jerome Brunet; +Cc: Kevin Hilman, linux-amlogic, linux-clk, linux-kernel

On 27/09/2019 11:14, Neil Armstrong wrote:
> On 24/09/2019 17:33, Jerome Brunet wrote:
>> The peripheral clock on the sm1 goes through some muxes
>> and dividers before reaching the audio gates. To model that,
>> without repeating our self too much, the "top" clock signal
>> is introduced and will serve as a the parent of the gates.
>>
>> On the axg and g12a, the top clock is just a pass-through to
>> the audio peripheral clock provided by the main controller.
>>
>> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
>> ---
>>  drivers/clk/meson/axg-audio.c | 19 ++++++++++++++++---
>>  drivers/clk/meson/axg-audio.h |  3 ++-
>>  2 files changed, 18 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
>> index ce8836776d1c..a8ccdbaecae2 100644
>> --- a/drivers/clk/meson/axg-audio.c
>> +++ b/drivers/clk/meson/axg-audio.c
>> @@ -74,9 +74,7 @@
>>  	.hw.init = &(struct clk_init_data) {				\
>>  		.name = "aud_"#_name,					\
>>  		.ops = &clk_regmap_gate_ops,				\
>> -		.parent_data = &(const struct clk_parent_data) {	\
>> -			.fw_name = "pclk",				\
>> -		},							\
>> +		.parent_names = (const char *[]){ "aud_top" },		\
>>  		.num_parents = 1,					\
>>  	},								\
>>  }
>> @@ -504,6 +502,19 @@ static struct clk_regmap tdmout_c_lrclk =
>>  	AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
>>  
>>  /* AXG/G12A Clocks */
>> +
>> +static struct clk_hw axg_aud_top = {
>> +	.init = &(struct clk_init_data) {
>> +		/* Provide aud_top signal name on axg and g12a */
>> +		.name = "aud_top",
>> +		.ops = &(const struct clk_ops) {},
>> +		.parent_data = &(const struct clk_parent_data) {
>> +			.fw_name = "pclk",
>> +		},
>> +		.num_parents = 1,
>> +	},
>> +};
>> +
>>  static struct clk_regmap mst_a_mclk_sel =
>>  	AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
>>  static struct clk_regmap mst_b_mclk_sel =
>> @@ -691,6 +702,7 @@ static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
>>  		[AUD_CLKID_TDMOUT_A_LRCLK]	= &tdmout_a_lrclk.hw,
>>  		[AUD_CLKID_TDMOUT_B_LRCLK]	= &tdmout_b_lrclk.hw,
>>  		[AUD_CLKID_TDMOUT_C_LRCLK]	= &tdmout_c_lrclk.hw,
>> +		[AUD_CLKID_TOP]			= &axg_aud_top,
>>  		[NR_CLKS] = NULL,
>>  	},
>>  	.num = NR_CLKS,
>> @@ -835,6 +847,7 @@ static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
>>  		[AUD_CLKID_TDM_SCLK_PAD0]	= &g12a_tdm_sclk_pad_0.hw,
>>  		[AUD_CLKID_TDM_SCLK_PAD1]	= &g12a_tdm_sclk_pad_1.hw,
>>  		[AUD_CLKID_TDM_SCLK_PAD2]	= &g12a_tdm_sclk_pad_2.hw,
>> +		[AUD_CLKID_TOP]			= &axg_aud_top,
>>  		[NR_CLKS] = NULL,
>>  	},
>>  	.num = NR_CLKS,
>> diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h
>> index c00e28b2e1a9..a4956837f597 100644
>> --- a/drivers/clk/meson/axg-audio.h
>> +++ b/drivers/clk/meson/axg-audio.h
>> @@ -116,9 +116,10 @@
>>  #define AUD_CLKID_SPDIFOUT_B_CLK_SEL	153
>>  #define AUD_CLKID_SPDIFOUT_B_CLK_DIV	154
>>  
>> +
> 
> AUD_CLKID_TOP seems to be missing here

Oh, yes it was exposed, do you need to it to be exposed since it's dummy for G12A ?

Neil

> 
> 
>>  /* include the CLKIDs which are part of the DT bindings */
>>  #include <dt-bindings/clock/axg-audio-clkc.h>
>>  
>> -#define NR_CLKS	163
>> +#define NR_CLKS	164
>>  
>>  #endif /*__AXG_AUDIO_CLKC_H */
>>
> 


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 6/7] clk: meson: axg-audio: provide clk top signal name
  2019-09-27  9:37     ` Neil Armstrong
@ 2019-09-27 13:58       ` Jerome Brunet
  2019-09-27 14:07         ` Neil Armstrong
  0 siblings, 1 reply; 19+ messages in thread
From: Jerome Brunet @ 2019-09-27 13:58 UTC (permalink / raw)
  To: Neil Armstrong
  Cc: Jerome Brunet, Kevin Hilman, linux-amlogic, linux-clk, linux-kernel


On Fri 27 Sep 2019 at 11:37, Neil Armstrong <narmstrong@baylibre.com> wrote:

> On 27/09/2019 11:14, Neil Armstrong wrote:
>> On 24/09/2019 17:33, Jerome Brunet wrote:
>>

[...]

>> AUD_CLKID_TOP seems to be missing here
>
> Oh, yes it was exposed, do you need to it to be exposed since it's
> dummy for G12A ?

It is a bypass clock on g12a and axg yes, but on the sm1.
It is the leaf of a block on sm1, for all I know it could be used
outside the clock controller.

Of course, I could wait this until there is an actual need for it if that is
what you mean ?

>
> Neil
>
>> 
>> 
>>>  /* include the CLKIDs which are part of the DT bindings */
>>>  #include <dt-bindings/clock/axg-audio-clkc.h>
>>>  
>>> -#define NR_CLKS	163
>>> +#define NR_CLKS	164
>>>  
>>>  #endif /*__AXG_AUDIO_CLKC_H */
>>>
>> 


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 7/7] clk: meson: axg_audio: add sm1 support
  2019-09-27  9:36   ` Neil Armstrong
@ 2019-09-27 14:01     ` Jerome Brunet
  0 siblings, 0 replies; 19+ messages in thread
From: Jerome Brunet @ 2019-09-27 14:01 UTC (permalink / raw)
  To: Neil Armstrong
  Cc: Jerome Brunet, Kevin Hilman, linux-amlogic, linux-clk, linux-kernel


On Fri 27 Sep 2019 at 11:36, Neil Armstrong <narmstrong@baylibre.com> wrote:

>>  
>>  static struct clk_regmap spdifout_clk_sel =
>>  	AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
>> @@ -502,7 +522,6 @@ static struct clk_regmap tdmout_c_lrclk =
>>  	AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
>>  
>>  /* AXG/G12A Clocks */
>> -
>
> Spurious line remove

Oops, I'll migrate that to the appropriate change, Thx

>
>>  static struct clk_hw axg_aud_top = {
>>  	.init = &(struct clk_init_data) {
>>  		/* Provide aud_top signal name on axg and g12a */
>> @@ -573,7 +592,185 @@ static struct clk_regmap g12a_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
>
> Small nit, but:
> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 6/7] clk: meson: axg-audio: provide clk top signal name
  2019-09-27 13:58       ` Jerome Brunet
@ 2019-09-27 14:07         ` Neil Armstrong
  0 siblings, 0 replies; 19+ messages in thread
From: Neil Armstrong @ 2019-09-27 14:07 UTC (permalink / raw)
  To: Jerome Brunet; +Cc: Kevin Hilman, linux-amlogic, linux-clk, linux-kernel

On 27/09/2019 15:58, Jerome Brunet wrote:
> 
> On Fri 27 Sep 2019 at 11:37, Neil Armstrong <narmstrong@baylibre.com> wrote:
> 
>> On 27/09/2019 11:14, Neil Armstrong wrote:
>>> On 24/09/2019 17:33, Jerome Brunet wrote:
>>>
> 
> [...]
> 
>>> AUD_CLKID_TOP seems to be missing here
>>
>> Oh, yes it was exposed, do you need to it to be exposed since it's
>> dummy for G12A ?
> 
> It is a bypass clock on g12a and axg yes, but on the sm1.
> It is the leaf of a block on sm1, for all I know it could be used
> outside the clock controller.
> 
> Of course, I could wait this until there is an actual need for it if that is
> what you mean ?

Yes, but it's a valid clock on sm1, so leave it as it is.

Neil

> 
>>
>> Neil
>>
>>>
>>>
>>>>  /* include the CLKIDs which are part of the DT bindings */
>>>>  #include <dt-bindings/clock/axg-audio-clkc.h>
>>>>  
>>>> -#define NR_CLKS	163
>>>> +#define NR_CLKS	164
>>>>  
>>>>  #endif /*__AXG_AUDIO_CLKC_H */
>>>>
>>>
> 


^ permalink raw reply	[flat|nested] 19+ messages in thread

end of thread, other threads:[~2019-09-27 14:07 UTC | newest]

Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-09-24 15:33 [PATCH 0/7] clk: meson: axg-audio: add sm1 support Jerome Brunet
2019-09-24 15:33 ` [PATCH 1/7] dt-bindings: clk: axg-audio: add sm1 bindings Jerome Brunet
2019-09-27  9:10   ` Neil Armstrong
2019-09-24 15:33 ` [PATCH 2/7] dt-bindings: clock: meson: add sm1 resets to the axg-audio controller Jerome Brunet
2019-09-27  9:10   ` Neil Armstrong
2019-09-24 15:33 ` [PATCH 3/7] clk: meson: axg-audio: remove useless defines Jerome Brunet
2019-09-27  9:10   ` Neil Armstrong
2019-09-24 15:33 ` [PATCH 4/7] clk: meson: axg-audio: fix regmap last register Jerome Brunet
2019-09-27  9:11   ` Neil Armstrong
2019-09-24 15:33 ` [PATCH 5/7] clk: meson: axg-audio: prepare sm1 addition Jerome Brunet
2019-09-27  9:13   ` Neil Armstrong
2019-09-24 15:33 ` [PATCH 6/7] clk: meson: axg-audio: provide clk top signal name Jerome Brunet
2019-09-27  9:14   ` Neil Armstrong
2019-09-27  9:37     ` Neil Armstrong
2019-09-27 13:58       ` Jerome Brunet
2019-09-27 14:07         ` Neil Armstrong
2019-09-24 15:33 ` [PATCH 7/7] clk: meson: axg_audio: add sm1 support Jerome Brunet
2019-09-27  9:36   ` Neil Armstrong
2019-09-27 14:01     ` Jerome Brunet

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