From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B49E5C4360C for ; Sun, 29 Sep 2019 17:43:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 903AC2086A for ; Sun, 29 Sep 2019 17:43:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1569779011; bh=fDMWIJ2q2yQifpis9eqvA9OLwFuD2uX2kyQjV7oQPDc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=eLci36w8FTL3ne050YM0Sz+qh2kme6WDnlkZr/kwg+uIT9EtDFLtlfzelQpRZkRF7 FMNxpxCs356QLgBWO3MEpAcyPFUvmC5JIE+XGdTwiew9ZNBmDaiGhar7zq6Q94TRcI OH/ZdMfbNQilz3+fK6u43ZPLBAexsdO5EBcieK/A= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729338AbfI2Rbd (ORCPT ); Sun, 29 Sep 2019 13:31:33 -0400 Received: from mail.kernel.org ([198.145.29.99]:41926 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729316AbfI2Rbb (ORCPT ); Sun, 29 Sep 2019 13:31:31 -0400 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 24FCD21927; Sun, 29 Sep 2019 17:31:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1569778290; bh=fDMWIJ2q2yQifpis9eqvA9OLwFuD2uX2kyQjV7oQPDc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MFGSbHj1w8WvVx0F3r0ndzVhUy3ZAL2Iiu+np/L4kwDB9fuIUitJhF+JZqpR5bwsm ExEYwE1S06iD2HK5TLfJfmah09QvhcBWgAE9QmyFMQkSpryZGEvDeisSLmhsorDNBQ jmMRTPG0zznnhTYzhuhazWXeIboDbA1o1sBbj0DA= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Will Deacon , Orion Hodson , Russell King , Sasha Levin Subject: [PATCH AUTOSEL 5.3 15/49] ARM: 8898/1: mm: Don't treat faults reported from cache maintenance as writes Date: Sun, 29 Sep 2019 13:30:15 -0400 Message-Id: <20190929173053.8400-15-sashal@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190929173053.8400-1-sashal@kernel.org> References: <20190929173053.8400-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Will Deacon [ Upstream commit 834020366da9ab3fb87d1eb9a3160eb22dbed63a ] Translation faults arising from cache maintenance instructions are rather unhelpfully reported with an FSR value where the WnR field is set to 1, indicating that the faulting access was a write. Since cache maintenance instructions on 32-bit ARM do not require any particular permissions, this can cause our private 'cacheflush' system call to fail spuriously if a translation fault is generated due to page aging when targetting a read-only VMA. In this situation, we will return -EFAULT to userspace, although this is unfortunately suppressed by the popular '__builtin___clear_cache()' intrinsic provided by GCC, which returns void. Although it's tempting to write this off as a userspace issue, we can actually do a little bit better on CPUs that support LPAE, even if the short-descriptor format is in use. On these CPUs, cache maintenance faults additionally set the CM field in the FSR, which we can use to suppress the write permission checks in the page fault handler and succeed in performing cache maintenance to read-only areas even in the presence of a translation fault. Reported-by: Orion Hodson Signed-off-by: Will Deacon Signed-off-by: Russell King Signed-off-by: Sasha Levin --- arch/arm/mm/fault.c | 4 ++-- arch/arm/mm/fault.h | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 890eeaac3cbba..bd0f4821f7e11 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -191,7 +191,7 @@ static inline bool access_error(unsigned int fsr, struct vm_area_struct *vma) { unsigned int mask = VM_READ | VM_WRITE | VM_EXEC; - if (fsr & FSR_WRITE) + if ((fsr & FSR_WRITE) && !(fsr & FSR_CM)) mask = VM_WRITE; if (fsr & FSR_LNX_PF) mask = VM_EXEC; @@ -262,7 +262,7 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) if (user_mode(regs)) flags |= FAULT_FLAG_USER; - if (fsr & FSR_WRITE) + if ((fsr & FSR_WRITE) && !(fsr & FSR_CM)) flags |= FAULT_FLAG_WRITE; /* diff --git a/arch/arm/mm/fault.h b/arch/arm/mm/fault.h index c063708fa5032..9ecc2097a87a0 100644 --- a/arch/arm/mm/fault.h +++ b/arch/arm/mm/fault.h @@ -6,6 +6,7 @@ * Fault status register encodings. We steal bit 31 for our own purposes. */ #define FSR_LNX_PF (1 << 31) +#define FSR_CM (1 << 13) #define FSR_WRITE (1 << 11) #define FSR_FS4 (1 << 10) #define FSR_FS3_0 (15) -- 2.20.1