From: Thierry Reding <thierry.reding@gmail.com>
To: JC Kuo <jckuo@nvidia.com>
Cc: gregkh@linuxfoundation.org, jonathanh@nvidia.com,
linux-tegra@vger.kernel.org, linux-usb@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
nkristam@nvidia.com, skomatineni@nvidia.com
Subject: Re: [PATCH 5/6] arm64: tegra: Add XUSB and pad controller on Tegra194
Date: Wed, 2 Oct 2019 12:11:02 +0200 [thread overview]
Message-ID: <20191002101102.GG3716706@ulmo> (raw)
In-Reply-To: <20191002080051.11142-6-jckuo@nvidia.com>
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On Wed, Oct 02, 2019 at 04:00:50PM +0800, JC Kuo wrote:
> Adds the XUSB pad and XUSB controllers on Tegra194.
>
> Signed-off-by: JC Kuo <jckuo@nvidia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 130 +++++++++++++++++++++++
> 1 file changed, 130 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index 3c0cf54f0aab..4d3371d3a407 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -1599,4 +1599,134 @@
> interrupt-parent = <&gic>;
> always-on;
> };
> +
> + xusb_padctl: padctl@3520000 {
I also noticed that this is outside of the /cbb bus node. It really
belongs inside /cbb. Same for the XHCI controller node.
Thierry
> + compatible = "nvidia,tegra194-xusb-padctl";
> + reg = <0x0 0x03520000 0x0 0x1000>,
> + <0x0 0x03540000 0x0 0x1000>;
> + reg-names = "padctl", "ao";
> +
> + resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
> + reset-names = "padctl";
> +
> + status = "disabled";
> +
> + pads {
> + usb2 {
> + clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
> + clock-names = "trk";
> +
> + lanes {
> + usb2-0 {
> + nvidia,function = "xusb";
> + status = "disabled";
> + #phy-cells = <0>;
> + };
> + usb2-1 {
> + nvidia,function = "xusb";
> + status = "disabled";
> + #phy-cells = <0>;
> + };
> + usb2-2 {
> + nvidia,function = "xusb";
> + status = "disabled";
> + #phy-cells = <0>;
> + };
> + usb2-3 {
> + nvidia,function = "xusb";
> + status = "disabled";
> + #phy-cells = <0>;
> + };
> + };
> + };
> + usb3 {
> + lanes {
> + usb3-0 {
> + nvidia,function = "xusb";
> + status = "disabled";
> + #phy-cells = <0>;
> + };
> + usb3-1 {
> + nvidia,function = "xusb";
> + status = "disabled";
> + #phy-cells = <0>;
> + };
> + usb3-2 {
> + nvidia,function = "xusb";
> + status = "disabled";
> + #phy-cells = <0>;
> + };
> + usb3-3 {
> + nvidia,function = "xusb";
> + status = "disabled";
> + #phy-cells = <0>;
> + };
> + };
> + };
> + };
> +
> + ports {
> + usb2-0 {
> + status = "disabled";
> + };
> + usb2-1 {
> + status = "disabled";
> + };
> + usb2-2 {
> + status = "disabled";
> + };
> + usb2-3 {
> + status = "disabled";
> + };
> + usb3-0 {
> + status = "disabled";
> + };
> + usb3-1 {
> + status = "disabled";
> + };
> + usb3-2 {
> + status = "disabled";
> + };
> + usb3-3 {
> + status = "disabled";
> + };
> + };
> + };
> +
> + tegra_xhci: xhci@3610000 {
> + compatible = "nvidia,tegra194-xusb";
> + reg = <0x0 0x03610000 0x0 0x40000>,
> + <0x0 0x03600000 0x0 0x10000>;
> + reg-names = "hcd", "fpci";
> +
> + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_MUX>,
> + <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
> + <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
> + <&bpmp TEGRA194_CLK_XUSB_FALCON>,
> + <&bpmp TEGRA194_CLK_XUSB_FALCON_HOST>,
> + <&bpmp TEGRA194_CLK_XUSB_FALCON_SS>,
> + <&bpmp TEGRA194_CLK_XUSB_FS>,
> + <&bpmp TEGRA194_CLK_XUSB_FS_HOST>,
> + <&bpmp TEGRA194_CLK_XUSB_SS>,
> + <&bpmp TEGRA194_CLK_XUSB_SS_SUPERSPEED>,
> + <&bpmp TEGRA194_CLK_UTMIPLL>,
> + <&bpmp TEGRA194_CLK_CLK_M>,
> + <&bpmp TEGRA194_CLK_PLLE>;
> + clock-names = "xusb_hs_src", "xusb_host",
> + "xusb_core_superspeed_clk", "xusb_falcon_src",
> + "xusb_falcon_host_clk", "xusb_falcon_superspeed_clk",
> + "xusb_fs_src", "xusb_fs_host_clk", "xusb_ss_src",
> + "xusb_ss", "pll_u_480m", "clk_m", "pll_e";
> +
> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
> + <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
> + power-domain-names = "xusb_host", "xusb_ss";
> +
> + nvidia,xusb-padctl = <&xusb_padctl>;
> + status = "disabled";
> + };
> };
> --
> 2.17.1
>
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next prev parent reply other threads:[~2019-10-02 10:11 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-02 8:00 [PATCH 0/6] Add Tegra194 XUSB host and pad controller support JC Kuo
2019-10-02 8:00 ` [PATCH 1/6] xhci: tegra: Parameterize mailbox register addresses JC Kuo
2019-10-02 9:39 ` Thierry Reding
2019-10-02 8:00 ` [PATCH 2/6] usb: host: xhci-tegra: Add Tegra194 XHCI support JC Kuo
2019-10-02 9:40 ` Thierry Reding
2019-10-02 8:00 ` [PATCH 3/6] phy: tegra: xusb: Add Tegra194 support JC Kuo
2019-10-02 10:02 ` Thierry Reding
2019-10-03 2:00 ` JC Kuo
2019-10-02 8:00 ` [PATCH 4/6] dt-bindings: phy: tegra: " JC Kuo
2019-10-02 9:44 ` Thierry Reding
2019-10-03 1:50 ` JC Kuo
2019-10-02 8:00 ` [PATCH 5/6] arm64: tegra: Add XUSB and pad controller on Tegra194 JC Kuo
2019-10-02 10:10 ` Thierry Reding
2019-10-03 2:04 ` JC Kuo
2019-10-02 10:11 ` Thierry Reding [this message]
2019-10-03 2:06 ` JC Kuo
2019-10-02 8:00 ` [PATCH 6/6] arm64: tegra: Enable XUSB host in P2972-0000 board JC Kuo
2019-10-02 10:26 ` Thierry Reding
2019-10-03 6:00 ` JC Kuo
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