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[86.9.19.6]) by smtp.gmail.com with ESMTPSA id n17sm2102552wrp.37.2019.10.03.03.20.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2019 03:20:25 -0700 (PDT) Date: Thu, 3 Oct 2019 11:20:23 +0100 From: Daniel Thompson To: Mathieu Poirier Cc: Sai Prakash Ranjan , Jeffrey Hugo , Mark Rutland , Rajendra Nayak , Suzuki K Poulose , Alexander Shishkin , MSM , Marc Gonzalez , lkml , Bjorn Andersson , David Brown , Andy Gross , Sibi Sankar , Leo Yan , linux-arm-kernel , linux-arm-msm-owner@vger.kernel.org Subject: Re: [PATCHv9 2/3] arm64: dts: qcom: msm8998: Add Coresight support Message-ID: <20191003102023.qk6ik5vmatheaofs@holly.lan> References: <90114e06825e537c3aafd3de5c78743a9de6fadc.1564550873.git.saiprakash.ranjan@codeaurora.org> <16212a577339204e901cf4eefa5e82f1@codeaurora.org> <5b8835905a704fb813714694a792df54@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20180716 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Oct 02, 2019 at 09:03:59AM -0600, Mathieu Poirier wrote: > On Tue, 1 Oct 2019 at 12:05, Sai Prakash Ranjan > wrote: > > > > On 2019-10-01 11:01, Jeffrey Hugo wrote: > > > On Tue, Oct 1, 2019 at 11:52 AM Sai Prakash Ranjan > > > wrote: > > >> > > >> > > >> Haan then likely it's the firmware issue. > > >> We should probably disable coresight in soc dtsi and enable only for > > >> MTP. For now you can add a status=disabled for all coresight nodes in > > >> msm8998.dtsi and I will send the patch doing the same in a day or > > >> two(sorry I am travelling currently). > > > > > > This sounds sane to me (and is what I did while bisecting the issue). > > > When you do create the patch, feel free to add the following tags as > > > you see fit. > > > > > > Reported-by: Jeffrey Hugo > > > Tested-by: Jeffrey Hugo > > > > Thanks Jeffrey, I will add them. > > Hope Mathieu and Suzuki are OK with this. > > The problem here is that a debug and production device are using the > same device tree, i.e msm8998.dtsi. Disabling coresight devices in > the DTS file will allow the laptop to boot but completely disabled > coresight blocks on the MTP board. Leaving things as is breaks the > laptop but allows coresight to be used on the MTP board. One of three > things can happen: > > 1) Nothing gets done and production board can't boot without DTS modifications. > 2) Disable tags are added to the DTS file and the debug board can't > use coresight without modifications. > 2) The handling of the debug power domain is done properly on the > MSM8998 rather than relying on the bootloader to enable it. > 3) The DTS file is split or reorganised to account for debug/production devices. msm8998.dtsi is a SoC include file. Can't whatever default it adopts be reversed in the board include files such as msm8998-mtp.dtsi or msm8998-clamshell.dtsi ? Daniel.