From: Peter Zijlstra <peterz@infradead.org>
To: "Liang, Kan" <kan.liang@linux.intel.com>
Cc: acme@kernel.org, mingo@kernel.org, linux-kernel@vger.kernel.org,
jolsa@kernel.org, namhyung@kernel.org, ak@linux.intel.com,
vitaly.slobodskoy@intel.com, pavel.gerasimov@intel.com
Subject: Re: [PATCH 01/10] perf/core, x86: Add PERF_SAMPLE_LBR_TOS
Date: Tue, 8 Oct 2019 16:38:50 +0200 [thread overview]
Message-ID: <20191008143850.GB2328@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <3ac026c3-6b9c-a6c1-2c2b-c7ecdbb22b1d@linux.intel.com>
On Tue, Oct 08, 2019 at 09:53:24AM -0400, Liang, Kan wrote:
>
>
> On 10/8/2019 4:31 AM, Peter Zijlstra wrote:
> > On Mon, Oct 07, 2019 at 10:59:01AM -0700, kan.liang@linux.intel.com wrote:
> > > diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
> > > index 61448c19a132..ee9ef0c4cb08 100644
> > > --- a/include/linux/perf_event.h
> > > +++ b/include/linux/perf_event.h
> > > @@ -100,6 +100,7 @@ struct perf_raw_record {
> > > */
> > > struct perf_branch_stack {
> > > __u64 nr;
> > > + __u64 tos;
> > > struct perf_branch_entry entries[0];
> > > };
> > > diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
> > > index bb7b271397a6..fe36ebb7dc2e 100644
> > > --- a/include/uapi/linux/perf_event.h
> > > +++ b/include/uapi/linux/perf_event.h
> > > @@ -141,8 +141,9 @@ enum perf_event_sample_format {
> > > PERF_SAMPLE_TRANSACTION = 1U << 17,
> > > PERF_SAMPLE_REGS_INTR = 1U << 18,
> > > PERF_SAMPLE_PHYS_ADDR = 1U << 19,
> > > + PERF_SAMPLE_LBR_TOS = 1U << 20,
> > > - PERF_SAMPLE_MAX = 1U << 20, /* non-ABI */
> > > + PERF_SAMPLE_MAX = 1U << 21, /* non-ABI */
> > > __PERF_SAMPLE_CALLCHAIN_EARLY = 1ULL << 63, /* non-ABI; internal use */
> > > };
> > > @@ -864,6 +865,7 @@ enum perf_event_type {
> > > * { u64 abi; # enum perf_sample_regs_abi
> > > * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR
> > > * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR
> > > + * { u64 tos;} && PERF_SAMPLE_LBR_TOS
> > > * };
> > > */
> > > PERF_RECORD_SAMPLE = 9,
> >
> > I have problems with the API.. You're introducing the intel specific LBR
> > naming, and adding a whole new sample type vs extending the existing
> > BRANCH_STACK (like you really already do with struct perf_branch_stack). >
> > So why not add a bit to PERF_SAMPLE_BRANCH_* to request the presence of
> > the TOS field in the PERF_SAMPLE_BRANCH_STACK output?
>
> We never store PERF_SAMPLE_BRANCH_* in a sample. The perf tool cannot tell
> if the sample includes TOS field.
The perf tool bloody sets the perf_event_attr::branch_sample_type value!
Of course it knows to expect the TOS field when it asks for it in the
first place.
> There will be a problem when a new perf tool parsing the data generated by
> an old kernel.
ISTR perf stores the full perf_event_attr in the .data file these days,
and therefore such confusion should never happen.
next prev parent reply other threads:[~2019-10-08 14:38 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-07 17:59 [PATCH 00/10] Stitch LBR call stack kan.liang
2019-10-07 17:59 ` [PATCH 01/10] perf/core, x86: Add PERF_SAMPLE_LBR_TOS kan.liang
2019-10-08 8:31 ` Peter Zijlstra
2019-10-08 13:53 ` Liang, Kan
2019-10-08 14:38 ` Peter Zijlstra [this message]
2019-10-08 15:25 ` Liang, Kan
2019-10-08 16:32 ` Peter Zijlstra
2019-10-07 17:59 ` [PATCH 02/10] perf tools: Support PERF_SAMPLE_LBR_TOS kan.liang
2019-10-07 17:59 ` [PATCH 03/10] perf pmu: Add support for PMU capabilities kan.liang
2019-10-07 17:59 ` [PATCH 04/10] perf header: Support CPU " kan.liang
2019-10-07 17:59 ` [PATCH 05/10] perf machine: Refine the function for LBR call stack reconstruction kan.liang
2019-10-07 17:59 ` [PATCH 06/10] perf tools: Stitch LBR call stack kan.liang
2019-10-07 17:59 ` [PATCH 07/10] perf report: Add option to enable the LBR stitching approach kan.liang
2019-10-07 17:59 ` [PATCH 08/10] perf script: " kan.liang
2019-10-07 17:59 ` [PATCH 09/10] perf top: " kan.liang
2019-10-07 17:59 ` [PATCH 10/10] perf c2c: " kan.liang
2019-10-07 18:24 ` [PATCH 00/10] Stitch LBR call stack Ingo Molnar
2019-10-07 20:06 ` Liang, Kan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20191008143850.GB2328@hirez.programming.kicks-ass.net \
--to=peterz@infradead.org \
--cc=acme@kernel.org \
--cc=ak@linux.intel.com \
--cc=jolsa@kernel.org \
--cc=kan.liang@linux.intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@kernel.org \
--cc=namhyung@kernel.org \
--cc=pavel.gerasimov@intel.com \
--cc=vitaly.slobodskoy@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).