From: Greg KH <greg@kroah.com>
To: Alexander Gordeev <a.gordeev.box@gmail.com>
Cc: linux-kernel@vger.kernel.org, devel@driverdev.osuosl.org,
Michael Chen <micchen@altera.com>,
dmaengine@vger.kernel.org
Subject: Re: [PATCH RFC v2 2/2] dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe test
Date: Wed, 9 Oct 2019 15:08:18 +0200 [thread overview]
Message-ID: <20191009130818.GB4148375@kroah.com> (raw)
In-Reply-To: <6b540aeae71112154836003f2356703df2b36333.1570558807.git.a.gordeev.box@gmail.com>
On Wed, Oct 09, 2019 at 12:12:31PM +0200, Alexander Gordeev wrote:
> +config AVALON_TEST_TARGET_BASE
> + hex "Target device base address"
> + default "0x70000000"
> +
> +config AVALON_TEST_TARGET_SIZE
> + hex "Target device memory size"
> + default "0x10000000"
Don't put stuff like this as a configuration option, requiring the
kernel to be rebuilt. Make it dynamic, or from device tree, but not
like this.
thanks,
greg k-h
next prev parent reply other threads:[~2019-10-09 13:08 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-09 10:12 [PATCH v2 0/2] dmaengine: avalon: Support Avalon-MM DMA Interface for PCIe Alexander Gordeev
2019-10-09 10:12 ` [PATCH v2 1/2] dmaengine: avalon: Intel " Alexander Gordeev
2019-10-09 12:14 ` Dan Carpenter
2019-10-09 14:58 ` Alexander Gordeev
2019-10-09 18:53 ` Dan Carpenter
2019-10-10 8:51 ` Alexander Gordeev
2019-10-10 11:30 ` Dan Carpenter
2019-10-15 11:24 ` Alexander Gordeev
2019-10-15 11:41 ` Dan Carpenter
2019-10-15 12:27 ` Alexander Gordeev
2019-10-15 13:19 ` Dan Carpenter
2019-10-15 14:31 ` Alexander Gordeev
2019-10-15 14:47 ` Dan Carpenter
2019-10-09 13:07 ` Greg KH
2019-10-15 10:33 ` Vinod Koul
2019-10-15 13:11 ` Alexander Gordeev
2019-10-09 10:12 ` [PATCH RFC v2 2/2] dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe test Alexander Gordeev
2019-10-09 13:08 ` Greg KH [this message]
2019-10-09 13:46 ` Dan Carpenter
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