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* [PATCH v2 0/2] clk: ast2600: Expose RMII RCLK for MACs 1-4
@ 2019-10-10  2:07 Andrew Jeffery
  2019-10-10  2:07 ` [PATCH v2 1/2] dt-bindings: clock: Add AST2600 RMII RCLK gate definitions Andrew Jeffery
  2019-10-10  2:07 ` [PATCH v2 2/2] clk: ast2600: Add RMII RCLK gates for all four MACs Andrew Jeffery
  0 siblings, 2 replies; 6+ messages in thread
From: Andrew Jeffery @ 2019-10-10  2:07 UTC (permalink / raw)
  To: linux-clk
  Cc: mturquette, sboyd, joel, robh+dt, mark.rutland, linux-arm-kernel,
	linux-aspeed, linux-kernel, devicetree

Hello,

This series is similar to that for the AST2500 but I've split the patches out
as the AST2600 driver is new for 5.4 and I'm hoping we have a chance of
slipping them in. Maybe we can get both series in, but I thought decoupling
them might make it more manageable if not.

Regardless, the blurb:

This series is two small changes enable kernel support for controlling the RMII
RCLK gate on AST2600-based systems. RMII is commonly used for NCSI, which
itself is commonly used for BMC-based designs to reduce cabling requirements
for the platform. NCSI support for the AST2600 is not yet implemented in
u-boot and so unlike the AST2500 the kernel can't rely on RCLK already being
ungated.

v2: Rename some macros and clocks based on feedback from Joel

v1 can be found here: https://lore.kernel.org/linux-clk/20191008113553.13662-1-andrew@aj.id.au/

Please review!

Andrew

Andrew Jeffery (2):
  dt-bindings: clock: Add AST2600 RMII RCLK gate definitions
  clk: ast2600: Add RMII RCLK gates for all four MACs

 drivers/clk/clk-ast2600.c                 | 47 ++++++++++++++++++++++-
 include/dt-bindings/clock/ast2600-clock.h |  4 ++
 2 files changed, 50 insertions(+), 1 deletion(-)

-- 
2.20.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH v2 1/2] dt-bindings: clock: Add AST2600 RMII RCLK gate definitions
  2019-10-10  2:07 [PATCH v2 0/2] clk: ast2600: Expose RMII RCLK for MACs 1-4 Andrew Jeffery
@ 2019-10-10  2:07 ` Andrew Jeffery
  2019-10-10 23:42   ` Joel Stanley
  2019-10-11 17:01   ` Rob Herring
  2019-10-10  2:07 ` [PATCH v2 2/2] clk: ast2600: Add RMII RCLK gates for all four MACs Andrew Jeffery
  1 sibling, 2 replies; 6+ messages in thread
From: Andrew Jeffery @ 2019-10-10  2:07 UTC (permalink / raw)
  To: linux-clk
  Cc: mturquette, sboyd, joel, robh+dt, mark.rutland, linux-arm-kernel,
	linux-aspeed, linux-kernel, devicetree

The AST2600 has an explicit gate for the RMII RCLK for each of the four
MACs.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
 include/dt-bindings/clock/ast2600-clock.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
index 38074a5f7296..62b9520a00fd 100644
--- a/include/dt-bindings/clock/ast2600-clock.h
+++ b/include/dt-bindings/clock/ast2600-clock.h
@@ -83,6 +83,10 @@
 #define ASPEED_CLK_MAC12		64
 #define ASPEED_CLK_MAC34		65
 #define ASPEED_CLK_USBPHY_40M		66
+#define ASPEED_CLK_MAC1RCLK		67
+#define ASPEED_CLK_MAC2RCLK		68
+#define ASPEED_CLK_MAC3RCLK		69
+#define ASPEED_CLK_MAC4RCLK		70
 
 /* Only list resets here that are not part of a gate */
 #define ASPEED_RESET_ADC		55
-- 
2.20.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH v2 2/2] clk: ast2600: Add RMII RCLK gates for all four MACs
  2019-10-10  2:07 [PATCH v2 0/2] clk: ast2600: Expose RMII RCLK for MACs 1-4 Andrew Jeffery
  2019-10-10  2:07 ` [PATCH v2 1/2] dt-bindings: clock: Add AST2600 RMII RCLK gate definitions Andrew Jeffery
@ 2019-10-10  2:07 ` Andrew Jeffery
  2019-10-10 23:43   ` Joel Stanley
  1 sibling, 1 reply; 6+ messages in thread
From: Andrew Jeffery @ 2019-10-10  2:07 UTC (permalink / raw)
  To: linux-clk
  Cc: mturquette, sboyd, joel, robh+dt, mark.rutland, linux-arm-kernel,
	linux-aspeed, linux-kernel, devicetree

RCLK is a fixed 50MHz clock derived from HPLL/HCLK that is described by a
single gate for each MAC.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
 drivers/clk/clk-ast2600.c | 47 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 46 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
index 1c1bb39bb04e..85acc7cdc83c 100644
--- a/drivers/clk/clk-ast2600.c
+++ b/drivers/clk/clk-ast2600.c
@@ -15,7 +15,7 @@
 
 #include "clk-aspeed.h"
 
-#define ASPEED_G6_NUM_CLKS		67
+#define ASPEED_G6_NUM_CLKS		71
 
 #define ASPEED_G6_SILICON_REV		0x004
 
@@ -40,6 +40,9 @@
 
 #define ASPEED_G6_STRAP1		0x500
 
+#define ASPEED_MAC12_CLK_DLY		0x340
+#define ASPEED_MAC34_CLK_DLY		0x350
+
 /* Globally visible clocks */
 static DEFINE_SPINLOCK(aspeed_g6_clk_lock);
 
@@ -485,6 +488,11 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
 		return PTR_ERR(hw);
 	aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw;
 
+	/* MAC1/2 RMII 50MHz RCLK */
+	hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0, 50000000);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+
 	/* MAC1/2 AHB bus clock divider */
 	hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0,
 			scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0,
@@ -494,6 +502,27 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
 		return PTR_ERR(hw);
 	aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw;
 
+	/* RMII1 50MHz (RCLK) output enable */
+	hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
+			scu_g6_base + ASPEED_MAC12_CLK_DLY, 29, 0,
+			&aspeed_g6_clk_lock);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+	aspeed_g6_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw;
+
+	/* RMII2 50MHz (RCLK) output enable */
+	hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
+			scu_g6_base + ASPEED_MAC12_CLK_DLY, 30, 0,
+			&aspeed_g6_clk_lock);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+	aspeed_g6_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw;
+
+	/* MAC1/2 RMII 50MHz RCLK */
+	hw = clk_hw_register_fixed_rate(dev, "mac34rclk", "hclk", 0, 50000000);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+
 	/* MAC3/4 AHB bus clock divider */
 	hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0,
 			scu_g6_base + 0x310, 24, 3, 0,
@@ -503,6 +532,22 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
 		return PTR_ERR(hw);
 	aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw;
 
+	/* RMII3 50MHz (RCLK) output enable */
+	hw = clk_hw_register_gate(dev, "mac3rclk", "mac34rclk", 0,
+			scu_g6_base + ASPEED_MAC34_CLK_DLY, 29, 0,
+			&aspeed_g6_clk_lock);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+	aspeed_g6_clk_data->hws[ASPEED_CLK_MAC3RCLK] = hw;
+
+	/* RMII4 50MHz (RCLK) output enable */
+	hw = clk_hw_register_gate(dev, "mac4rclk", "mac34rclk", 0,
+			scu_g6_base + ASPEED_MAC34_CLK_DLY, 30, 0,
+			&aspeed_g6_clk_lock);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+	aspeed_g6_clk_data->hws[ASPEED_CLK_MAC4RCLK] = hw;
+
 	/* LPC Host (LHCLK) clock divider */
 	hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
 			scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
-- 
2.20.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH v2 1/2] dt-bindings: clock: Add AST2600 RMII RCLK gate definitions
  2019-10-10  2:07 ` [PATCH v2 1/2] dt-bindings: clock: Add AST2600 RMII RCLK gate definitions Andrew Jeffery
@ 2019-10-10 23:42   ` Joel Stanley
  2019-10-11 17:01   ` Rob Herring
  1 sibling, 0 replies; 6+ messages in thread
From: Joel Stanley @ 2019-10-10 23:42 UTC (permalink / raw)
  To: Andrew Jeffery
  Cc: linux-clk, Michael Turquette, Stephen Boyd, Rob Herring,
	Mark Rutland, Linux ARM, linux-aspeed, Linux Kernel Mailing List,
	devicetree

On Thu, 10 Oct 2019 at 02:06, Andrew Jeffery <andrew@aj.id.au> wrote:
>
> The AST2600 has an explicit gate for the RMII RCLK for each of the four
> MACs.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>

Reviewed-by: Joel Stanley <joel@jms.id.au>

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH v2 2/2] clk: ast2600: Add RMII RCLK gates for all four MACs
  2019-10-10  2:07 ` [PATCH v2 2/2] clk: ast2600: Add RMII RCLK gates for all four MACs Andrew Jeffery
@ 2019-10-10 23:43   ` Joel Stanley
  0 siblings, 0 replies; 6+ messages in thread
From: Joel Stanley @ 2019-10-10 23:43 UTC (permalink / raw)
  To: Andrew Jeffery
  Cc: linux-clk, Michael Turquette, Stephen Boyd, Rob Herring,
	Mark Rutland, Linux ARM, linux-aspeed, Linux Kernel Mailing List,
	devicetree

On Thu, 10 Oct 2019 at 02:06, Andrew Jeffery <andrew@aj.id.au> wrote:
>
> RCLK is a fixed 50MHz clock derived from HPLL/HCLK that is described by a
> single gate for each MAC.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>

Reviewed-by: Joel Stanley <joel@jms.id.au>

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH v2 1/2] dt-bindings: clock: Add AST2600 RMII RCLK gate definitions
  2019-10-10  2:07 ` [PATCH v2 1/2] dt-bindings: clock: Add AST2600 RMII RCLK gate definitions Andrew Jeffery
  2019-10-10 23:42   ` Joel Stanley
@ 2019-10-11 17:01   ` Rob Herring
  1 sibling, 0 replies; 6+ messages in thread
From: Rob Herring @ 2019-10-11 17:01 UTC (permalink / raw)
  To: Andrew Jeffery
  Cc: linux-clk, mturquette, sboyd, joel, robh+dt, mark.rutland,
	linux-arm-kernel, linux-aspeed, linux-kernel, devicetree

On Thu, 10 Oct 2019 12:37:24 +1030, Andrew Jeffery wrote:
> The AST2600 has an explicit gate for the RMII RCLK for each of the four
> MACs.
> 
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
>  include/dt-bindings/clock/ast2600-clock.h | 4 ++++
>  1 file changed, 4 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 6+ messages in thread

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Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-10  2:07 [PATCH v2 0/2] clk: ast2600: Expose RMII RCLK for MACs 1-4 Andrew Jeffery
2019-10-10  2:07 ` [PATCH v2 1/2] dt-bindings: clock: Add AST2600 RMII RCLK gate definitions Andrew Jeffery
2019-10-10 23:42   ` Joel Stanley
2019-10-11 17:01   ` Rob Herring
2019-10-10  2:07 ` [PATCH v2 2/2] clk: ast2600: Add RMII RCLK gates for all four MACs Andrew Jeffery
2019-10-10 23:43   ` Joel Stanley

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